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陈春
2025-09-29 16:47:12 +08:00
parent 2d906350bf
commit 0a4832db5e
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A5H_9225_8108_SPIV3.0/HY88xx/hy8612.h
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#ifndef __HY8612_H
#define __HY8612_H
#ifdef HY8612
#define CH_NUMBERS 12
#define PWM_OFFSET 0
#define BTI_WIDTH 16
//0x41
#define TP_NUM_SEL_Pos 0
#define TP_NUM_SEL_14BIT_TP 0
#define TP_NUM_SEL_13BIT_TP 1
#define TP_NUM_SEL_12BIT_TP 2
#define TP_NUM_SEL_11BIT_TP 3
#define TP_NUM_SEL_10BIT_TP 4
#define TP_NUM_SEL_9BIT_TP 5
#define TP_NUM_SEL_8BIT_TP 6
#define TP_NUM_SEL_6BIT_TP 7
#define TP_NUM_SEL (TP_NUM_SEL_14BIT_TP<<TP_NUM_SEL_Pos)
#define HT_DITHER_NUM_Pos 4
#define HT_DITHER_NUM_0BIT_DITHER 0
#define HT_DITHER_NUM_1BIT_DITHER 1
#define HT_DITHER_NUM_2BIT_DITHER 2
#define HT_DITHER_NUM_3BIT_DITHER 3
#define HT_DITHER_NUM_4BIT_DITHER 4
#define HT_DITHER_NUM_5BIT_DITHER 5
#define HT_DITHER_NUM_6BIT_DITHER 6
#define HT_DITHER_NUM (HT_DITHER_NUM_0BIT_DITHER<<HT_DITHER_NUM_Pos)
//0x47
#define HEADROOM_Pos 0
#define HEADROOM_150MV 0
#define HEADROOM_200MV 1
#define HEADROOM_300MV 2
#define HEADROOM_400MV 3
#define HEADROOM_450MV 4
#define HEADROOM_500MV 5
#define HEADROOM_550MV 6
#define HEADROOM_600MV 7
#define HEADROOM_700MV 8
#define HEADROOM_750MV 9
#define HEADROOM_800MV 10
#define HEADROOM_900MV 11
#define HEADROOM_1000MV 12
#define HEADROOM_1100MV 13
#define HEADROOM_1200MV 14
#define HEADROOM_1300MV 15
#define HEADROOM (HEADROOM_500MV<<HEADROOM_Pos) //headroom<6F><6D><EFBFBD><EFBFBD>
//0x48
#define CLK_DIP_ALWAYS_ON_Pos 0
#define CLK_DIP_ALWAYS_ON (0<<CLK_DIP_ALWAYS_ON_Pos)
#define CLK_DIS_ALWAYS_ON_Pos 1
#define CLK_DIS_ALWAYS_ON (0<<CLK_DIS_ALWAYS_ON_Pos)
#define OPEN_LV_Pos 2
#define OPEN_LV_50MV 0
#define OPEN_LV_80MV 1
#define OPEN_LV_100MV 2
#define OPEN_LV_130MV 3
#define OPEN_LV (OPEN_LV_80MV<<OPEN_LV_Pos) //<2F><><EFBFBD><EFBFBD>open<65><6E><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5>ѹ
#define RISE_FALL_Pos 4
#define RISE_FALL_TIME_0_3US 0
#define RISE_FALL_TIME_0_6US 1
#define RISE_FALL_TIME_1US 2
#define RISE_FALL_TIME_1_6US 3
#define RISE_FALL_TIME (RISE_FALL_TIME_1_6US<<RISE_FALL_Pos) //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>/<2F>½<EFBFBD><C2BD><EFBFBD>ʱ<EFBFBD><CAB1>
#define BURST_Pos 9
#define BURST_DIS 0
#define BURST_EN 1
#define BURST (BURST_DIS<<BURST_Pos) //DC*133%
#define OPEN_DEBOUNCE_TIME_Pos 13
#define OPEN_DEBOUNCE_TIME_3_TPWM 0
#define OPEN_DEBOUNCE_TIME_4_TPWM 1
#define OPEN_DEBOUNCE_TIME_8_TPWM 2
#define OPEN_DEBOUNCE_TIME_16_TPWM 3
#define OPEN_DEBOUNCE_TIME_32_TPWM 4
#define OPEN_DEBOUNCE_TIME_64_TPWM 5
#define OPEN_DEBOUNCE_TIME_96_TPWM 6
#define OPEN_DEBOUNCE_TIME_128_TPWM 7
#define OPEN_DEBOUNCE_TIME (OPEN_DEBOUNCE_TIME_16_TPWM<<OPEN_DEBOUNCE_TIME_Pos) //<2F><><EFBFBD><EFBFBD>open<65><6E><EFBFBD>ϼ<EFBFBD><CFBC><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
//0x49
#define READ_BACK_EOP_DOS_FRE_Pos 11
#define READ_BACK_EOP_DOS_FRE_500K 0
#define READ_BACK_EOP_DOS_FRE_1M 1
#define READ_BACK_EOP_DOS_FRE_2M 2
#define READ_BACK_EOP_DOS_FRE_3M 3
#define READ_BACK_EOP_DOS_FRE (READ_BACK_EOP_DOS_FRE_2M << READ_BACK_EOP_DOS_FRE_Pos)
#define UART_TC_FREQ_Pos 13
#define UART_TC_FREQ_19200 0
#define UART_TC_FREQ_38400 1
#define UART_TC_FREQ_57600 2
#define UART_TC_FREQ_115200 4
#define UART_TC_FREQ_230400 5
#define UART_TC_FREQ_460800 6
#define UART_TC_FREQ_921600 7
#define UART_TC_FREQ (UART_TC_FREQ_115200<<UART_TC_FREQ_Pos)
//0x4A
#define OTP_LV_Pos 1
#define OTP_LV_155 0
#define OTP_LV_145 1
#define OTP_LV_135 2
#define OTP_LV_125 3
#define OTP_LV (OTP_LV_145<<OTP_LV_Pos) //<2F><><EFBFBD><EFBFBD>OTP<54><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
#define OTP_RECOVERY_Pos 3
#define OTP_RECOVERY_155 0
#define OTP_RECOVERY_145 1
#define OTP_RECOVERY_135 2
#define OTP_RECOVERY_125 3
#define OTP_RECOVERY (OTP_RECOVERY_145<<OTP_RECOVERY_Pos) //<2F><><EFBFBD><EFBFBD>OTP<54>ָ<EFBFBD><D6B8><EFBFBD>ֵ
#define SPIKE_FILTER_Pos 5
#define SPIKE_FILTER_2P2NS 0
#define SPIKE_FILTER_4P2NS 1
#define SPIKE_FILTER (SPIKE_FILTER_2P2NS<<SPIKE_FILTER_Pos) //<2F><><EFBFBD><EFBFBD><EFBFBD>źŵļ<C5B5><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define SPIKE_EN_Pos 6
#define SPIKE_EN_BYPASS 0
#define SPIKE_EN_ENABLE 1
#define SPIKE_EN (SPIKE_EN_BYPASS<<SPIKE_EN_Pos) //<2F>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>źŵļ<C5B5><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˹<EFBFBD><CBB9><EFBFBD>
#define DEGLITCH_TIME_Pos 7
#define DEGLITCH_TIME_2TOSC 0
#define DEGLITCH_TIME_4TOSC 1
#define DEGLITCH_TIME_8TOSC 2
#define DEGLITCH_TIME_32TOSC 3
#define DEGLITCH_TIME (DEGLITCH_TIME_2TOSC<<DEGLITCH_TIME_Pos) //<2F><><EFBFBD><EFBFBD>dither<65><72>λ<EFBFBD><CEBB>
#define ANALOG_MOP_Pos 10
#define ANALOG_100 0
#define ANALOG_75 1
#define ANALOG_50 2
#define ANALOG_25 3
#define ANALOG_MOP (ANALOG_100<<ANALOG_MOP_Pos)
//0x4C
#define CHANNEL_GPOUPING_Pos 0
#define CHANNEL_GROUP_NO 0
#define CHANNEL_GROUP_2_CHANNEL 1
#define CHANNEL_GROUP_4_CHANNEL 2
#define CHANNEL_GPOUPING (CHANNEL_GROUP_NO<<CHANNEL_GPOUPING_Pos)
#define FAULT_DEGLITCH_TIME_Pos 3
#define FAULT_DEGLITCH_TIME_0P5US 0
#define FAULT_DEGLITCH_TIME_1US 1
#define FAULT_DEGLITCH_TIME_2US 2
#define FAULT_DEGLITCH_TIME_3US 3
#define FAULT_DEGLITCH_TIME (FAULT_DEGLITCH_TIME_1US<<FAULT_DEGLITCH_TIME_Pos)
#define DOS_OUTPUT_Pos 5
#define DOS_HIZ 0
#define DOS_OUTPUT 1
#define DOS_OUTPUT_MODE (DOS_OUTPUT<<DOS_OUTPUT_Pos)
#define OH_DERATING_INC_STEP_Pos 6
#define OH_DERATING_INC_STEP 0
#define FAULT_BLANK_TIME_Pos 10
#define FAULT_BLANK_TIME (0<<FAULT_BLANK_TIME_Pos) //BLANK time<6D><65><EFBFBD><EFBFBD>
//0x4D
#define OH_TRIGGER_Pos 0
#define OH_TRIGGER_VALUT (8<<OH_TRIGGER_Pos) //145-5*N
#define OH_RECOVER_Pos 5
#define OH_RECOVER_VALUT (10<<OH_RECOVER_Pos) //145-5*N
#define OH_DERATING_DEC_STEP_Pos 10
#define OH_DERATING_DEC_STEP (0<<OH_DERATING_DEC_STEP_Pos)
#define OH_DERATING_ADJUST_FREQ_Pos 14
#define OH_DERATING_ADJUST_FREQ_4 0
#define OH_DERATING_ADJUST_FREQ_16 0
#define OH_DERATING_ADJUST_FREQ_64 0
#define OH_DERATING_ADJUST_FREQ_128 0
#define OH_DERATING_ADJUST_FREQ (OH_DERATING_ADJUST_FREQ_4<<OH_DERATING_ADJUST_FREQ_Pos)
//0x4E
#define PWM_CHANNEL_CLOCK_Pos 0
#define PWM_CHANNEL_CLOCK_3P84K 0
#define PWM_CHANNEL_CLOCK (PWM_CHANNEL_CLOCK_3P84K << PWM_CHANNEL_CLOCK_Pos)
#define PWM_CHANNEL_CLOCK_20K_Pos 8
#define PWM_CHANNEL_CLOCK_20K_EN 1
#define PWM_CHANNEL_CLOCK_20K_DIS 0
#define PWM_CHANNEL_CLOCK_20K (PWM_CHANNEL_CLOCK_20K_EN << PWM_CHANNEL_CLOCK_20K_Pos)
#define SHORT_LV_Pos 9
#define SHORT_LV_2V 0
#define SHORT_LV_3V 1
#define SHORT_LV_4V 2
#define SHORT_LV_5V 3
#define SHORT_LV_6V 4
#define SHORT_LV_7V 5
#define SHORT_LV_9V 6
#define SHORT_LV_12V 7
#define SHORT_LV (SHORT_LV_12V<<SHORT_LV_Pos) //<2F><><EFBFBD>ö<EFBFBD>·<EFBFBD><C2B7>ֵ
#define OPEN_DEBOUNCE_Pos 12
#define OPEN_DEBOUNCE_SEL_EOP 0
#define OPEN_DEBOUNCE_SEL_PWM 1
#define OPEN_DEBOUNCE (OPEN_DEBOUNCE_SEL_EOP<<OPEN_DEBOUNCE_Pos) //<2F><><EFBFBD><EFBFBD>open<65><6E><EFBFBD><EFBFBD><EFBFBD>ο<EFBFBD>EOP<4F><50><EFBFBD><EFBFBD>PWM
#define BFI_MODE_Pos 13
#define BFI_RESERVE_FIRST 0
#define BFI_BLANK_FIRST 1
#define BFI_MODE (BFI_RESERVE_FIRST<<BFI_MODE_Pos) //BFIģʽ<C4A3><CABD><EFBFBD><EFBFBD>
#define BFI_Pos 14
#define BFI_ENABLE 1
#define BFI_DISABLE 0
#define BFI (BFI_DISABLE<<BFI_Pos) //<2F>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD>BFIģʽ
#define SLEEP_MODE_EXIT_Pos 15
#define SLEEP_MODE_EXIT_NO_RECOVERY 0
#define SLEEP_MODE_EXIT_RECOVERY 1
#define SLEEP_MODE_EXIT (SLEEP_MODE_EXIT_RECOVERY<<SLEEP_MODE_EXIT_Pos) //<2F>˳<EFBFBD>˯<EFBFBD><CBAF>ģʽʱ<CABD><CAB1><EFBFBD>Ƿ<EFBFBD><C7B7>ָ<EFBFBD><D6B8><EFBFBD>һ֡<D2BB><D6A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//0x4F
#define BFI_NUMBER_Pos 0
#define BFI_NUMBER (1<<BFI_NUMBER_Pos) //9BITS BFI<46><49><EFBFBD>õ<EFBFBD>PWM<57><4D><EFBFBD><EFBFBD>
//0x7B
#define GLOBAL_DAC_Pro 0
#define GLOBAL_DAC (32<<GLOBAL_DAC_Pro) //12+N*0.57ma
//0x46
#define SICK_FAULT_DISABLE 0 // 0:Enable sick dection 1:Disable sick dection
#define OPEN_FALUT_DISABLE 0 // 0:Enable open dection 1:Disable open dection
#define SHORT_FAULT_DISABLE 0 // 0:Enable short dection 1:Disable short dection
#define OTP_FAULT_DISABLE 0 // 0:Enable OTP dection 1:Disable OTP dection
#define OTP_OFF_DISABLE 0 // 0:Turn off pwm when OTP 1:not turn off pwm when OTP
#define OTP_REC_DISABLE 0 // 0:recovery pwm when OTP relieve 1:not auto recovery pwm when OTP relieve
#define OPEN_OFF_DISABLE 1 // 0:turn off pwm when open fault detected 1:not turn off pwm when open fault detected
#define SHORT_OFF_DISABLE 0 // 0:turn off pwm when short fault detected 1:not turn off pwm when short fault detected
#define DIP_CRC_CHECK_DISABLE 0 // 0:enable double-wire CRC check 1:disable double-wire CRC check
#define PWM_HIGH_TIME_FAULT_DISABLE 0 // 0:enable pwm high time detect function 1:disable pwm high time detect function
#define OH_DISABLE 0
#define SICK_RANGE_SEL 0 // 0:sick detection related to open 1:sick detection not related to open
#define DIS_DOS_CRC 0 // 0:enable dis-dos communication CRC check 1:disable dis-dos communication CRC check
#define OH_DERATING_ENABLE 0
#define CONFIG_DONE 1
#endif
#endif