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陈春
2025-09-29 16:47:12 +08:00
parent 2d906350bf
commit 0a4832db5e
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A5H_9225_8108_SPIV3.0/HY88xx/hy8811.h
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#ifndef __HY8811_H
#define __HY8811_H
#ifdef HY8811
#define CH_NUMBERS 4
#define PWM_OFFSET 2
#define BTI_WIDTH 20
//0x48
#define DC_RANGE_Pos 0
#define DC_RANGE_24MA 0
#define DC_RANGE_36MA 0
#define DC_RANGE_60MA 1
#define DC_RANGE_72MA 2
#define DC_RANGE (DC_RANGE_72MA<<DC_RANGE_Pos) //<2F><><EFBFBD>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5>Χ
#define OPEN_LV_Pos 2
#define OPEN_LV_50MV 0
#define OPEN_LV_80MV 1
#define OPEN_LV_100MV 2
#define OPEN_LV_130MV 3
#define OPEN_LV (OPEN_LV_80MV<<OPEN_LV_Pos) //<2F><><EFBFBD><EFBFBD>open<65><6E><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5>ѹ
#define RISE_FALL_TIME_Pos 4
#define RISE_FALL_TIME_0_3US 0
#define RISE_FALL_TIME_0_6US 1
#define RISE_FALL_TIME_1US 2
#define RISE_FALL_TIME_1_6US 3
#define RISE_FALL_TIME (RISE_FALL_TIME_1_6US<<RISE_FALL_TIME_Pos) //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>/<2F>½<EFBFBD><C2BD><EFBFBD>ʱ<EFBFBD><CAB1>
#define DERATING_Pos 6
#define DERATING_NO 0
#define DERATING_50 1
#define DERATING_25 2
#define DERATING_12_5 3
#define DERATING (DERATING_NO<<DERATING_Pos) //<2F><><EFBFBD>÷<EFBFBD><C3B7><EFBFBD>OHʱ<48><CAB1>DC˥<43><CBA5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define CHANNEL_DELAY_UPDATE_Pos 8
#define CHANNEL_DELAY_UPDATE_WAIT_PWM 0
#define CHANNEL_DELAY_UPDATE_IMMEDIATELY 1
#define CHANNEL_DELAY_UPDATE (CHANNEL_DELAY_UPDATE_WAIT_PWM<<CHANNEL_DELAY_UPDATE_Pos) //<2F><><EFBFBD><EFBFBD>dimming<6E><67><EFBFBD>ݺ<EFBFBD>ʱ<EFBFBD><CAB1>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ֡PWM<57><4D><EFBFBD><EFBFBD>
#define DOS_OUT_OH_Pos 9
#define DOS_OUTPUT_OH_LOCKED 0
#define DOS_OUTPUT_OH_REAL 1
#define DOS_OUTPUT_OH_SEL (DOS_OUTPUT_OH_LOCKED<<DOS_OUT_OH_Pos) //<2F><><EFBFBD>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD>OH<4F><48><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>DOS״̬
#define FAULT_SAMPLE_BFI_Pos 10
#define FAULT_SAMPLE_BFI_ENABLE 0
#define FAULT_SAMPLE_BFI_DISABLE 1
#define FAULT_SAMPLE_BFI (FAULT_SAMPLE_BFI_ENABLE<<FAULT_SAMPLE_BFI_Pos) //<2F><><EFBFBD><EFBFBD>BFIģʽ<C4A3>£<EFBFBD><C2A3>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϼ<EFBFBD><CFBC><EFBFBD><EFBFBD>Ƚ<EFBFBD><C8BD><EFBFBD>
#define OPEN_DEBOUNCE_TIME_Pos 13
#define OPEN_DEBOUNCE_TIME_3_TPWM 0
#define OPEN_DEBOUNCE_TIME_4_TPWM 1
#define OPEN_DEBOUNCE_TIME_8_TPWM 2
#define OPEN_DEBOUNCE_TIME_16_TPWM 3
#define OPEN_DEBOUNCE_TIME_32_TPWM 4
#define OPEN_DEBOUNCE_TIME_64_TPWM 5
#define OPEN_DEBOUNCE_TIME_96_TPWM 6
#define OPEN_DEBOUNCE_TIME_128_TPWM 7
#define OPEN_DEBOUNCE_TIME (OPEN_DEBOUNCE_TIME_64_TPWM<<OPEN_DEBOUNCE_TIME_Pos) //<2F><><EFBFBD><EFBFBD>open<65><6E><EFBFBD>ϼ<EFBFBD><CFBC><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
//0x4A
#define OTP_LV_Pos 0
#define OTP_LV_155 0
#define OTP_LV_145 1
#define OTP_LV_135 2
#define OTP_LV_125 3
#define OTP_LV (OTP_LV_145<<OTP_LV_Pos) //<2F><><EFBFBD><EFBFBD>OTP<54><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
#define SHORT_DET_DAC_Pos 2
#define SHORT_DET_DAC_ENABLE 0
#define SHORT_DET_DAC_DISABLE 1
#define SHORT_DET_DAC (SHORT_DET_DAC_ENABLE<<SHORT_DET_DAC_Pos) //short<72><74><EFBFBD>ϼ<EFBFBD><CFBC><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD>ҪDAC<41><43>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>
#define IDAC_REF_Pos 3
#define IDAC_REF_130MV 0
#define IDAC_REF_150MV 1
#define IDAC_REF_220MV 2
#define IDAC_REF_260MV 3
#define IDAC_REF (IDAC_REF_260MV<<IDAC_REF_Pos) //<2F><><EFBFBD><EFBFBD>IDAC<41><43>ѹ<EFBFBD><D1B9><EFBFBD>Ż<EFBFBD>headroom<6F><6D>һ<EFBFBD><D2BB>ʹ<EFBFBD><CAB9>Ĭ<EFBFBD><C4AC>ֵ<EFBFBD><D6B5>
#define SPIKE_FILTER_TIME_Pos 5
#define SPIKE_FILTER_TIME_1NS 0
#define SPIKE_FILTER_TIME_2NS 1
#define SPIKE_FILTER_TIME (SPIKE_FILTER_TIME_1NS<<SPIKE_FILTER_TIME_Pos) //<2F><><EFBFBD><EFBFBD><EFBFBD>źŵļ<C5B5><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define SPIKE_FILTER_Pos 6
#define SPIKE_FILTER_BYPASS 0
#define SPIKE_FILTER_ENABLE 1
#define SPIKE_FILTER (SPIKE_FILTER_BYPASS<<SPIKE_FILTER_Pos) //<2F>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>źŵļ<C5B5><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˹<EFBFBD><CBB9><EFBFBD>
#define ONE_WIRE_DEGLITCH_TIME_Pos 7
#define ONE_WIRE_DEGLITCH_TIME_2_TOSC 0
#define ONE_WIRE_DEGLITCH_TIME_4_TOSC 1
#define ONE_WIRE_DEGLITCH_TIME_8_TOSC 2
#define ONE_WIRE_DEGLITCH_TIME_32_TOSC 3
#define ONE_WIRE_DEGLITCH_TIME (ONE_WIRE_DEGLITCH_TIME_4_TOSC<<ONE_WIRE_DEGLITCH_TIME_Pos) //DIP/DIS<49>ķ<EFBFBD><C4B7><EFBFBD>ʱ<EFBFBD><CAB1>
#define ADDRESS_DEBUG_MODE_Pos 9
#define ADDRESS_DEBUG_DISABLE 0
#define ADDRESS_DEBUG_ENABLE 1
#define ADDRESS_DEBUG_MODE (ADDRESS_DEBUG_DISABLE<<ADDRESS_DEBUG_MODE_Pos) //<2F>Ƿ<EFBFBD>ʹ<EFBFBD>ܵ<EFBFBD>ַdebugģʽ
#define MOPICC_CONFIG_Pos 10
#define MOPICC_CONFIG_100 0
#define MOPICC_CONFIG_75 1
#define MOPICC_CONFIG_50 2
#define MOPICC_CONFIG_25 3
#define MOPICC_CONFIG_25_1 4
#define MOPICC_CONFIG_18_75 5
#define MOPICC_CONFIG_12_5 6
#define MOPICC_CONFIG_6_25 7
#define MOPICC_CONFIG (MOPICC_CONFIG_100<<MOPICC_CONFIG_Pos) //һ<><D2BB>ʹ<EFBFBD><CAB9>Ĭ<EFBFBD><C4AC>ֵ
#define SHORT_DETECTION_THRESHOLD_Pos 13
#define SHORT_DETECTION_THRESHOLD_4 0
#define SHORT_DETECTION_THRESHOLD_8 1
#define SHORT_DETECTION_THRESHOLD_16 2
#define SHORT_DETECTION_THRESHOLD_31 3
#define SHORT_DETECTION_THRESHOLD (SHORT_DETECTION_THRESHOLD_4<<SHORT_DETECTION_THRESHOLD_Pos) //short<72><74>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define PWM_DITHER_Pos 15
#define PWM_DITHER_DISABLE 0
#define PWM_DITHER_ENABLE 1
#define PWM_DITHER (PWM_DITHER_DISABLE<<PWM_DITHER_Pos) //<2F>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9>ditherģʽ
//0x4C
#define OH_LV_Pos 0
#define OH_LV_115__105 0
#define OH_LV_105__95 1
#define OH_LV_95__85 2
#define OH_LV_85__75 3
#define OH_LV (OH_LV_105__95<<OH_LV_Pos) //OH<4F><48>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>
#define SHORT_FIX_PWM_Pos 2
#define SHORT_FIX_PWM_DISABLE 0
#define SHORT_FIX_PWM_ENABLE 1
#define SHORT_FIX_PWM (SHORT_FIX_PWM_DISABLE<<SHORT_FIX_PWM_Pos) //<2F><><EFBFBD><EFBFBD>short<72><74><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>Ƿ<EFBFBD>ǿ<EFBFBD><C7BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PWMdutyΪ10%
#define FAULT_DEGLITCH_TIME_Pos 3
#define FAULT_DEGLITCH_TIME_0_5US 0
#define FAULT_DEGLITCH_TIME_1US 1
#define FAULT_DEGLITCH_TIME_2US 2
#define FAULT_DEGLITCH_TIME_3US 3
#define FAULT_DEGLITCH_TIME (FAULT_DEGLITCH_TIME_1US<<FAULT_DEGLITCH_TIME_Pos) //<2F><><EFBFBD>ϼ<EFBFBD><CFBC><EFBFBD><EFBFBD>ķ<EFBFBD><C4B7><EFBFBD>ʱ<EFBFBD><CAB1>
#define DOS_MODE_Pos 5
#define DOS_MODE_OPEN_DRAIN 0
#define DOS_MODE_CMOS 1
#define DOS_MODE (DOS_MODE_CMOS<<DOS_MODE_Pos) //DOS<4F>ܽŵ<DCBD><C5B5><EFBFBD><EFBFBD><EFBFBD>ģʽ
#define CHANNEL_GPOUPING_Pos 6
#define CHANNEL_GROUP_NO 0
#define CHANNEL_GROUP_2_CHANNEL 1
#define CHANNEL_GROUP_4_CHANNEL 2
#define CHANNEL_GPOUPING (CHANNEL_GROUP_NO<<CHANNEL_GPOUPING_Pos) //CH<43>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD>з<EFBFBD><D0B7><EFBFBD>
#define MIX_DC_LSB_Pos 8
#define MIX_DC_LSB_0 0
#define MIX_DC_LSB_1 1
#define MIX_DC_LSB (MIX_DC_LSB_0<<MIX_DC_LSB_Pos) //DCֵ<43><D6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>ֵ
#define MIX_PWM_LSB_Pos 9
#define MIX_PWM_LSB_0 0
#define MIX_PWM_LSB_1 1
#define MIX_PWM_LSB (MIX_PWM_LSB_0<<MIX_PWM_LSB_Pos) //PWM<57><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>ֵ
#define FAULT_BLANK_TIME_Pos 10
#define FAULT_BLANK_TIME (10<<FAULT_BLANK_TIME_Pos) //(4*N+3) * Tclock_pwm (duty:0.3% ~ 24.9%) //6bits //BLANK time<6D><65><EFBFBD><EFBFBD>
//0x4E
#define PWM_CHANNEL_CLK_DIVIDED_Pos 0
#define PWM_CHANNEL_CLK_DIVIDED (7<<PWM_CHANNEL_CLK_DIVIDED_Pos) //<2F><><EFBFBD><EFBFBD>PWMƵ<4D>ʷ<EFBFBD>Ƶϵ<C6B5><CFB5>
#define PWM_CLK_SEL_Pos 8
#define PWM_CLK_SEL_DIVEDED_CLK 0
#define PWM_CLK_SEL_20480HZ 1
#define PWM_CLK_SEL (PWM_CLK_SEL_DIVEDED_CLK<<PWM_CLK_SEL_Pos) //<2F>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD>PWMƵ<4D><C6B5>Ϊ20.48K
#define SHORT_LV_Pos 9
#define SHORT_LV_2V 0
#define SHORT_LV_3V 1
#define SHORT_LV_4V 2
#define SHORT_LV_5V 3
#define SHORT_LV_6V 4
#define SHORT_LV_7V 5
#define SHORT_LV_9V 6
#define SHORT_LV_12V 7
#define SHORT_LV (SHORT_LV_9V<<SHORT_LV_Pos) //<2F><><EFBFBD>ö<EFBFBD>·<EFBFBD><C2B7>ֵ
#define OPEN_DEBOUNCE_Pos 12
#define OPEN_DEBOUNCE_SEL_EOP 0
#define OPEN_DEBOUNCE_SEL_PWM 1
#define OPEN_DEBOUNCE (OPEN_DEBOUNCE_SEL_PWM<<OPEN_DEBOUNCE_Pos) //<2F><><EFBFBD><EFBFBD>open<65><6E><EFBFBD><EFBFBD><EFBFBD>ο<EFBFBD>EOP<4F><50><EFBFBD><EFBFBD>PWM
#define BFI_MODE_Pos 13
#define BFI_RESERVE_FIRST 0
#define BFI_BLANK_FIRST 1
#define BFI_MODE (BFI_RESERVE_FIRST<<BFI_MODE_Pos) //BFIģʽ<C4A3><CABD><EFBFBD><EFBFBD>
#define BFI_Pos 14
#define BFI_ENABLE 1
#define BFI_DISABLE 0
#define BFI (BFI_DISABLE<<BFI_Pos) //<2F>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD>BFIģʽ
#define SLEEP_MODE_EXIT_Pos 15
#define SLEEP_MODE_EXIT_NO_RECOVERY 0
#define SLEEP_MODE_EXIT_RECOVERY 1
#define SLEEP_MODE_EXIT (SLEEP_MODE_EXIT_RECOVERY<<SLEEP_MODE_EXIT_Pos)//<2F>˳<EFBFBD>˯<EFBFBD><CBAF>ģʽʱ<CABD><CAB1><EFBFBD>Ƿ<EFBFBD><C7B7>ָ<EFBFBD><D6B8><EFBFBD>һ֡<D2BB><D6A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//0x50
#define BFI_NUMBER_Pos 0
#define BFI_NUMBER (0<<BFI_NUMBER_Pos) //9BITS BFI<46><49><EFBFBD>õ<EFBFBD>PWM<57><4D><EFBFBD><EFBFBD>
#define LDO_3V3_Pos 9
#define LDO_3V3_DISABLE 0
#define LDO_3V3_ENABLE 1
#define LDO_3V3 (LDO_3V3_DISABLE<<LDO_3V3_Pos)
#define DAC_133_BURST_Pos 10
#define DAC_133_BURST_DISABLE 0
#define DAC_133_BURST_ENABLE 1
#define DAC_133_BURST (DAC_133_BURST_DISABLE<<DAC_133_BURST_Pos) //<2F><><EFBFBD><EFBFBD>1.3<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ
#define DAC_200_BURST_Pos 11
#define DAC_200_BURST_DISABLE 0
#define DAC_200_BURST_ENABLE 1
#define DAC_200_BURST (DAC_200_BURST_DISABLE<<DAC_200_BURST_Pos) //<2F><><EFBFBD><EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ
#define PWM_COMPENSATION_Pos 12
#define PWM_COMPENSATION_NO 0
#define PWM_COMPENSATION_400NS 1
#define PWM_COMPENSATION (PWM_COMPENSATION_NO<<PWM_COMPENSATION_Pos) //PWM<57><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define FORCEON_REFER_Pos 13
#define FORCEON_REFER_HDRM 0
#define FORCEON_REFER_OPEN 1
#define FORCEON_REFER (FORCEON_REFER_HDRM<<FORCEON_REFER_Pos)
//0x52 //<2F><><EFBFBD><EFBFBD>CH1<48><31>delayʱ<79><CAB1>
//0x54 //<2F><><EFBFBD><EFBFBD>CH2<48><32>delayʱ<79><CAB1>
//0x56 //<2F><><EFBFBD><EFBFBD>CH3<48><33>delayʱ<79><CAB1>
//0x58 //<2F><><EFBFBD><EFBFBD>CH4<48><34>delayʱ<79><CAB1>
//0x5A
#define HEADROOM_Pos 0
#define HEADROOM_500MV 0
#define HEADROOM_600MV 1
#define HEADROOM_700MV 2
#define HEADROOM_800MV 3
#define HEADROOM_900MV 4
#define HEADROOM_1000MV 5
#define HEADROOM_1200MV 6
#define HEADROOM_1400MV 7
#define HEADROOM (HEADROOM_900MV<<HEADROOM_Pos) //headroom<6F><6D><EFBFBD><EFBFBD>
//0x5B
#define FRAME_SPACE_PREM_NUMBER_CFG_Pos 0
#define FRAME_SPACE_PREM_NUMBER_CFG_BY_DIS_DOS 0
#define FRAME_SPACE_PREM_NUMBER_CFG_BY_REGISTER 1
#define FRAME_SPACE_PREM_NUMBER_CFG FRAME_SPACE_PREM_NUMBER_CFG_BY_REGISTER //<2F>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9>ͨ<EFBFBD><CDA8><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֡<EFBFBD><D6A1><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define FRAME_SPACE_Pos 1
#define FRAME_SPACE_1024_TOSC 0
#define FRAME_SPACE_512_TOSC 1
#define FRAME_SPACE_256_TOSC 2
#define FRAME_SPACE_128_TOSC 3
#define FRAME_SPACE (FRAME_SPACE_1024_TOSC<<FRAME_SPACE_Pos) //֡<><D6A1><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define PREAMBLE_NUMBER_Pos 3
#define PREAMBLE_NUMBER_60_BIT 0
#define PREAMBLE_NUMBER_40_BIT 1
#define PREAMBLE_NUMBER_20_BIT 2
#define PREAMBLE_NUMBER_10_BIT 3
#define PREAMBLE_NUMBER (PREAMBLE_NUMBER_60_BIT<<PREAMBLE_NUMBER_Pos) //ǰ<><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define DOS_FIX_FREQ_Pos 5
#define DOS_FIX_FREQ_DISABLE 0
#define DOS_FIX_FREQ_ENABLE 1
#define DOS_FIX_FREQ (DOS_FIX_FREQ_ENABLE<<PREAMBLE_NUMBER_Pos) //DOS<4F><53>Ƶ<EFBFBD><C6B5><EFBFBD>Ƿ<EFBFBD><C7B7>̶<EFBFBD>
#define DOS_FREQ_Pos 6
#define DOS_FREQ_500K 0
#define DOS_FREQ_1M 1
#define DOS_FREQ_1_5M 2
#define DOS_FREQ_1_75M 3
#define DOS_OUTPUT_FREQ (DOS_FREQ_500K<<DOS_FREQ_Pos) //DOS<4F><53><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//0x46
#define SICK_FAULT_DISABLE 0 // 0:Enable sick dection 1:Disable sick dection
#define OPEN_FALUT_DISABLE 0 // 0:Enable open dection 1:Disable open dection
#define SHORT_FAULT_DISABLE 0 // 0:Enable short dection 1:Disable short dection
#define OTP_FAULT_DISABLE 0 // 0:Enable OTP dection 1:Disable OTP dection
#define OTP_OFF_DISABLE 0 // 0:Turn off pwm when OTP 1:not turn off pwm when OTP
#define OTP_REC_DISABLE 0 // 0:recovery pwm when OTP relieve 1:not auto recovery pwm when OTP relieve
#define OPEN_OFF_DISABLE 1 // 0:turn off pwm when open fault detected 1:not turn off pwm when open fault detected
#define SHORT_OFF_DISABLE 0 // 0:turn off pwm when short fault detected 1:not turn off pwm when short fault detected
#define DIP_CRC_CHECK_DISABLE 0 // 0:enable double-wire CRC check 1:disable double-wire CRC check
#define PWM_HIGH_TIME_FAULT_DISABLE 0 // 0:enable pwm high time detect function 1:disable pwm high time detect function
#define SICK_LIMIT_SEL 0 // 0:open debounce signal for sick 1:open deglitch signal for sick
#define SICK_RANGE_SEL 0 // 0:sick detection related to open 1:sick detection not related to open
#define DIS_DOS_CRC 0 // 0:enable dis-dos communication CRC check 1:disable dis-dos communication CRC check
#define CONFIG_DONE 1
#endif
#endif