#ifndef __HY8822_H
#define __HY8822_H

#ifdef HY8822

#define 	CH_NUMBERS						4
#define 	PWM_OFFSET						0
#define   BTI_WIDTH							20

//Reg47   
#define RD_CHIP_NUM_Pos								0
#define RD_CHIP_NUM										(0<<RD_CHIP_NUM_Pos)  //read chip num  when read back after EOP

#define RD_EOP_ADDR_Pos								8
#define RD_EOP_ADDR										(0<<RD_EOP_ADDR_Pos)	//the register address of first chip sent read back command 

//Reg48
#define OPEN_LV_Pos								2
#define OPEN_LV_50MV							0
#define OPEN_LV_80MV							1		
#define OPEN_LV_100MV							2 
#define OPEN_LV_130MV							3  
#define OPEN_LV  									(OPEN_LV_80MV<<OPEN_LV_Pos)

#define RISE_FALL_TIME_Pos				4
#define RISE_FALL_TIME_97NS				0
#define RISE_FALL_TIME_328NS			1		
#define RISE_FALL_TIME_484NS			2 
#define RISE_FALL_TIME_706NS			3  
#define RISE_FALL_TIME  					(RISE_FALL_TIME_706NS<<RISE_FALL_TIME_Pos)
	
#define DERATING_Pos											6
#define NO_DERATING												0
#define DAC_DERATING_50										1		
#define DAC_DERATING_25										2 
#define DAC_DERATING_12_5									3  
#define DERATING  												(NO_DERATING<<DERATING_Pos)

#define CHANNEL_DELAY_Pos									8
#define CHANNEL_DELAY_UPDATE_WAIT_PWM			0 
#define CHANNEL_DELAY_UPDATE_IMMEDIATELY	1
#define CHANNEL_DELAY_UPDATE							(CHANNEL_DELAY_UPDATE_WAIT_PWM<<CHANNEL_DELAY_Pos)

#define MULTISTAGE_SENT_Pos								9
#define MULTISTAGE_SENT_DISABLE						0 
#define MULTISTAGE_SENT_ENABLE						1
#define MULTISTAGE_SENT										(MULTISTAGE_SENT_DISABLE<<MULTISTAGE_SENT_Pos)

#define FAULT_SAMPLE_Pos									10
#define FAULT_SAMPLE_BFI_ENABLE						0
#define FAULT_SAMPLE_BFI_DISABLE					1 
#define FAULT_SAMPLE_BFI									(FAULT_SAMPLE_BFI_ENABLE<<FAULT_SAMPLE_Pos)

#define DOS_OUTPUT_OH_Pos									11
#define DOS_OUTPUT_OH_LOCKED_STATE				0
#define DOS_OUTPUT_OH_REAL								1 
#define DOS_OUTPUT_OH_SEL									(DOS_OUTPUT_OH_LOCKED_STATE<<DOS_OUTPUT_OH_Pos)

#define CLK_DIP_ALWAYS_Pos									11
#define CLK_DIP_ALWAYS_OFF							0
#define CLK_DIP_ALWAYS_ON								1 
#define CLK_DIP_ALWAYS									(CLK_DIP_ALWAYS_OFF<<CLK_DIP_ALWAYS_Pos)

#define OPEN_DEBOUNCE_TIME_Pos						13
#define OPEN_DEBOUNCE_TIME_3_TPWM					0
#define OPEN_DEBOUNCE_TIME_4_TPWM					1
#define OPEN_DEBOUNCE_TIME_8_TPWM					2
#define OPEN_DEBOUNCE_TIME_16_TPWM				3
#define OPEN_DEBOUNCE_TIME_32_TPWM			  4		
#define OPEN_DEBOUNCE_TIME_64_TPWM			  5
#define OPEN_DEBOUNCE_TIME_96_TPWM			  6
#define OPEN_DEBOUNCE_TIME_128_TPWM			  7
#define OPEN_DEBOUNCE_TIME  							(OPEN_DEBOUNCE_TIME_16_TPWM<<OPEN_DEBOUNCE_TIME_Pos)

//Reg49
#define UART_TX_DATA_LENGTH_Pos				0
#define UART_TX_DATA_LENGTH								(16<<UART_TX_DATA_LENGTH_Pos)

#define READ_BACK_MODE_SEL_Pos				8
#define NOT_SENT_READ_BACK_MODE_GET_EOP		0
#define SENT_READ_BACK_MODE_GET_EOP				1
#define READ_BACK_MODE_SEL								(NOT_SENT_READ_BACK_MODE_GET_EOP<<READ_BACK_MODE_SEL_Pos)

#define DOS_SENT_PROTOCOL_TYPE_Pos				9
#define DOS_SENT_PROTOCOL_TYPE_SPB				0
#define DOS_SENT_PROTOCOL_TYPE_UART				1
#define DOS_SENT_PROTOCOL_TYPE						(DOS_SENT_PROTOCOL_TYPE_SPB<<DOS_SENT_PROTOCOL_TYPE_Pos)

#define DOS_DELAY_NUM_Pos									10
#define DOS_DELAY_NUM_20									0
#define DOS_DELAY_NUM_40									1
#define DOS_DELAY_NUM_60									2
#define DOS_DELAY_NUM											(DOS_DELAY_NUM_20<<DOS_DELAY_NUM_Pos)

#define UART_FREQ_Pos											12
#define UART_FREQ_19200										0
#define UART_FREQ_38400										1
#define UART_FREQ_57600										2
#define UART_FREQ_115200									3
#define UART_FREQ_115200_DEFAULT					4
#define UART_FREQ_230400									5
#define UART_FREQ_460800									6
#define UART_FREQ_921600									7
#define UART_FREQ													(UART_FREQ_115200_DEFAULT<<UART_FREQ_Pos)

#define READ_BACK_EOP_SOP_TYPE_Pos				15
#define READ_BACK_EOP_SOP_TYPE_FAULT			0
#define READ_BACK_EOP_SOP_TYPE_REGISTER		1 
#define READ_BACK_EOP_SOP_TYPE						(READ_BACK_EOP_SOP_TYPE_REGISTER<<READ_BACK_EOP_SOP_TYPE_Pos)

//Reg4A
#define OTP_LV_Pos												0
#define OTP_LV_155__125										0
#define OTP_LV_145__115										1		
#define OTP_LV_135__105										2 
#define OTP_LV_125__95										3  
#define OTP_LV  													(OTP_LV_145__115<<OTP_LV_Pos)

#define SHORT_DET_DAC_Pos									2
#define SHORT_DET_DAC_ENABLE							0
#define SHORT_DET_DAC_DISABLE							1			
#define SHORT_DET_DAC											(SHORT_DET_DAC_ENABLE<<SHORT_DET_DAC_Pos)

#define IDAC_REF_Pos											3
#define IDAC_REF_120MV_270MV							0
#define IDAC_REF_100MV_250MV							1
#define IDAC_REF_80MV_230MV								2
#define IDAC_REF_60MV_210MV								3
#define IDAC_REF													(IDAC_REF_120MV_270MV<<IDAC_REF_Pos)

#define SPIKE_FILTER_TIME_Pos							5
#define SPIKE_FILTER_TIME_2_2NS						0
#define SPIKE_FILTER_TIME_4_2NS						1 
#define SPIKE_FILTER_TIME									(SPIKE_FILTER_TIME_2_2NS<<SPIKE_FILTER_TIME_Pos)

#define SPIKE_FILTER_Pos									6
#define SPIKE_FILTER_BYPASS								0
#define SPIKE_FILTER_USE									1 
#define SPIKE_FILTER											(SPIKE_FILTER_BYPASS<<SPIKE_FILTER_Pos)

#define ONE_WIRE_DEGLITCH_TIME_Pos				7
#define ONE_WIRE_DEGLITCH_TIME_2_TOSC			0
#define ONE_WIRE_DEGLITCH_TIME_4_TOSC			1
#define ONE_WIRE_DEGLITCH_TIME_8_TOSC			2
#define ONE_WIRE_DEGLITCH_TIME_32_TOSC		3
#define ONE_WIRE_DEGLITCH_TIME						(ONE_WIRE_DEGLITCH_TIME_4_TOSC<<ONE_WIRE_DEGLITCH_TIME_Pos)

#define ADDRESS_DEBUG_MODE_Pos						9
#define ADDRESS_DEBUG_MODE_DISABLE				0
#define ADDRESS_DEBUG_MODE_ENABLE					1
#define ADDRESS_DEBUG_MODE								(ADDRESS_DEBUG_MODE_DISABLE<<ADDRESS_DEBUG_MODE_Pos)

#define MOPICC_CONFIG_Pos									10
#define MOPICC_CONFIG_100									0
#define MOPICC_CONFIG_75									1
#define MOPICC_CONFIG_50									2
#define MOPICC_CONFIG_25									3
#define MOPICC_CONFIG_25_1								4
#define MOPICC_CONFIG_18_75 							5
#define MOPICC_CONFIG_12_5								6
#define MOPICC_CONFIG_6_25								7
#define MOPICC_CONFIG											(MOPICC_CONFIG_100<<MOPICC_CONFIG_Pos)

#define SHORT_DETECTION_THRESHOLD_Pos			13
#define SHORT_DETECTION_THRESHOLD_4				0
#define SHORT_DETECTION_THRESHOLD_8				1
#define SHORT_DETECTION_THRESHOLD_16			2
#define SHORT_DETECTION_THRESHOLD_31			3
#define SHORT_DETECTION_THRESHOLD					(SHORT_DETECTION_THRESHOLD_4<<SHORT_DETECTION_THRESHOLD_Pos)

#define PWM_DITHER_Pos										15
#define PWM_DITHER_DISABLE								0
#define PWM_DITHER_ENABLE									1
#define PWM_DITHER												(PWM_DITHER_DISABLE<<PWM_DITHER_Pos)


//Reg4c
#define OH_DERATING_Pos										0
#define OH_DERATING_FREQ_1_TVSYNC					0
#define OH_DERATING_FREQ_4_TVSYNC					1
#define OH_DERATING_FREQ_8_TVSYNC					2
#define OH_DERATING_FREQ_16_TVSYNC				3
#define OH_DERATING_FREQ									(OH_DERATING_FREQ_1_TVSYNC<<OH_DERATING_Pos)

#define SHORT_FIX_PWM_Pos									2
#define SHORT_FIX_PWM_DISABLE							0
#define SHORT_FIX_PWM_ENABLE							1
#define SHORT_FIX_PWM											(SHORT_FIX_PWM_DISABLE<<SHORT_FIX_PWM_Pos)

#define FAULT_DEGLITCH_TIME_Pos						3
#define FAULT_DEGLITCH_TIME_0_5US					0
#define FAULT_DEGLITCH_TIME_1US						1		
#define FAULT_DEGLITCH_TIME_2US						2 
#define FAULT_DEGLITCH_TIME_3US						3  
#define FAULT_DEGLITCH_TIME								(FAULT_DEGLITCH_TIME_1US<<FAULT_DEGLITCH_TIME_Pos)

#define DOS_MODE_Pos											5
#define DOS_MODE_OPEN_DRAIN								0
#define DOS_MODE_CMOS											1 
#define DOS_MODE													(DOS_MODE_CMOS<<DOS_MODE_Pos)

#define CHANNEL_GPOUPING_Pos							6
#define CHANNEL_GROUP_NO									0
#define CHANNEL_GROUP_2_CHANNEL						1
#define CHANNEL_GROUP_4_CHANNEL						2 
#define CHANNEL_GPOUPING									(CHANNEL_GROUP_NO<<CHANNEL_GPOUPING_Pos)

#define MIX_DC_LSB_Pos										8
#define MIX_DC_LSB_0											0
#define MIX_DC_LSB_1											1
#define MIX_DC_LSB												(MIX_DC_LSB_0<<MIX_DC_LSB_Pos)

#define MIX_PWM_LSB_Pos										9
#define MIX_PWM_LSB_0											0
#define MIX_PWM_LSB_1											1
#define MIX_PWM_LSB												(MIX_PWM_LSB_0<<MIX_PWM_LSB_Pos)

#define FAULT_BLANK_TIME_Pos							10
#define FAULT_BLANK_TIME	  							(10<<FAULT_BLANK_TIME_Pos)   //(4*N+3) * Tclock_pwm (duty:0.3% ~ 24.9%)  //6bits

//Reg4D
#define OH_LV_Pos										0
#define OH_LV_145										0
#define OH_LV_140										1		
#define OH_LV_135										2 
#define OH_LV_130										3
#define OH_LV_125										4
#define OH_LV_120										5
#define OH_LV_115										6
#define OH_LV_110 									7
#define OH_LV_105										8
#define OH_LV_100										9
#define OH_LV_95										10
#define OH_LV_90										11
#define OH_LV_85										12
#define OH_LV_80										13
#define OH_LV_75										14
#define OH_LV_70  									15    
#define OH_LV  											(OH_LV_105<<OH_LV_Pos)

#define OH_RECOVERY_Pos										4
#define OH_RECOVERY_140										0		
#define OH_RECOVERY_135										1 
#define OH_RECOVERY_130										2
#define OH_RECOVERY_125										3
#define OH_RECOVERY_120										4
#define OH_RECOVERY_115										5
#define OH_RECOVERY_110 									6
#define OH_RECOVERY_105										7
#define OH_RECOVERY_100										8
#define OH_RECOVERY_95										9
#define OH_RECOVERY_90										10
#define OH_RECOVERY_85										11
#define OH_RECOVERY_80										12
#define OH_RECOVERY_75										13
#define OH_RECOVERY_70  									14 
#define OH_RECOVERY_65  									15	
#define OH_RECOVERY  											(OH_RECOVERY_95<<OH_RECOVERY_Pos)

#define OH_DERATING_DECREASE_STEP_Pos			8
#define OH_DERATING_DECREASE_STEP 				(2<<OH_DERATING_DECREASE_STEP_Pos)

#define OH_DERATING_INCREASE_STEP_Pos			12
#define OH_DERATING_INCREASE_STEP 				(1<<OH_DERATING_INCREASE_STEP_Pos)

//Reg4E
#define PWM_CHANNEL_CLK_DIVIDED_Pos				0
#define PWM_CHANNEL_CLK_DIVIDED  					(7<<PWM_CHANNEL_CLK_DIVIDED_Pos) //

#define PWM_CLK_SEL_Pos										8
#define PWM_CLK_SEL_DIVEDED_CLK						0
#define PWM_CLK_SEL_20480HZ								1
#define PWM_CLK_SEL												(PWM_CLK_SEL_DIVEDED_CLK<<PWM_CLK_SEL_Pos)

#define SHORT_LV_Pos											9
#define SHORT_LV_2V												0
#define SHORT_LV_3V												1
#define SHORT_LV_4V												2
#define SHORT_LV_5V												3
#define SHORT_LV_6V												4
#define SHORT_LV_7V												5
#define SHORT_LV_9V												6
#define SHORT_LV_12V											7 
#define SHORT_LV	  											(SHORT_LV_12V<<SHORT_LV_Pos)

#define OPEN_DEBOUNCE_Pos									12
#define OPEN_DEBOUNCE_SEL_EOP							0
#define OPEN_DEBOUNCE_SEL_PWM							1
#define OPEN_DEBOUNCE											(OPEN_DEBOUNCE_SEL_PWM<<OPEN_DEBOUNCE_Pos)

#define BFI_MODE_Pos											13
#define BFI_MODE_RESERVE									0
#define BFI_MODE_BLANK										1
#define BFI_MODE													(BFI_MODE_RESERVE<<BFI_MODE_Pos)

#define BFI_Pos														14
#define BFI_DISABLE												0
#define BFI_ENABLE												1 
#define BFI																(BFI_DISABLE<<BFI_Pos) 

#define SLEEP_MODE_EXIT_Pos								15
#define SLEEP_MODE_EXIT_NO_RECOVERY				0
#define SLEEP_MODE_EXIT_RECOVERY					1
#define SLEEP_MODE_EXIT										(SLEEP_MODE_EXIT_RECOVERY<<SLEEP_MODE_EXIT_Pos)

//0X4F
#define BFI_NUMBER_Pos										0
#define BFI_NUMBER												(0<<BFI_NUMBER_Pos) 							//9BITS

#define LDO_3V3_Pos												9
#define LDO_3V3_DISABLE										0
#define LDO_3V3_ENABLE										1
#define LDO_3V3														(LDO_3V3_ENABLE<<LDO_3V3_Pos)

#define MOPICC_X1D5_CFG_D2A_Pos						10
#define MOPICC_X1D5_CFG_D2A_NORMAL				0
#define MOPICC_X1D5_CFG_D2A_1_5TIMERS			1
#define MOPICC_X1D5_CFG_D2A								(MOPICC_X1D5_CFG_D2A_NORMAL<<MOPICC_X1D5_CFG_D2A_Pos)

#define MOPICC_X2_CFG_D3A_Pos							11
#define MOPICC_X2_CFG_D3A_NORMAL					0
#define MOPICC_X2_CFG_D3A_2TIMERS					1
#define MOPICC_X2_CFG_D3A									(MOPICC_X2_CFG_D3A_NORMAL<<MOPICC_X2_CFG_D3A_Pos)

//	#define DAC_133_BURST_DISABLE							0
//	#define DAC_133_BURST_ENABLE							1
//	#define DAC_133_BURST											DAC_133_BURST_DISABLE

//	#define DAC_200_TURBO_DISABLE							0
//	#define DAC_200_TURBO_ENABLE							1
//	#define DAC_200_TURBO											DAC_200_TURBO_DISABLE

#define PWM_COMPENSATION_Pos							12
#define PWM_COMPENSATION_NO								0
#define PWM_COMPENSATION_400NS						1
#define PWM_COMPENSATION									(PWM_COMPENSATION_NO<<PWM_COMPENSATION_Pos)  

//0X5A
#define HEADROOM_Pos											0
#define HEADROOM_300MV										0
#define HEADROOM_350MV										1
#define HEADROOM_400MV										2
#define HEADROOM_450MV										3		
#define HEADROOM_500MV										4
#define HEADROOM_550MV										5
#define HEADROOM_600MV										6
#define HEADROOM_650MV										7
#define HEADROOM_700MV										8
#define HEADROOM_750MV										9 
#define HEADROOM_800MV										10
#define HEADROOM_850MV										11
#define HEADROOM_900MV										12
#define HEADROOM_1000MV										13
#define HEADROOM_1100MV										14
#define HEADROOM_1200MV										15
#define HEADROOM  												(HEADROOM_700MV<<HEADROOM_Pos)

//0X5B
#define FRAME_SPACE_PREM_NUMBER_CFG_Pos						0
#define FRAME_SPACE_PREM_NUMBER_CFG_BY_DIS_DOS  	0
#define FRAME_SPACE_PREM_NUMBER_CFG_BY_REGISTER		1
#define FRAME_SPACE_PREM_NUMBER_CFG								(FRAME_SPACE_PREM_NUMBER_CFG_BY_REGISTER<<FRAME_SPACE_PREM_NUMBER_CFG_Pos)

#define FRAME_SPACE_Pos										1
#define FRAME_SPACE_1024_TOSC							0
#define FRAME_SPACE_512_TOSC							1
#define FRAME_SPACE_256_TOSC							2
#define FRAME_SPACE_128_TOSC							3
#define FRAME_SPACE												(FRAME_SPACE_1024_TOSC<<FRAME_SPACE_Pos)

#define PREAMBLE_NUMBER_Pos								3
#define PREAMBLE_NUMBER_60_BIT						0
#define PREAMBLE_NUMBER_40_BIT						1
#define PREAMBLE_NUMBER_20_BIT						2
#define PREAMBLE_NUMBER_10_BIT						3
#define PREAMBLE_NUMBER										(PREAMBLE_NUMBER_60_BIT<<PREAMBLE_NUMBER_Pos)

#define DOS_FIX_FREQ_Pos									5
#define DOS_FIX_FREQ_DISABLE							0
#define DOS_FIX_FREQ_ENABLE								1 
#define DOS_FIX_FREQ											(DOS_FIX_FREQ_ENABLE<<DOS_FIX_FREQ_Pos)
	
#define DOS_OUTPUT_FREQ_Pos								6
#define DOS_FREQ_500K											0
#define DOS_FREQ_1M												1
#define DOS_FREQ_1_5M											2
#define DOS_FREQ_1_75M										3
#define DOS_OUTPUT_FREQ										(DOS_FREQ_500K<<DOS_OUTPUT_FREQ_Pos)

#define DIS_DIP_CONNECT_Pos								8
#define DIS_DIP_CONNECT_DISABLE						0
#define DIS_DIP_CONNECT_ENABLE						1
#define DIS_DIP_CONNECT										(DIS_DIP_CONNECT_DISABLE<<DIS_DIP_CONNECT_Pos)

#define BFI_VRR_MODE_Pos										9
#define BFI_VRR_MODE_DISABLE								0
#define BFI_VRR_MODE_DC_SET_BY_GLOAL_DC			1
#define BFI_VRR_MODE_DC_DERATING_BY_OH_CONFIG		2
#define BFI_VRR_MODE											(BFI_VRR_MODE_DISABLE<<BFI_VRR_MODE_Pos)

#define BFI_VRR_DAC_DERATE_Pos						11
#define BFI_VRR_DAC_DERATE_DISABLE				0
#define BFI_VRR_DAC_DERATE_ENABLE					1 
#define BFI_VRR_DAC_DERATE								(BFI_VRR_DAC_DERATE_DISABLE<<BFI_VRR_DAC_DERATE_Pos) 


//0x7B
#define GLOBAL_DAC												32  //80+N*2.5 ma



#define	SICK_FAULT_DISABLE          			0		// 0:Enable sick dection 											1:Disable sick dection
#define	OPEN_FALUT_DISABLE				 				0		// 0:Enable open dection 											1:Disable open dection
#define	SHORT_FAULT_DISABLE	        			0	  // 0:Enable short dection 										1:Disable short dection				
#define	OTP_FAULT_DISABLE				 					0   // 0:Enable OTP dection 											1:Disable OTP dection									
#define OTP_OFF_DISABLE                 	0   // 0:Turn off pwm when OTP 										1:not turn off pwm when OTP
#define OTP_REC_DISABLE                 	0   // 0:recovery pwm when OTP relieve 						1:not auto recovery pwm when OTP relieve
#define OPEN_OFF_DISABLE                	1   // 0:turn off pwm when open fault detected 		1:not turn off pwm when open fault detected
#define SHORT_OFF_DISABLE               	0   // 0:turn off pwm when short fault detected 	1:not turn off pwm when short fault detected
#define	DIP_CRC_CHECK_DISABLE 						0   // 0:enable double-wire CRC check							1:disable double-wire CRC check
#define	PWM_HIGH_TIME_FAULT_DISABLE 			0   // 0:enable pwm high time detect function			1:disable pwm high time detect function
#define OH_DISABLE												0   // 0:enable OH detect function								1:disable OH detect function
#define	SICK_RANGE_SEL 								0   // 0:sick detection related to open comparator result			1:sick detection not related to open comparator result
#define	DIS_DOS_CRC 											0   // 0:enable double-wire CRC check							1:disable double-wire CRC check
#define OH_DERATING_ENABLE										0   // 0:disable OH derate								1:enable OH derate
#define CONFIG_DONE												1
  

#endif



#endif