#ifndef __HY8608_H
#define __HY8608_H

#ifdef HY8608

#define CH_NUMBERS						8
#define PWM_OFFSET						4
#define BTI_WIDTH							16

 
//0x41
#define TP_NUM_Pos                       0
#define TP_NUM_14BIT_TP                 0
#define TP_NUM_13BIT_TP                  1
#define TP_NUM_12BIT_TP                 2
#define TP_NUM_11BIT_TP                 3
#define TP_NUM_10BIT_TP                 4
#define TP_NUM_9BIT_TP                 5
#define TP_NUM_8BIT_TP                 6
#define TP_NUM_6BIT_TP                 7
#define TP_NUM                         (TP_NUM_14BIT_TP<<TP_NUM_Pos)

#define HT_DITHER_NUM_Pos                  4
#define HT_DITHER_NUM_0BIT_DITHER          0
#define HT_DITHER_NUM_1BIT_DITHER          1
#define HT_DITHER_NUM_2BIT_DITHER          2
#define HT_DITHER_NUM_3BIT_DITHER          3
#define HT_DITHER_NUM_4BIT_DITHER          4
#define HT_DITHER_NUM_5BIT_DITHER          5
#define HT_DITHER_NUM_6BIT_DITHER          6
#define HT_DITHER_NUM                   (HT_DITHER_NUM_0BIT_DITHER<<HT_DITHER_NUM_Pos)

#define TURBO_Pos													8
#define TURBO_DISABLE											0
#define TURBO_ENABLE											1
#define TURBO															(TURBO_DISABLE<<TURBO_Pos)

#define BFI_AUTO_REPETE_Pos								9
#define BFI_AUTO_REPETE_DISABLE						0
#define BFI_AUTO_REPETE_ENABLE						1
#define BFI_AUTO_REPETE										(BFI_AUTO_REPETE_DISABLE<<BFI_AUTO_REPETE_Pos)

#define BFI_AUTO_REPETE_FREQ_Pos								10
#define BFI_AUTO_REPETE_FREQ_DISABLE						0
#define BFI_AUTO_REPETE_FREQ_ENABLE						1
#define BFI_AUTO_REPETE_FREQ										(BFI_AUTO_REPETE_FREQ_DISABLE<<BFI_AUTO_REPETE_FREQ_Pos)

#define IO_SWITCH_TIMEOUT_Pos								11
#define IO_SWITCH_TIMEOUT_1MS								0
#define IO_SWITCH_TIMEOUT_2MS								1
#define IO_SWITCH_TIMEOUT_4MS								2
#define IO_SWITCH_TIMEOUT_6MS								3
#define IO_SWITCH_TIMEOUT										(IO_SWITCH_TIMEOUT_1MS<<IO_SWITCH_TIMEOUT_Pos)


#define IO_SWITCH_WINDOW_Pos								13
#define IO_SWITCH_WINDOW_250US								0
#define IO_SWITCH_WINDOW_500US							1
#define IO_SWITCH_WINDOW_1MS								2
#define IO_SWITCH_WINDOW_1500US								3
#define IO_SWITCH_WINDOW										(IO_SWITCH_WINDOW_250US<<IO_SWITCH_WINDOW_Pos)

#define IO_SWITCH_COMMAND_NUM_Pos								15
#define IO_SWITCH_COMMAND_NUM_2								0
#define IO_SWITCH_COMMAND_NUM_1							1 
#define IO_SWITCH_COMMAND_NUM										(IO_SWITCH_COMMAND_NUM_2<<IO_SWITCH_COMMAND_NUM_Pos)


//0x42
#define OWB_6_8_DATA_OFFSET_Pos						0
#define OWB_6_8_DATA_OFFSET								(0<<OWB_6_8_DATA_OFFSET_Pos)

#define DUPLEX_IO_OVERLAP_TIME_Pos				12
#define DUPLEX_IO_OVERLAP_TIME_126NS			0
#define DUPLEX_IO_OVERLAP_TIME_252NS			1
#define DUPLEX_IO_OVERLAP_TIME						(DUPLEX_IO_OVERLAP_TIME_126NS<<DUPLEX_IO_OVERLAP_TIME_Pos)

#define LAST_CHIP_TX_FREQ_Pos							13
#define LAST_CHIP_TX_FREQ_FOLLOW_RX				0
#define LAST_CHIP_TX_FREQ_FIX500K					1
#define LAST_CHIP_TX_FREQ									(LAST_CHIP_TX_FREQ_FOLLOW_RX<<LAST_CHIP_TX_FREQ_Pos)

#define DELAY_CHANGE_IO_CMD_Pos							14
#define DELAY_CHANGE_IO_CMD_8_16US				0
#define DELAY_CHANGE_IO_CMD_2_10US					1
#define DELAY_CHANGE_IO_CMD_4_12US				2
#define DELAY_CHANGE_IO_CMD_16_24US					3
#define DELAY_CHANGE_IO_CMD									(DELAY_CHANGE_IO_CMD_8_16US<<DELAY_CHANGE_IO_CMD_Pos)

//0x47
#define HEADROOM_Pos									    0
#define HEADROOM_200MV										0
#define HEADROOM_250MV										1		
#define HEADROOM_300MV										2
#define HEADROOM_350MV										3
#define HEADROOM_400MV										4
#define HEADROOM_450MV										5
#define HEADROOM_500MV										6
#define HEADROOM_550MV										7 
#define HEADROOM_600MV										8
#define HEADROOM_650MV										9
#define HEADROOM_700MV										10
#define HEADROOM_800MV										11
#define HEADROOM_900MV										12
#define HEADROOM_1000MV										13
#define HEADROOM_1100MV										14     
#define HEADROOM_1200MV										15
#define HEADROOM  										   (HEADROOM_400MV<<HEADROOM_Pos)	//headroomÉèÖÃ

//0x48
#define MOPICC_X1D50_Pos            				0
#define MOPICC_X1D50_DISABLE               0
#define MOPICC_X1D50_ENABLE								1
#define MOPICC_X1D50												(MOPICC_X1D50_DISABLE<<MOPICC_X1D50_Pos)

#define CLK_ALWAYS_ON_Pos					1
#define CLK_ALWAYS_ON_DISABLE  		0
#define CLK_ALWAYS_ON_ENABLE  		1
#define CLK_ALWAYS_ON							(CLK_ALWAYS_ON_DISABLE<<CLK_ALWAYS_ON_Pos)


#define OPEN_LV_Pos				2
#define OPEN_LV_50MV			0
#define OPEN_LV_80MV			1		
#define OPEN_LV_100MV			2 
#define OPEN_LV_130MV			3  
#define OPEN_LV  					(OPEN_LV_80MV<<OPEN_LV_Pos)

#define PWM_COMPENSATION_TIME_Pos				4
#define PWM_COMPENSATION_TIME_97NS			0
#define PWM_COMPENSATION_TIME_328NS			1		
#define PWM_COMPENSATION_TIME_484US			2 
#define PWM_COMPENSATION_TIME_706NS			3  
#define PWM_COMPENSATION_TIME  					(PWM_COMPENSATION_TIME_706NS<<PWM_COMPENSATION_TIME_Pos)

#define MOPICC_X2_Pos									6
#define MOPICC_X2_DISBALE	  					0
#define MOPICC_X2_ENABLE						  1
#define MOPICC_X2											(MOPICC_X2_DISBALE<<MOPICC_X2_Pos)

#define BFI_VRR_Pos								7
#define BFI_VRR_DISABLE						0
#define BFI_VRR_ENABLE						1
#define BFI_VRR										(BFI_VRR_DISABLE<<BFI_VRR_Pos)

#define LDO_3V3_Pos												8
#define LDO_3V3_DISABLE										0
#define LDO_3V3_ENABLE										1
#define LDO_3V3														(LDO_3V3_DISABLE<<LDO_3V3_Pos)

#define BURST_MODE_Pos						9
#define BURST_MODE_DISABLE				0
#define BURST_MODE_ENABLE					1
#define BURST_MODE								(BURST_MODE_DISABLE<<BURST_MODE_Pos)

#define PWM_COMPENSATION_Pos						10
#define PWM_COMPENSATION_NO							0
#define PWM_COMPENSATION_WITH						1
#define PWM_COMPENSATION									(PWM_COMPENSATION_NO<<PWM_COMPENSATION_Pos) 

#define FAULT_SAMPLE_BFI_Pos							11
#define FAULT_SAMPLE_BFI_ENABLE						0
#define FAULT_SAMPLE_BFI_DISABLE					1 
#define FAULT_SAMPLE_BFI									(FAULT_SAMPLE_BFI_DISABLE<<FAULT_SAMPLE_BFI_Pos)

#define DOS_OUTPUT_OH_SEL_Pos							12
#define DOS_OUTPUT_OH_LOCKED_STATE				0
#define DOS_OUTPUT_OH_REAL								1 
#define DOS_OUTPUT_OH_SEL									(DOS_OUTPUT_OH_LOCKED_STATE<<DOS_OUTPUT_OH_SEL_Pos)

#define OPEN_DEBOUNCE_TIME_Pos						13
#define OPEN_DEBOUNCE_TIME_3_TPWM					0
#define OPEN_DEBOUNCE_TIME_4_TPWM					1
#define OPEN_DEBOUNCE_TIME_8_TPWM					2
#define OPEN_DEBOUNCE_TIME_16_TPWM				3
#define OPEN_DEBOUNCE_TIME_32_TPWM			  4		
#define OPEN_DEBOUNCE_TIME_64_TPWM			  5
#define OPEN_DEBOUNCE_TIME_96_TPWM			  6
#define OPEN_DEBOUNCE_TIME_128_TPWM			  7
#define OPEN_DEBOUNCE_TIME  							(OPEN_DEBOUNCE_TIME_16_TPWM<<OPEN_DEBOUNCE_TIME_Pos)

//Reg49
#define BFI_VRR_DAC_MULTIPLICATION_Pos		0
#define BFI_VRR_DAC_MULTIPLICATION				(0<<BFI_VRR_DAC_MULTIPLICATION_Pos)		//9BITS

#define UART_TRANS_TYPE_Pos								9
#define UART_TRANS_DATA										0
#define UART_TRANS_FAULT									1
#define UART_TRANS_TYPE										(UART_TRANS_FAULT<<UART_TRANS_TYPE_Pos)

#define UART_CRC_Pos											10
#define UART_WITHOUT_CRC									0
#define UART_WITH_CRC											1
#define UART_CRC													(UART_WITHOUT_CRC<<UART_CRC_Pos)

#define UART_STOP_BIT_Pos									11
#define UART_STOP_1BIT										0
#define UART_STOP_1_5BIT									1
#define UART_STOP_2BIT										2 
#define UART_STOP_BIT											(UART_STOP_1BIT<<UART_STOP_BIT_Pos)

#define UART_FREQ_Pos											13
#define UART_FREQ_19200										0
#define UART_FREQ_38400										1
#define UART_FREQ_57600										2
#define UART_FREQ_115200									3
#define UART_FREQ_115200_DEFAULT					4
#define UART_FREQ_230400									5
#define UART_FREQ_460800									6
#define UART_FREQ_921600									7
#define UART_FREQ													(UART_FREQ_115200_DEFAULT<<UART_FREQ_Pos)
	
 
//Reg4A
#define OTP_LV_Pos												0
#define OTP_LV_155__125										0
#define OTP_LV_145__115										1		
#define OTP_LV_135__105										2 
#define OTP_LV_125__95										3  
#define OTP_LV  													(OTP_LV_145__115<<OTP_LV_Pos)

#define SHORT_DET_DAC_Pos									2
#define SHORT_DET_DAC_ENABLE							0
#define SHORT_DET_DAC_DISABLE							1			
#define SHORT_DET_DAC											(SHORT_DET_DAC_ENABLE<<SHORT_DET_DAC_Pos)

#define IDAC_REF_Pos											3
#define IDAC_REF_200MV_350MV							0
#define IDAC_REF_160MV_310MV							1
#define IDAC_REF_120MV_270MV							2
#define IDAC_REF_80MV_230MV								3
#define IDAC_REF													(IDAC_REF_80MV_230MV<<IDAC_REF_Pos)

#define SPIKE_FILTER_TIME_Pos							5
#define SPIKE_FILTER_TIME_2_2NS						0
#define SPIKE_FILTER_TIME_4_2NS						1 
#define SPIKE_FILTER_TIME									(SPIKE_FILTER_TIME_2_2NS<<SPIKE_FILTER_TIME_Pos)

#define SPIKE_FILTER_Pos									6
#define SPIKE_FILTER_BYPASS								0
#define SPIKE_FILTER_USE									1 
#define SPIKE_FILTER											(SPIKE_FILTER_BYPASS<<SPIKE_FILTER_Pos)

#define ONE_WIRE_DEGLITCH_TIME_Pos				7
#define ONE_WIRE_DEGLITCH_TIME_2_TOSC			0
#define ONE_WIRE_DEGLITCH_TIME_4_TOSC			1
#define ONE_WIRE_DEGLITCH_TIME_8_TOSC			2
#define ONE_WIRE_DEGLITCH_TIME_32_TOSC		3
#define ONE_WIRE_DEGLITCH_TIME						(ONE_WIRE_DEGLITCH_TIME_2_TOSC<<ONE_WIRE_DEGLITCH_TIME_Pos)

#define MOPICC_CONFIG_Pos									10
#define MOPICC_CONFIG_100									0
#define MOPICC_CONFIG_75									1
#define MOPICC_CONFIG_50									2
#define MOPICC_CONFIG_25									3
#define MOPICC_CONFIG_25_1								4
#define MOPICC_CONFIG_18_75 							5
#define MOPICC_CONFIG_12_5								6
#define MOPICC_CONFIG_6_25								7
#define MOPICC_CONFIG											(MOPICC_CONFIG_100<<MOPICC_CONFIG_Pos)

#define SHORT_DETECTION_THRESHOLD_Pos			13
#define SHORT_DETECTION_THRESHOLD_4				0
#define SHORT_DETECTION_THRESHOLD_8				1
#define SHORT_DETECTION_THRESHOLD_16			2
#define SHORT_DETECTION_THRESHOLD_31			3
#define SHORT_DETECTION_THRESHOLD					(SHORT_DETECTION_THRESHOLD_4<<SHORT_DETECTION_THRESHOLD_Pos)

#define CHANNEL_DELAY_UPDATE_Pos					15
#define CHANNEL_DELAY_UPDATE_WAIT_PWM			0 
#define CHANNEL_DELAY_UPDATE_IMMEDIATELY	1
#define CHANNEL_DELAY_UPDATE							(CHANNEL_DELAY_UPDATE_WAIT_PWM<<CHANNEL_DELAY_UPDATE_Pos)

//Reg4B
#define BFI_VRR_BEGIN_CYCLE_Pos						0
#define BFI_VRR_BEGIN_CYCLE								(0<<BFI_VRR_BEGIN_CYCLE_Pos)				//9BIT

#define READ_BACK_MODE_Pos								10
#define NOT_SENT_READ_BACK_CMD_GET_EOP		0
#define SENT_READ_BACK_CMD_GET_EOP				1
#define READ_BACK_MODE										(NOT_SENT_READ_BACK_CMD_GET_EOP<<READ_BACK_MODE_Pos)

#define READ_BACK_EOP_SOP_TYPE_Pos				11
#define READ_BACK_EOP_SOP_TYPE_FAULT			0
#define READ_BACK_EOP_SOP_TYPE_REGISTER		1 
#define READ_BACK_EOP_SOP_TYPE						(READ_BACK_EOP_SOP_TYPE_FAULT<<READ_BACK_EOP_SOP_TYPE_Pos)

#define FRAME_SPACE_Pos									  12
#define FRAME_SPACE_4096_TOSC							0
#define FRAME_SPACE_2048_TOSC							1
#define FRAME_SPACE_1024_TOSC							2
#define FRAME_SPACE_512_TOSC							3
#define FRAME_SPACE_256_TOSC							4
#define FRAME_SPACE_128_TOSC							5
#define FRAME_SPACE_64_TOSC								6
#define FRAME_SPACE_32_TOSC								7
#define FRAME_SPACE												(FRAME_SPACE_4096_TOSC<<FRAME_SPACE_Pos)

#define DC_DITHER_DC_PWM_Pos							15
#define DC_DITHER_DC_PWM_DISABLE												0
#define DC_DITHER_DC_PWM_ENABLE												1
#define DC_DITHER_DC_PWM								  (DC_DITHER_DC_PWM_DISABLE<<DC_DITHER_DC_PWM_Pos)


//Reg4c
#define CHANNEL_GROUP_Pos									0
#define CHANNEL_GROUP_NO									0
#define CHANNEL_GROUP_2_CHANNEL						1
#define CHANNEL_GROUP_4_CHANNEL						2 
#define CHANNEL_GROUP   									(CHANNEL_GROUP_NO<<CHANNEL_GROUP_Pos)

#define SHORT_FIX_PWM_Pos									2
#define SHORT_FIX_PWM_DISABLE							0
#define SHORT_FIX_PWM_ENABLE							1
#define SHORT_FIX_PWM											(SHORT_FIX_PWM_DISABLE<<SHORT_FIX_PWM_Pos)

#define FAULT_DEGLITCH_TIME_Pos						3
#define FAULT_DEGLITCH_TIME_0_5US					0
#define FAULT_DEGLITCH_TIME_1US						1		
#define FAULT_DEGLITCH_TIME_2US						2 
#define FAULT_DEGLITCH_TIME_3US						3  
#define FAULT_DEGLITCH_TIME								(FAULT_DEGLITCH_TIME_1US<<FAULT_DEGLITCH_TIME_Pos)

#define BFI_CRC_ERR_REPEAT_Pos						5
#define BFI_CRC_ERR_REPEAT_DISABLE				0
#define BFI_CRC_ERR_REPEAT_ENABLE					1
#define BFI_CRC_ERR_REPEAT								(BFI_CRC_ERR_REPEAT_DISABLE<<BFI_CRC_ERR_REPEAT_Pos)

#define OH_DERATING_INCREASE_STEP_Pos			6
#define OH_DERATING_INCREASE_STEP 				(0<<OH_DERATING_INCREASE_STEP_Pos)

#define FAULT_BLANK_TIME_Pos							10
#define FAULT_BLANK_TIME	  							(0<<FAULT_BLANK_TIME_Pos)   //6bits

//Reg4D
#define OH_TRIGGER_Pos										0
#define OH_TRIGGER  											(8<<OH_TRIGGER_Pos) 				//(145¡æ-N*5¡æ)  5bits

#define OH_RECOVERY_Pos										5
#define OH_RECOVERY  											(10<<OH_RECOVERY_Pos)    		//(145¡æ-N*5¡æ)  5bits
	
#define OH_DERATING_DECREASE_STEP_Pos			10
#define OH_DERATING_DECREASE_STEP 				(0<<OH_DERATING_DECREASE_STEP_Pos)

#define OH_DERATING_FREQ_Pos							14
#define OH_DERATING_FREQ_4_TVSYNC					0
#define OH_DERATING_FREQ_16_TVSYNC				1
#define OH_DERATING_FREQ_64_TVSYNC				2
#define OH_DERATING_FREQ_128_TVSYNC				3
#define OH_DERATING_FREQ									(OH_DERATING_FREQ_4_TVSYNC<<OH_DERATING_FREQ_Pos)
	
//Reg4E
#define PWM_CHANNEL_CLK_DIVIDED_Pos				0
#define PWM_CHANNEL_CLK_DIVIDED  					(7<<PWM_CHANNEL_CLK_DIVIDED_Pos) 		//8BITS

//#define PWM_CLK_SEL_DIVEDED_CLK						0
//#define PWM_CLK_SEL_20480HZ								1
//#define PWM_CLK_SEL												PWM_CLK_SEL_DIVEDED_CLK

#define SHORT_LV_Pos											9
#define SHORT_LV_2V												0
#define SHORT_LV_3V												1
#define SHORT_LV_4V												2
#define SHORT_LV_5V												3
#define SHORT_LV_6V												4
#define SHORT_LV_7V												5
#define SHORT_LV_9V												6
#define SHORT_LV_12V											7 
#define SHORT_LV	  											(SHORT_LV_12V<<SHORT_LV_Pos)

#define OPEN_DEBOUNCE_SEL_Pos							12
#define OPEN_SEL_EOP											0
#define OPEN_SEL_PWM											1
#define OPEN_DEBOUNCE_SEL									(OPEN_SEL_PWM<<OPEN_DEBOUNCE_SEL_Pos)

#define BFI_MODE_Pos											13
#define BFI_RESERVE_FIRST									0
#define BFI_BLANK_FIRST										1
#define BFI_MODE													(BFI_RESERVE_FIRST<<BFI_MODE_Pos)

#define BFI_Pos														14
#define BFI_DISABLE												0
#define BFI_ENABLE												1 
#define BFI																(BFI_DISABLE<<BFI_Pos) 

#define SLEEP_MODE_EXIT_Pos								15
#define SLEEP_MODE_EXIT_NO_RECOVERY				0
#define SLEEP_MODE_EXIT_RECOVERY					1
#define SLEEP_MODE_EXIT										(SLEEP_MODE_EXIT_RECOVERY<<SLEEP_MODE_EXIT_Pos)

//0X4F
#define BFI_NUMBER_Pos										0
#define BFI_NUMBER												(0<<BFI_NUMBER_Pos) 							//9BITS

#define BMC_SAMPLING_POINT_Pos						13
#define BMC_SAMPLING_POINT_0							0
#define BMC_SAMPLING_POINT_1							1
#define BMC_SAMPLING_POINT_2							2
#define BMC_SAMPLING_POINT_3							3
#define BMC_SAMPLING_POINT								(BMC_SAMPLING_POINT_1<<BMC_SAMPLING_POINT_Pos)

#define MUX_OPTION_Pos										15
#define MUX_OPTION_OWB										0
#define MUX_OPTION_OWS										1
#define MUX_OPTION												(MUX_OPTION_OWS<<MUX_OPTION_Pos)
 
	 
//0X7B
#define GLOBAL_DAC_Pos										0
#define GLOBAL_DAC												(33<<GLOBAL_DAC_Pos)			//18+N*0.66mA		N:register value   6bits


//0x46
#define	SICK_FAULT_DISABLE          			0		// 0:Enable sick dection 											1:Disable sick dection
#define	OPEN_FALUT_DISABLE				 				0		// 0:Enable open dection 											1:Disable open dection
#define	SHORT_FAULT_DISABLE	        			0	  // 0:Enable short dection 										1:Disable short dection				
#define	OTP_FAULT_DISABLE				 					0   // 0:Enable OTP dection 											1:Disable OTP dection									
#define OTP_OFF_DISABLE                 			0   // 0:Turn off pwm when OTP 										1:not turn off pwm when OTP
#define OTP_REC_DISABLE                 			0   // 0:recovery pwm when OTP relieve 						1:not auto recovery pwm when OTP relieve
#define OPEN_OFF_DISABLE                			1   // 0:turn off pwm when open fault detected 		1:not turn off pwm when open fault detected
#define SHORT_OFF_DISABLE               			0   // 0:turn off pwm when short fault detected 	1:not turn off pwm when short fault detected
#define OWB_DATA_OFFSET_ENABLE            0   // 0: disable OWB_data_offset_register 					1: enable OWB_data_offset_register
#define	PWM_HIGH_TIME_FAULT_DISABLE 			0   // 0:enable pwm high time detect function			1:disable pwm high time detect function
#define OH_DISABLE												0   // 0:enable OH detect function								1:disable OH detect function
#define SICK_RANGE_SEL										0   // 0:sick detection related to open 					1:sick detection not related to open
#define DIS_DOS_CRC												0		// 0:enable dis-dos communication CRC check   1:disable dis-dos communication CRC check
#define OH_DERATING_ENABLE								0   // 0:disable OH dreating											1:enable OH dreating
#define DUPLEX_ENABLE											0		// 0:disable duplex														1:enable duplex	
#define CONFIG_DONE												1


#endif

#endif