436 lines
16 KiB
C
436 lines
16 KiB
C
#ifndef __HY8608_H
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#define __HY8608_H
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#ifdef HY8608
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#define CH_NUMBERS 8
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#define PWM_OFFSET 4
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#define BTI_WIDTH 16
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//0x41
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#define TP_NUM_Pos 0
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#define TP_NUM_14BIT_TP 0
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#define TP_NUM_13BIT_TP 1
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#define TP_NUM_12BIT_TP 2
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#define TP_NUM_11BIT_TP 3
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#define TP_NUM_10BIT_TP 4
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#define TP_NUM_9BIT_TP 5
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#define TP_NUM_8BIT_TP 6
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#define TP_NUM_6BIT_TP 7
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#define TP_NUM (TP_NUM_14BIT_TP<<TP_NUM_Pos)
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#define HT_DITHER_NUM_Pos 4
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#define HT_DITHER_NUM_0BIT_DITHER 0
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#define HT_DITHER_NUM_1BIT_DITHER 1
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#define HT_DITHER_NUM_2BIT_DITHER 2
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#define HT_DITHER_NUM_3BIT_DITHER 3
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#define HT_DITHER_NUM_4BIT_DITHER 4
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#define HT_DITHER_NUM_5BIT_DITHER 5
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#define HT_DITHER_NUM_6BIT_DITHER 6
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#define HT_DITHER_NUM (HT_DITHER_NUM_0BIT_DITHER<<HT_DITHER_NUM_Pos)
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#define TURBO_Pos 8
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#define TURBO_DISABLE 0
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#define TURBO_ENABLE 1
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#define TURBO (TURBO_DISABLE<<TURBO_Pos)
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#define BFI_AUTO_REPETE_Pos 9
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#define BFI_AUTO_REPETE_DISABLE 0
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#define BFI_AUTO_REPETE_ENABLE 1
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#define BFI_AUTO_REPETE (BFI_AUTO_REPETE_DISABLE<<BFI_AUTO_REPETE_Pos)
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#define BFI_AUTO_REPETE_FREQ_Pos 10
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#define BFI_AUTO_REPETE_FREQ_DISABLE 0
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#define BFI_AUTO_REPETE_FREQ_ENABLE 1
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#define BFI_AUTO_REPETE_FREQ (BFI_AUTO_REPETE_FREQ_DISABLE<<BFI_AUTO_REPETE_FREQ_Pos)
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#define IO_SWITCH_TIMEOUT_Pos 11
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#define IO_SWITCH_TIMEOUT_1MS 0
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#define IO_SWITCH_TIMEOUT_2MS 1
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#define IO_SWITCH_TIMEOUT_4MS 2
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#define IO_SWITCH_TIMEOUT_6MS 3
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#define IO_SWITCH_TIMEOUT (IO_SWITCH_TIMEOUT_1MS<<IO_SWITCH_TIMEOUT_Pos)
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#define IO_SWITCH_WINDOW_Pos 13
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#define IO_SWITCH_WINDOW_250US 0
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#define IO_SWITCH_WINDOW_500US 1
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#define IO_SWITCH_WINDOW_1MS 2
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#define IO_SWITCH_WINDOW_1500US 3
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#define IO_SWITCH_WINDOW (IO_SWITCH_WINDOW_250US<<IO_SWITCH_WINDOW_Pos)
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#define IO_SWITCH_COMMAND_NUM_Pos 15
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#define IO_SWITCH_COMMAND_NUM_2 0
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#define IO_SWITCH_COMMAND_NUM_1 1
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#define IO_SWITCH_COMMAND_NUM (IO_SWITCH_COMMAND_NUM_2<<IO_SWITCH_COMMAND_NUM_Pos)
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//0x42
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#define OWB_6_8_DATA_OFFSET_Pos 0
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#define OWB_6_8_DATA_OFFSET (0<<OWB_6_8_DATA_OFFSET_Pos)
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#define DUPLEX_IO_OVERLAP_TIME_Pos 12
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#define DUPLEX_IO_OVERLAP_TIME_126NS 0
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#define DUPLEX_IO_OVERLAP_TIME_252NS 1
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#define DUPLEX_IO_OVERLAP_TIME (DUPLEX_IO_OVERLAP_TIME_126NS<<DUPLEX_IO_OVERLAP_TIME_Pos)
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#define LAST_CHIP_TX_FREQ_Pos 13
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#define LAST_CHIP_TX_FREQ_FOLLOW_RX 0
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#define LAST_CHIP_TX_FREQ_FIX500K 1
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#define LAST_CHIP_TX_FREQ (LAST_CHIP_TX_FREQ_FOLLOW_RX<<LAST_CHIP_TX_FREQ_Pos)
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#define DELAY_CHANGE_IO_CMD_Pos 14
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#define DELAY_CHANGE_IO_CMD_8_16US 0
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#define DELAY_CHANGE_IO_CMD_2_10US 1
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#define DELAY_CHANGE_IO_CMD_4_12US 2
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#define DELAY_CHANGE_IO_CMD_16_24US 3
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#define DELAY_CHANGE_IO_CMD (DELAY_CHANGE_IO_CMD_8_16US<<DELAY_CHANGE_IO_CMD_Pos)
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//0x47
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#define HEADROOM_Pos 0
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#define HEADROOM_200MV 0
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#define HEADROOM_250MV 1
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#define HEADROOM_300MV 2
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#define HEADROOM_350MV 3
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#define HEADROOM_400MV 4
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#define HEADROOM_450MV 5
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#define HEADROOM_500MV 6
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#define HEADROOM_550MV 7
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#define HEADROOM_600MV 8
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#define HEADROOM_650MV 9
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#define HEADROOM_700MV 10
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#define HEADROOM_800MV 11
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#define HEADROOM_900MV 12
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#define HEADROOM_1000MV 13
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#define HEADROOM_1100MV 14
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#define HEADROOM_1200MV 15
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#define HEADROOM (HEADROOM_400MV<<HEADROOM_Pos) //headroom<6F><6D><EFBFBD><EFBFBD>
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//0x48
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#define MOPICC_X1D50_Pos 0
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#define MOPICC_X1D50_DISABLE 0
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#define MOPICC_X1D50_ENABLE 1
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#define MOPICC_X1D50 (MOPICC_X1D50_DISABLE<<MOPICC_X1D50_Pos)
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#define CLK_ALWAYS_ON_Pos 1
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#define CLK_ALWAYS_ON_DISABLE 0
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#define CLK_ALWAYS_ON_ENABLE 1
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#define CLK_ALWAYS_ON (CLK_ALWAYS_ON_DISABLE<<CLK_ALWAYS_ON_Pos)
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#define OPEN_LV_Pos 2
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#define OPEN_LV_50MV 0
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#define OPEN_LV_80MV 1
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#define OPEN_LV_100MV 2
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#define OPEN_LV_130MV 3
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#define OPEN_LV (OPEN_LV_80MV<<OPEN_LV_Pos)
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#define PWM_COMPENSATION_TIME_Pos 4
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#define PWM_COMPENSATION_TIME_97NS 0
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#define PWM_COMPENSATION_TIME_328NS 1
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#define PWM_COMPENSATION_TIME_484US 2
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#define PWM_COMPENSATION_TIME_706NS 3
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#define PWM_COMPENSATION_TIME (PWM_COMPENSATION_TIME_706NS<<PWM_COMPENSATION_TIME_Pos)
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#define MOPICC_X2_Pos 6
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#define MOPICC_X2_DISBALE 0
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#define MOPICC_X2_ENABLE 1
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#define MOPICC_X2 (MOPICC_X2_DISBALE<<MOPICC_X2_Pos)
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#define BFI_VRR_Pos 7
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#define BFI_VRR_DISABLE 0
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#define BFI_VRR_ENABLE 1
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#define BFI_VRR (BFI_VRR_DISABLE<<BFI_VRR_Pos)
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#define LDO_3V3_Pos 8
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#define LDO_3V3_DISABLE 0
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#define LDO_3V3_ENABLE 1
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#define LDO_3V3 (LDO_3V3_DISABLE<<LDO_3V3_Pos)
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#define BURST_MODE_Pos 9
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#define BURST_MODE_DISABLE 0
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#define BURST_MODE_ENABLE 1
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#define BURST_MODE (BURST_MODE_DISABLE<<BURST_MODE_Pos)
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#define PWM_COMPENSATION_Pos 10
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#define PWM_COMPENSATION_NO 0
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#define PWM_COMPENSATION_WITH 1
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#define PWM_COMPENSATION (PWM_COMPENSATION_NO<<PWM_COMPENSATION_Pos)
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#define FAULT_SAMPLE_BFI_Pos 11
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#define FAULT_SAMPLE_BFI_ENABLE 0
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#define FAULT_SAMPLE_BFI_DISABLE 1
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#define FAULT_SAMPLE_BFI (FAULT_SAMPLE_BFI_DISABLE<<FAULT_SAMPLE_BFI_Pos)
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#define DOS_OUTPUT_OH_SEL_Pos 12
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#define DOS_OUTPUT_OH_LOCKED_STATE 0
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#define DOS_OUTPUT_OH_REAL 1
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#define DOS_OUTPUT_OH_SEL (DOS_OUTPUT_OH_LOCKED_STATE<<DOS_OUTPUT_OH_SEL_Pos)
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#define OPEN_DEBOUNCE_TIME_Pos 13
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#define OPEN_DEBOUNCE_TIME_3_TPWM 0
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#define OPEN_DEBOUNCE_TIME_4_TPWM 1
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#define OPEN_DEBOUNCE_TIME_8_TPWM 2
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#define OPEN_DEBOUNCE_TIME_16_TPWM 3
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#define OPEN_DEBOUNCE_TIME_32_TPWM 4
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#define OPEN_DEBOUNCE_TIME_64_TPWM 5
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#define OPEN_DEBOUNCE_TIME_96_TPWM 6
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#define OPEN_DEBOUNCE_TIME_128_TPWM 7
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#define OPEN_DEBOUNCE_TIME (OPEN_DEBOUNCE_TIME_16_TPWM<<OPEN_DEBOUNCE_TIME_Pos)
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//Reg49
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#define BFI_VRR_DAC_MULTIPLICATION_Pos 0
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#define BFI_VRR_DAC_MULTIPLICATION (0<<BFI_VRR_DAC_MULTIPLICATION_Pos) //9BITS
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#define UART_TRANS_TYPE_Pos 9
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#define UART_TRANS_DATA 0
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#define UART_TRANS_FAULT 1
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#define UART_TRANS_TYPE (UART_TRANS_FAULT<<UART_TRANS_TYPE_Pos)
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#define UART_CRC_Pos 10
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#define UART_WITHOUT_CRC 0
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#define UART_WITH_CRC 1
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#define UART_CRC (UART_WITHOUT_CRC<<UART_CRC_Pos)
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#define UART_STOP_BIT_Pos 11
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#define UART_STOP_1BIT 0
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#define UART_STOP_1_5BIT 1
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#define UART_STOP_2BIT 2
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#define UART_STOP_BIT (UART_STOP_1BIT<<UART_STOP_BIT_Pos)
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#define UART_FREQ_Pos 13
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#define UART_FREQ_19200 0
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#define UART_FREQ_38400 1
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#define UART_FREQ_57600 2
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#define UART_FREQ_115200 3
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#define UART_FREQ_115200_DEFAULT 4
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#define UART_FREQ_230400 5
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#define UART_FREQ_460800 6
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#define UART_FREQ_921600 7
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#define UART_FREQ (UART_FREQ_115200_DEFAULT<<UART_FREQ_Pos)
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//Reg4A
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#define OTP_LV_Pos 0
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#define OTP_LV_155__125 0
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#define OTP_LV_145__115 1
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#define OTP_LV_135__105 2
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#define OTP_LV_125__95 3
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#define OTP_LV (OTP_LV_145__115<<OTP_LV_Pos)
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#define SHORT_DET_DAC_Pos 2
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#define SHORT_DET_DAC_ENABLE 0
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#define SHORT_DET_DAC_DISABLE 1
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#define SHORT_DET_DAC (SHORT_DET_DAC_ENABLE<<SHORT_DET_DAC_Pos)
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#define IDAC_REF_Pos 3
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#define IDAC_REF_200MV_350MV 0
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#define IDAC_REF_160MV_310MV 1
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#define IDAC_REF_120MV_270MV 2
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#define IDAC_REF_80MV_230MV 3
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#define IDAC_REF (IDAC_REF_80MV_230MV<<IDAC_REF_Pos)
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#define SPIKE_FILTER_TIME_Pos 5
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#define SPIKE_FILTER_TIME_2_2NS 0
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#define SPIKE_FILTER_TIME_4_2NS 1
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#define SPIKE_FILTER_TIME (SPIKE_FILTER_TIME_2_2NS<<SPIKE_FILTER_TIME_Pos)
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#define SPIKE_FILTER_Pos 6
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#define SPIKE_FILTER_BYPASS 0
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#define SPIKE_FILTER_USE 1
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#define SPIKE_FILTER (SPIKE_FILTER_BYPASS<<SPIKE_FILTER_Pos)
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#define ONE_WIRE_DEGLITCH_TIME_Pos 7
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#define ONE_WIRE_DEGLITCH_TIME_2_TOSC 0
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#define ONE_WIRE_DEGLITCH_TIME_4_TOSC 1
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#define ONE_WIRE_DEGLITCH_TIME_8_TOSC 2
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#define ONE_WIRE_DEGLITCH_TIME_32_TOSC 3
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#define ONE_WIRE_DEGLITCH_TIME (ONE_WIRE_DEGLITCH_TIME_2_TOSC<<ONE_WIRE_DEGLITCH_TIME_Pos)
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#define MOPICC_CONFIG_Pos 10
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#define MOPICC_CONFIG_100 0
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#define MOPICC_CONFIG_75 1
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#define MOPICC_CONFIG_50 2
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#define MOPICC_CONFIG_25 3
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#define MOPICC_CONFIG_25_1 4
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#define MOPICC_CONFIG_18_75 5
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#define MOPICC_CONFIG_12_5 6
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#define MOPICC_CONFIG_6_25 7
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#define MOPICC_CONFIG (MOPICC_CONFIG_100<<MOPICC_CONFIG_Pos)
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#define SHORT_DETECTION_THRESHOLD_Pos 13
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#define SHORT_DETECTION_THRESHOLD_4 0
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#define SHORT_DETECTION_THRESHOLD_8 1
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#define SHORT_DETECTION_THRESHOLD_16 2
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#define SHORT_DETECTION_THRESHOLD_31 3
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#define SHORT_DETECTION_THRESHOLD (SHORT_DETECTION_THRESHOLD_4<<SHORT_DETECTION_THRESHOLD_Pos)
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#define CHANNEL_DELAY_UPDATE_Pos 15
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#define CHANNEL_DELAY_UPDATE_WAIT_PWM 0
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#define CHANNEL_DELAY_UPDATE_IMMEDIATELY 1
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#define CHANNEL_DELAY_UPDATE (CHANNEL_DELAY_UPDATE_WAIT_PWM<<CHANNEL_DELAY_UPDATE_Pos)
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//Reg4B
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#define BFI_VRR_BEGIN_CYCLE_Pos 0
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#define BFI_VRR_BEGIN_CYCLE (0<<BFI_VRR_BEGIN_CYCLE_Pos) //9BIT
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#define READ_BACK_MODE_Pos 10
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#define NOT_SENT_READ_BACK_CMD_GET_EOP 0
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#define SENT_READ_BACK_CMD_GET_EOP 1
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#define READ_BACK_MODE (NOT_SENT_READ_BACK_CMD_GET_EOP<<READ_BACK_MODE_Pos)
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#define READ_BACK_EOP_SOP_TYPE_Pos 11
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#define READ_BACK_EOP_SOP_TYPE_FAULT 0
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#define READ_BACK_EOP_SOP_TYPE_REGISTER 1
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#define READ_BACK_EOP_SOP_TYPE (READ_BACK_EOP_SOP_TYPE_FAULT<<READ_BACK_EOP_SOP_TYPE_Pos)
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#define FRAME_SPACE_Pos 12
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#define FRAME_SPACE_4096_TOSC 0
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#define FRAME_SPACE_2048_TOSC 1
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#define FRAME_SPACE_1024_TOSC 2
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#define FRAME_SPACE_512_TOSC 3
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#define FRAME_SPACE_256_TOSC 4
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#define FRAME_SPACE_128_TOSC 5
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#define FRAME_SPACE_64_TOSC 6
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#define FRAME_SPACE_32_TOSC 7
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#define FRAME_SPACE (FRAME_SPACE_4096_TOSC<<FRAME_SPACE_Pos)
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#define DC_DITHER_DC_PWM_Pos 15
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#define DC_DITHER_DC_PWM_DISABLE 0
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#define DC_DITHER_DC_PWM_ENABLE 1
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#define DC_DITHER_DC_PWM (DC_DITHER_DC_PWM_DISABLE<<DC_DITHER_DC_PWM_Pos)
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//Reg4c
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#define CHANNEL_GROUP_Pos 0
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#define CHANNEL_GROUP_NO 0
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#define CHANNEL_GROUP_2_CHANNEL 1
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#define CHANNEL_GROUP_4_CHANNEL 2
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#define CHANNEL_GROUP (CHANNEL_GROUP_NO<<CHANNEL_GROUP_Pos)
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#define SHORT_FIX_PWM_Pos 2
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#define SHORT_FIX_PWM_DISABLE 0
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#define SHORT_FIX_PWM_ENABLE 1
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#define SHORT_FIX_PWM (SHORT_FIX_PWM_DISABLE<<SHORT_FIX_PWM_Pos)
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#define FAULT_DEGLITCH_TIME_Pos 3
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#define FAULT_DEGLITCH_TIME_0_5US 0
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#define FAULT_DEGLITCH_TIME_1US 1
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#define FAULT_DEGLITCH_TIME_2US 2
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#define FAULT_DEGLITCH_TIME_3US 3
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#define FAULT_DEGLITCH_TIME (FAULT_DEGLITCH_TIME_1US<<FAULT_DEGLITCH_TIME_Pos)
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#define BFI_CRC_ERR_REPEAT_Pos 5
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#define BFI_CRC_ERR_REPEAT_DISABLE 0
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#define BFI_CRC_ERR_REPEAT_ENABLE 1
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#define BFI_CRC_ERR_REPEAT (BFI_CRC_ERR_REPEAT_DISABLE<<BFI_CRC_ERR_REPEAT_Pos)
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#define OH_DERATING_INCREASE_STEP_Pos 6
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#define OH_DERATING_INCREASE_STEP (0<<OH_DERATING_INCREASE_STEP_Pos)
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#define FAULT_BLANK_TIME_Pos 10
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#define FAULT_BLANK_TIME (0<<FAULT_BLANK_TIME_Pos) //6bits
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//Reg4D
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#define OH_TRIGGER_Pos 0
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#define OH_TRIGGER (8<<OH_TRIGGER_Pos) //(145<34><35>-N*5<><35>) 5bits
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#define OH_RECOVERY_Pos 5
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#define OH_RECOVERY (10<<OH_RECOVERY_Pos) //(145<34><35>-N*5<><35>) 5bits
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#define OH_DERATING_DECREASE_STEP_Pos 10
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#define OH_DERATING_DECREASE_STEP (0<<OH_DERATING_DECREASE_STEP_Pos)
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#define OH_DERATING_FREQ_Pos 14
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#define OH_DERATING_FREQ_4_TVSYNC 0
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#define OH_DERATING_FREQ_16_TVSYNC 1
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#define OH_DERATING_FREQ_64_TVSYNC 2
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#define OH_DERATING_FREQ_128_TVSYNC 3
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#define OH_DERATING_FREQ (OH_DERATING_FREQ_4_TVSYNC<<OH_DERATING_FREQ_Pos)
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//Reg4E
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#define PWM_CHANNEL_CLK_DIVIDED_Pos 0
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#define PWM_CHANNEL_CLK_DIVIDED (7<<PWM_CHANNEL_CLK_DIVIDED_Pos) //8BITS
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//#define PWM_CLK_SEL_DIVEDED_CLK 0
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//#define PWM_CLK_SEL_20480HZ 1
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//#define PWM_CLK_SEL PWM_CLK_SEL_DIVEDED_CLK
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#define SHORT_LV_Pos 9
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#define SHORT_LV_2V 0
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#define SHORT_LV_3V 1
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#define SHORT_LV_4V 2
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#define SHORT_LV_5V 3
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#define SHORT_LV_6V 4
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#define SHORT_LV_7V 5
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#define SHORT_LV_9V 6
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#define SHORT_LV_12V 7
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#define SHORT_LV (SHORT_LV_12V<<SHORT_LV_Pos)
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#define OPEN_DEBOUNCE_SEL_Pos 12
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#define OPEN_SEL_EOP 0
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#define OPEN_SEL_PWM 1
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#define OPEN_DEBOUNCE_SEL (OPEN_SEL_PWM<<OPEN_DEBOUNCE_SEL_Pos)
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#define BFI_MODE_Pos 13
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#define BFI_RESERVE_FIRST 0
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#define BFI_BLANK_FIRST 1
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#define BFI_MODE (BFI_RESERVE_FIRST<<BFI_MODE_Pos)
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#define BFI_Pos 14
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#define BFI_DISABLE 0
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#define BFI_ENABLE 1
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#define BFI (BFI_DISABLE<<BFI_Pos)
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#define SLEEP_MODE_EXIT_Pos 15
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#define SLEEP_MODE_EXIT_NO_RECOVERY 0
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#define SLEEP_MODE_EXIT_RECOVERY 1
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#define SLEEP_MODE_EXIT (SLEEP_MODE_EXIT_RECOVERY<<SLEEP_MODE_EXIT_Pos)
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//0X4F
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#define BFI_NUMBER_Pos 0
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#define BFI_NUMBER (0<<BFI_NUMBER_Pos) //9BITS
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#define BMC_SAMPLING_POINT_Pos 13
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#define BMC_SAMPLING_POINT_0 0
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#define BMC_SAMPLING_POINT_1 1
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#define BMC_SAMPLING_POINT_2 2
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#define BMC_SAMPLING_POINT_3 3
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#define BMC_SAMPLING_POINT (BMC_SAMPLING_POINT_1<<BMC_SAMPLING_POINT_Pos)
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#define MUX_OPTION_Pos 15
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#define MUX_OPTION_OWB 0
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#define MUX_OPTION_OWS 1
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||
#define MUX_OPTION (MUX_OPTION_OWS<<MUX_OPTION_Pos)
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||
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||
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||
//0X7B
|
||
#define GLOBAL_DAC_Pos 0
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||
#define GLOBAL_DAC (33<<GLOBAL_DAC_Pos) //18+N*0.66mA N:register value 6bits
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||
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||
|
||
//0x46
|
||
#define SICK_FAULT_DISABLE 0 // 0:Enable sick dection 1:Disable sick dection
|
||
#define OPEN_FALUT_DISABLE 0 // 0:Enable open dection 1:Disable open dection
|
||
#define SHORT_FAULT_DISABLE 0 // 0:Enable short dection 1:Disable short dection
|
||
#define OTP_FAULT_DISABLE 0 // 0:Enable OTP dection 1:Disable OTP dection
|
||
#define OTP_OFF_DISABLE 0 // 0:Turn off pwm when OTP 1:not turn off pwm when OTP
|
||
#define OTP_REC_DISABLE 0 // 0:recovery pwm when OTP relieve 1:not auto recovery pwm when OTP relieve
|
||
#define OPEN_OFF_DISABLE 1 // 0:turn off pwm when open fault detected 1:not turn off pwm when open fault detected
|
||
#define SHORT_OFF_DISABLE 0 // 0:turn off pwm when short fault detected 1:not turn off pwm when short fault detected
|
||
#define OWB_DATA_OFFSET_ENABLE 0 // 0: disable OWB_data_offset_register 1: enable OWB_data_offset_register
|
||
#define PWM_HIGH_TIME_FAULT_DISABLE 0 // 0:enable pwm high time detect function 1:disable pwm high time detect function
|
||
#define OH_DISABLE 0 // 0:enable OH detect function 1:disable OH detect function
|
||
#define SICK_RANGE_SEL 0 // 0:sick detection related to open 1:sick detection not related to open
|
||
#define DIS_DOS_CRC 0 // 0:enable dis-dos communication CRC check 1:disable dis-dos communication CRC check
|
||
#define OH_DERATING_ENABLE 0 // 0:disable OH dreating 1:enable OH dreating
|
||
#define DUPLEX_ENABLE 0 // 0:disable duplex 1:enable duplex
|
||
#define CONFIG_DONE 1
|
||
|
||
|
||
#endif
|
||
|
||
#endif
|
||
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