435 lines
16 KiB
C
435 lines
16 KiB
C
#ifndef __HY8822_H
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#define __HY8822_H
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#ifdef HY8822
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#define CH_NUMBERS 4
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#define PWM_OFFSET 0
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#define BTI_WIDTH 20
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//Reg47
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#define RD_CHIP_NUM_Pos 0
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#define RD_CHIP_NUM (0<<RD_CHIP_NUM_Pos) //read chip num when read back after EOP
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#define RD_EOP_ADDR_Pos 8
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#define RD_EOP_ADDR (0<<RD_EOP_ADDR_Pos) //the register address of first chip sent read back command
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//Reg48
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#define OPEN_LV_Pos 2
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#define OPEN_LV_50MV 0
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#define OPEN_LV_80MV 1
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#define OPEN_LV_100MV 2
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#define OPEN_LV_130MV 3
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#define OPEN_LV (OPEN_LV_80MV<<OPEN_LV_Pos)
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#define RISE_FALL_TIME_Pos 4
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#define RISE_FALL_TIME_97NS 0
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#define RISE_FALL_TIME_328NS 1
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#define RISE_FALL_TIME_484NS 2
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#define RISE_FALL_TIME_706NS 3
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#define RISE_FALL_TIME (RISE_FALL_TIME_706NS<<RISE_FALL_TIME_Pos)
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#define DERATING_Pos 6
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#define NO_DERATING 0
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#define DAC_DERATING_50 1
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#define DAC_DERATING_25 2
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#define DAC_DERATING_12_5 3
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#define DERATING (NO_DERATING<<DERATING_Pos)
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#define CHANNEL_DELAY_Pos 8
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#define CHANNEL_DELAY_UPDATE_WAIT_PWM 0
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#define CHANNEL_DELAY_UPDATE_IMMEDIATELY 1
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#define CHANNEL_DELAY_UPDATE (CHANNEL_DELAY_UPDATE_WAIT_PWM<<CHANNEL_DELAY_Pos)
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#define MULTISTAGE_SENT_Pos 9
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#define MULTISTAGE_SENT_DISABLE 0
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#define MULTISTAGE_SENT_ENABLE 1
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#define MULTISTAGE_SENT (MULTISTAGE_SENT_DISABLE<<MULTISTAGE_SENT_Pos)
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#define FAULT_SAMPLE_Pos 10
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#define FAULT_SAMPLE_BFI_ENABLE 0
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#define FAULT_SAMPLE_BFI_DISABLE 1
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#define FAULT_SAMPLE_BFI (FAULT_SAMPLE_BFI_ENABLE<<FAULT_SAMPLE_Pos)
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#define DOS_OUTPUT_OH_Pos 11
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#define DOS_OUTPUT_OH_LOCKED_STATE 0
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#define DOS_OUTPUT_OH_REAL 1
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#define DOS_OUTPUT_OH_SEL (DOS_OUTPUT_OH_LOCKED_STATE<<DOS_OUTPUT_OH_Pos)
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#define CLK_DIP_ALWAYS_Pos 11
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#define CLK_DIP_ALWAYS_OFF 0
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#define CLK_DIP_ALWAYS_ON 1
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#define CLK_DIP_ALWAYS (CLK_DIP_ALWAYS_OFF<<CLK_DIP_ALWAYS_Pos)
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#define OPEN_DEBOUNCE_TIME_Pos 13
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#define OPEN_DEBOUNCE_TIME_3_TPWM 0
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#define OPEN_DEBOUNCE_TIME_4_TPWM 1
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#define OPEN_DEBOUNCE_TIME_8_TPWM 2
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#define OPEN_DEBOUNCE_TIME_16_TPWM 3
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#define OPEN_DEBOUNCE_TIME_32_TPWM 4
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#define OPEN_DEBOUNCE_TIME_64_TPWM 5
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#define OPEN_DEBOUNCE_TIME_96_TPWM 6
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#define OPEN_DEBOUNCE_TIME_128_TPWM 7
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#define OPEN_DEBOUNCE_TIME (OPEN_DEBOUNCE_TIME_16_TPWM<<OPEN_DEBOUNCE_TIME_Pos)
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//Reg49
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#define UART_TX_DATA_LENGTH_Pos 0
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#define UART_TX_DATA_LENGTH (16<<UART_TX_DATA_LENGTH_Pos)
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#define READ_BACK_MODE_SEL_Pos 8
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#define NOT_SENT_READ_BACK_MODE_GET_EOP 0
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#define SENT_READ_BACK_MODE_GET_EOP 1
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#define READ_BACK_MODE_SEL (NOT_SENT_READ_BACK_MODE_GET_EOP<<READ_BACK_MODE_SEL_Pos)
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#define DOS_SENT_PROTOCOL_TYPE_Pos 9
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#define DOS_SENT_PROTOCOL_TYPE_SPB 0
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#define DOS_SENT_PROTOCOL_TYPE_UART 1
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#define DOS_SENT_PROTOCOL_TYPE (DOS_SENT_PROTOCOL_TYPE_SPB<<DOS_SENT_PROTOCOL_TYPE_Pos)
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#define DOS_DELAY_NUM_Pos 10
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#define DOS_DELAY_NUM_20 0
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#define DOS_DELAY_NUM_40 1
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#define DOS_DELAY_NUM_60 2
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#define DOS_DELAY_NUM (DOS_DELAY_NUM_20<<DOS_DELAY_NUM_Pos)
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#define UART_FREQ_Pos 12
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#define UART_FREQ_19200 0
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#define UART_FREQ_38400 1
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#define UART_FREQ_57600 2
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#define UART_FREQ_115200 3
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#define UART_FREQ_115200_DEFAULT 4
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#define UART_FREQ_230400 5
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#define UART_FREQ_460800 6
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#define UART_FREQ_921600 7
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#define UART_FREQ (UART_FREQ_115200_DEFAULT<<UART_FREQ_Pos)
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#define READ_BACK_EOP_SOP_TYPE_Pos 15
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#define READ_BACK_EOP_SOP_TYPE_FAULT 0
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#define READ_BACK_EOP_SOP_TYPE_REGISTER 1
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#define READ_BACK_EOP_SOP_TYPE (READ_BACK_EOP_SOP_TYPE_REGISTER<<READ_BACK_EOP_SOP_TYPE_Pos)
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//Reg4A
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#define OTP_LV_Pos 0
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#define OTP_LV_155__125 0
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#define OTP_LV_145__115 1
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#define OTP_LV_135__105 2
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#define OTP_LV_125__95 3
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#define OTP_LV (OTP_LV_145__115<<OTP_LV_Pos)
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#define SHORT_DET_DAC_Pos 2
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#define SHORT_DET_DAC_ENABLE 0
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#define SHORT_DET_DAC_DISABLE 1
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#define SHORT_DET_DAC (SHORT_DET_DAC_ENABLE<<SHORT_DET_DAC_Pos)
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#define IDAC_REF_Pos 3
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#define IDAC_REF_120MV_270MV 0
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#define IDAC_REF_100MV_250MV 1
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#define IDAC_REF_80MV_230MV 2
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#define IDAC_REF_60MV_210MV 3
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#define IDAC_REF (IDAC_REF_120MV_270MV<<IDAC_REF_Pos)
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#define SPIKE_FILTER_TIME_Pos 5
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#define SPIKE_FILTER_TIME_2_2NS 0
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#define SPIKE_FILTER_TIME_4_2NS 1
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#define SPIKE_FILTER_TIME (SPIKE_FILTER_TIME_2_2NS<<SPIKE_FILTER_TIME_Pos)
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#define SPIKE_FILTER_Pos 6
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#define SPIKE_FILTER_BYPASS 0
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#define SPIKE_FILTER_USE 1
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#define SPIKE_FILTER (SPIKE_FILTER_BYPASS<<SPIKE_FILTER_Pos)
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#define ONE_WIRE_DEGLITCH_TIME_Pos 7
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#define ONE_WIRE_DEGLITCH_TIME_2_TOSC 0
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#define ONE_WIRE_DEGLITCH_TIME_4_TOSC 1
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#define ONE_WIRE_DEGLITCH_TIME_8_TOSC 2
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#define ONE_WIRE_DEGLITCH_TIME_32_TOSC 3
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#define ONE_WIRE_DEGLITCH_TIME (ONE_WIRE_DEGLITCH_TIME_4_TOSC<<ONE_WIRE_DEGLITCH_TIME_Pos)
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#define ADDRESS_DEBUG_MODE_Pos 9
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#define ADDRESS_DEBUG_MODE_DISABLE 0
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#define ADDRESS_DEBUG_MODE_ENABLE 1
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#define ADDRESS_DEBUG_MODE (ADDRESS_DEBUG_MODE_DISABLE<<ADDRESS_DEBUG_MODE_Pos)
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#define MOPICC_CONFIG_Pos 10
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#define MOPICC_CONFIG_100 0
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#define MOPICC_CONFIG_75 1
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#define MOPICC_CONFIG_50 2
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#define MOPICC_CONFIG_25 3
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#define MOPICC_CONFIG_25_1 4
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#define MOPICC_CONFIG_18_75 5
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#define MOPICC_CONFIG_12_5 6
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#define MOPICC_CONFIG_6_25 7
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#define MOPICC_CONFIG (MOPICC_CONFIG_100<<MOPICC_CONFIG_Pos)
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#define SHORT_DETECTION_THRESHOLD_Pos 13
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#define SHORT_DETECTION_THRESHOLD_4 0
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#define SHORT_DETECTION_THRESHOLD_8 1
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#define SHORT_DETECTION_THRESHOLD_16 2
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#define SHORT_DETECTION_THRESHOLD_31 3
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#define SHORT_DETECTION_THRESHOLD (SHORT_DETECTION_THRESHOLD_4<<SHORT_DETECTION_THRESHOLD_Pos)
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#define PWM_DITHER_Pos 15
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#define PWM_DITHER_DISABLE 0
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#define PWM_DITHER_ENABLE 1
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#define PWM_DITHER (PWM_DITHER_DISABLE<<PWM_DITHER_Pos)
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//Reg4c
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#define OH_DERATING_Pos 0
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#define OH_DERATING_FREQ_1_TVSYNC 0
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#define OH_DERATING_FREQ_4_TVSYNC 1
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#define OH_DERATING_FREQ_8_TVSYNC 2
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#define OH_DERATING_FREQ_16_TVSYNC 3
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#define OH_DERATING_FREQ (OH_DERATING_FREQ_1_TVSYNC<<OH_DERATING_Pos)
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#define SHORT_FIX_PWM_Pos 2
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#define SHORT_FIX_PWM_DISABLE 0
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#define SHORT_FIX_PWM_ENABLE 1
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#define SHORT_FIX_PWM (SHORT_FIX_PWM_DISABLE<<SHORT_FIX_PWM_Pos)
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#define FAULT_DEGLITCH_TIME_Pos 3
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#define FAULT_DEGLITCH_TIME_0_5US 0
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#define FAULT_DEGLITCH_TIME_1US 1
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#define FAULT_DEGLITCH_TIME_2US 2
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#define FAULT_DEGLITCH_TIME_3US 3
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#define FAULT_DEGLITCH_TIME (FAULT_DEGLITCH_TIME_1US<<FAULT_DEGLITCH_TIME_Pos)
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#define DOS_MODE_Pos 5
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#define DOS_MODE_OPEN_DRAIN 0
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#define DOS_MODE_CMOS 1
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#define DOS_MODE (DOS_MODE_CMOS<<DOS_MODE_Pos)
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#define CHANNEL_GPOUPING_Pos 6
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#define CHANNEL_GROUP_NO 0
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#define CHANNEL_GROUP_2_CHANNEL 1
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#define CHANNEL_GROUP_4_CHANNEL 2
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#define CHANNEL_GPOUPING (CHANNEL_GROUP_NO<<CHANNEL_GPOUPING_Pos)
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#define MIX_DC_LSB_Pos 8
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#define MIX_DC_LSB_0 0
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#define MIX_DC_LSB_1 1
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#define MIX_DC_LSB (MIX_DC_LSB_0<<MIX_DC_LSB_Pos)
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#define MIX_PWM_LSB_Pos 9
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#define MIX_PWM_LSB_0 0
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#define MIX_PWM_LSB_1 1
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#define MIX_PWM_LSB (MIX_PWM_LSB_0<<MIX_PWM_LSB_Pos)
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#define FAULT_BLANK_TIME_Pos 10
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#define FAULT_BLANK_TIME (10<<FAULT_BLANK_TIME_Pos) //(4*N+3) * Tclock_pwm (duty:0.3% ~ 24.9%) //6bits
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//Reg4D
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#define OH_LV_Pos 0
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#define OH_LV_145 0
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#define OH_LV_140 1
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#define OH_LV_135 2
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#define OH_LV_130 3
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#define OH_LV_125 4
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#define OH_LV_120 5
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#define OH_LV_115 6
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#define OH_LV_110 7
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#define OH_LV_105 8
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#define OH_LV_100 9
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#define OH_LV_95 10
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#define OH_LV_90 11
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#define OH_LV_85 12
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#define OH_LV_80 13
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#define OH_LV_75 14
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#define OH_LV_70 15
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#define OH_LV (OH_LV_105<<OH_LV_Pos)
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#define OH_RECOVERY_Pos 4
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#define OH_RECOVERY_140 0
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#define OH_RECOVERY_135 1
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#define OH_RECOVERY_130 2
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#define OH_RECOVERY_125 3
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#define OH_RECOVERY_120 4
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#define OH_RECOVERY_115 5
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#define OH_RECOVERY_110 6
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#define OH_RECOVERY_105 7
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#define OH_RECOVERY_100 8
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#define OH_RECOVERY_95 9
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#define OH_RECOVERY_90 10
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#define OH_RECOVERY_85 11
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#define OH_RECOVERY_80 12
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#define OH_RECOVERY_75 13
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#define OH_RECOVERY_70 14
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#define OH_RECOVERY_65 15
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#define OH_RECOVERY (OH_RECOVERY_95<<OH_RECOVERY_Pos)
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#define OH_DERATING_DECREASE_STEP_Pos 8
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#define OH_DERATING_DECREASE_STEP (2<<OH_DERATING_DECREASE_STEP_Pos)
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#define OH_DERATING_INCREASE_STEP_Pos 12
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#define OH_DERATING_INCREASE_STEP (1<<OH_DERATING_INCREASE_STEP_Pos)
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//Reg4E
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#define PWM_CHANNEL_CLK_DIVIDED_Pos 0
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#define PWM_CHANNEL_CLK_DIVIDED (7<<PWM_CHANNEL_CLK_DIVIDED_Pos) //
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#define PWM_CLK_SEL_Pos 8
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#define PWM_CLK_SEL_DIVEDED_CLK 0
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#define PWM_CLK_SEL_20480HZ 1
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#define PWM_CLK_SEL (PWM_CLK_SEL_DIVEDED_CLK<<PWM_CLK_SEL_Pos)
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#define SHORT_LV_Pos 9
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#define SHORT_LV_2V 0
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#define SHORT_LV_3V 1
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#define SHORT_LV_4V 2
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#define SHORT_LV_5V 3
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#define SHORT_LV_6V 4
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#define SHORT_LV_7V 5
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#define SHORT_LV_9V 6
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#define SHORT_LV_12V 7
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#define SHORT_LV (SHORT_LV_12V<<SHORT_LV_Pos)
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#define OPEN_DEBOUNCE_Pos 12
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#define OPEN_DEBOUNCE_SEL_EOP 0
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#define OPEN_DEBOUNCE_SEL_PWM 1
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#define OPEN_DEBOUNCE (OPEN_DEBOUNCE_SEL_PWM<<OPEN_DEBOUNCE_Pos)
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#define BFI_MODE_Pos 13
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#define BFI_MODE_RESERVE 0
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#define BFI_MODE_BLANK 1
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#define BFI_MODE (BFI_MODE_RESERVE<<BFI_MODE_Pos)
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#define BFI_Pos 14
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#define BFI_DISABLE 0
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#define BFI_ENABLE 1
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#define BFI (BFI_DISABLE<<BFI_Pos)
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#define SLEEP_MODE_EXIT_Pos 15
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#define SLEEP_MODE_EXIT_NO_RECOVERY 0
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#define SLEEP_MODE_EXIT_RECOVERY 1
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#define SLEEP_MODE_EXIT (SLEEP_MODE_EXIT_RECOVERY<<SLEEP_MODE_EXIT_Pos)
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//0X4F
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#define BFI_NUMBER_Pos 0
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#define BFI_NUMBER (0<<BFI_NUMBER_Pos) //9BITS
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#define LDO_3V3_Pos 9
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#define LDO_3V3_DISABLE 0
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#define LDO_3V3_ENABLE 1
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#define LDO_3V3 (LDO_3V3_ENABLE<<LDO_3V3_Pos)
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#define MOPICC_X1D5_CFG_D2A_Pos 10
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#define MOPICC_X1D5_CFG_D2A_NORMAL 0
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#define MOPICC_X1D5_CFG_D2A_1_5TIMERS 1
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#define MOPICC_X1D5_CFG_D2A (MOPICC_X1D5_CFG_D2A_NORMAL<<MOPICC_X1D5_CFG_D2A_Pos)
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#define MOPICC_X2_CFG_D3A_Pos 11
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#define MOPICC_X2_CFG_D3A_NORMAL 0
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#define MOPICC_X2_CFG_D3A_2TIMERS 1
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#define MOPICC_X2_CFG_D3A (MOPICC_X2_CFG_D3A_NORMAL<<MOPICC_X2_CFG_D3A_Pos)
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// #define DAC_133_BURST_DISABLE 0
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// #define DAC_133_BURST_ENABLE 1
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// #define DAC_133_BURST DAC_133_BURST_DISABLE
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// #define DAC_200_TURBO_DISABLE 0
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// #define DAC_200_TURBO_ENABLE 1
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// #define DAC_200_TURBO DAC_200_TURBO_DISABLE
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#define PWM_COMPENSATION_Pos 12
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#define PWM_COMPENSATION_NO 0
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#define PWM_COMPENSATION_400NS 1
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#define PWM_COMPENSATION (PWM_COMPENSATION_NO<<PWM_COMPENSATION_Pos)
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//0X5A
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#define HEADROOM_Pos 0
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#define HEADROOM_300MV 0
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#define HEADROOM_350MV 1
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#define HEADROOM_400MV 2
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#define HEADROOM_450MV 3
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#define HEADROOM_500MV 4
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#define HEADROOM_550MV 5
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#define HEADROOM_600MV 6
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#define HEADROOM_650MV 7
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#define HEADROOM_700MV 8
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#define HEADROOM_750MV 9
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#define HEADROOM_800MV 10
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#define HEADROOM_850MV 11
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#define HEADROOM_900MV 12
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#define HEADROOM_1000MV 13
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#define HEADROOM_1100MV 14
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#define HEADROOM_1200MV 15
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#define HEADROOM (HEADROOM_700MV<<HEADROOM_Pos)
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//0X5B
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#define FRAME_SPACE_PREM_NUMBER_CFG_Pos 0
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#define FRAME_SPACE_PREM_NUMBER_CFG_BY_DIS_DOS 0
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#define FRAME_SPACE_PREM_NUMBER_CFG_BY_REGISTER 1
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#define FRAME_SPACE_PREM_NUMBER_CFG (FRAME_SPACE_PREM_NUMBER_CFG_BY_REGISTER<<FRAME_SPACE_PREM_NUMBER_CFG_Pos)
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#define FRAME_SPACE_Pos 1
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#define FRAME_SPACE_1024_TOSC 0
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#define FRAME_SPACE_512_TOSC 1
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#define FRAME_SPACE_256_TOSC 2
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#define FRAME_SPACE_128_TOSC 3
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#define FRAME_SPACE (FRAME_SPACE_1024_TOSC<<FRAME_SPACE_Pos)
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#define PREAMBLE_NUMBER_Pos 3
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#define PREAMBLE_NUMBER_60_BIT 0
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#define PREAMBLE_NUMBER_40_BIT 1
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#define PREAMBLE_NUMBER_20_BIT 2
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#define PREAMBLE_NUMBER_10_BIT 3
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#define PREAMBLE_NUMBER (PREAMBLE_NUMBER_60_BIT<<PREAMBLE_NUMBER_Pos)
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#define DOS_FIX_FREQ_Pos 5
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#define DOS_FIX_FREQ_DISABLE 0
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#define DOS_FIX_FREQ_ENABLE 1
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#define DOS_FIX_FREQ (DOS_FIX_FREQ_ENABLE<<DOS_FIX_FREQ_Pos)
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#define DOS_OUTPUT_FREQ_Pos 6
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#define DOS_FREQ_500K 0
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#define DOS_FREQ_1M 1
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#define DOS_FREQ_1_5M 2
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#define DOS_FREQ_1_75M 3
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#define DOS_OUTPUT_FREQ (DOS_FREQ_500K<<DOS_OUTPUT_FREQ_Pos)
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#define DIS_DIP_CONNECT_Pos 8
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#define DIS_DIP_CONNECT_DISABLE 0
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#define DIS_DIP_CONNECT_ENABLE 1
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#define DIS_DIP_CONNECT (DIS_DIP_CONNECT_DISABLE<<DIS_DIP_CONNECT_Pos)
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#define BFI_VRR_MODE_Pos 9
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#define BFI_VRR_MODE_DISABLE 0
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#define BFI_VRR_MODE_DC_SET_BY_GLOAL_DC 1
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#define BFI_VRR_MODE_DC_DERATING_BY_OH_CONFIG 2
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#define BFI_VRR_MODE (BFI_VRR_MODE_DISABLE<<BFI_VRR_MODE_Pos)
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#define BFI_VRR_DAC_DERATE_Pos 11
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#define BFI_VRR_DAC_DERATE_DISABLE 0
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#define BFI_VRR_DAC_DERATE_ENABLE 1
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#define BFI_VRR_DAC_DERATE (BFI_VRR_DAC_DERATE_DISABLE<<BFI_VRR_DAC_DERATE_Pos)
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//0x7B
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#define GLOBAL_DAC 32 //80+N*2.5 ma
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#define SICK_FAULT_DISABLE 0 // 0:Enable sick dection 1:Disable sick dection
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#define OPEN_FALUT_DISABLE 0 // 0:Enable open dection 1:Disable open dection
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#define SHORT_FAULT_DISABLE 0 // 0:Enable short dection 1:Disable short dection
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#define OTP_FAULT_DISABLE 0 // 0:Enable OTP dection 1:Disable OTP dection
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#define OTP_OFF_DISABLE 0 // 0:Turn off pwm when OTP 1:not turn off pwm when OTP
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#define OTP_REC_DISABLE 0 // 0:recovery pwm when OTP relieve 1:not auto recovery pwm when OTP relieve
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#define OPEN_OFF_DISABLE 1 // 0:turn off pwm when open fault detected 1:not turn off pwm when open fault detected
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#define SHORT_OFF_DISABLE 0 // 0:turn off pwm when short fault detected 1:not turn off pwm when short fault detected
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#define DIP_CRC_CHECK_DISABLE 0 // 0:enable double-wire CRC check 1:disable double-wire CRC check
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#define PWM_HIGH_TIME_FAULT_DISABLE 0 // 0:enable pwm high time detect function 1:disable pwm high time detect function
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#define OH_DISABLE 0 // 0:enable OH detect function 1:disable OH detect function
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#define SICK_RANGE_SEL 0 // 0:sick detection related to open comparator result 1:sick detection not related to open comparator result
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#define DIS_DOS_CRC 0 // 0:enable double-wire CRC check 1:disable double-wire CRC check
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#define OH_DERATING_ENABLE 0 // 0:disable OH derate 1:enable OH derate
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#define CONFIG_DONE 1
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#endif
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#endif
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