185 lines
5.8 KiB
C
185 lines
5.8 KiB
C
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/*
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* Copyright(c) 2018-2021 Allwinnertech Co., Ltd.
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*
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* Hardware dram frequency scaling, for which code run in dram.
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*
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* Author: frank <frank@allwinnertech.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#define MDFS_DEBUG 0
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/* helper for debug */
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#if MDFS_DEBUG
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static void reg_dump(struct sunxi_dramfreq *dramfreq)
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{
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printk("MC_MDFSCR:%x\n", readl(dramfreq->dramcom_base + MC_MDFSCR));
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printk("VTFCR:%x\n", readl(dramfreq->dramctl_base + VTFCR));
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printk("RFSHTMG:%x\n", readl(dramfreq->dramctl_base + RFSHTMG));
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printk("DXnGCR0(0):%x\n", readl(dramfreq->dramctl_base + DXnGCR0(0)));
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printk("DXnGCR0(1):%x\n", readl(dramfreq->dramctl_base + DXnGCR0(1)));
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printk("DXnGCR0(2):%x\n", readl(dramfreq->dramctl_base + DXnGCR0(2)));
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printk("DXnGCR0(3):%x\n", readl(dramfreq->dramctl_base + DXnGCR0(3)));
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printk("ODTMAP:%x\n", readl(dramfreq->dramctl_base + ODTMAP));
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printk("_DRAM_CLK_REG:%x\n", readl(dramfreq->ccu_base + _DRAM_CLK_REG));
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printk("PGCR0:%x\n", readl(dramfreq->dramctl_base + PGCR0));
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}
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#endif
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/* CONFIG_ARCH_SUN8IW16 */
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#if defined(CONFIG_ARCH_SUN8IW16)
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#include <linux/arm-smccc.h>
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#include <linux/arisc/arisc.h>
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static int mdfs_dfs(struct sunxi_dramfreq *dramfreq, unsigned int freq)
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{
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struct arm_smccc_res res;
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arm_smccc_smc(ARM_SVC_ARISC_DRAM_DVFS_REQ, freq, 0, 0, 0, 0, 0, 0, &res);
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return res.a0;
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}
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#endif
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/* CONFIG_ARCH_SUN8IW18 */
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#if defined(CONFIG_ARCH_SUN8IW18)
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static int mdfs_dfs(struct sunxi_dramfreq *dramfreq, unsigned int freq)
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{
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struct dram_para_t *para = &dramfreq->dram_para;
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unsigned int rank_num;
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uint32_t reg_val;
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unsigned int trefi, trfc, ctrl_freq;
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unsigned int i = 0, n = 4;
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unsigned int div, source;
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unsigned int vtf ;
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//bit0 must be 0 for new MDFS process
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while (readl(dramfreq->dramcom_base + MC_MDFSCR) & 0x1)
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;
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//calculate source and divider
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if (para->dram_tpr9 != 0) {
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if (((para->dram_clk % freq) == 0) && ((para->dram_tpr9 % freq) == 0)) {
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if ((para->dram_clk / freq) > (para->dram_tpr9 / freq)) {
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source = 0;
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div = para->dram_tpr9 / freq;
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} else {
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source = 1;
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div = para->dram_clk / freq;
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}
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} else if ((para->dram_clk % freq) == 0) {
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source = 1;
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div = para->dram_clk / freq;
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} else if ((para->dram_tpr9 % freq) == 0) {
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source = 0;
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div = para->dram_tpr9 / freq;
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} else{
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printk("MDFS fail!\n");
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return 1;
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}
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} else {
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source = (para->dram_tpr13 >> 6) & 0x1;
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div = para->dram_clk / freq;
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}
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ctrl_freq = freq >> 1;
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if ((para->dram_type == 3) || (para->dram_type == 2)) {
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trefi = ((7800 * ctrl_freq) / 1000 + ((((7800 * ctrl_freq) % 1000) != 0) ? 1 : 0)) / 32;
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trfc = (350 * ctrl_freq) / 1000 + ((((350 * ctrl_freq) % 1000) != 0) ? 1 : 0);
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} else {
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trefi = ((3900 * ctrl_freq) / 1000 + ((((3900 * ctrl_freq) % 1000) != 0) ? 1 : 0)) / 32;
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trfc = (210 * ctrl_freq) / 1000 + ((((210 * ctrl_freq) % 1000) != 0) ? 1 : 0);
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}
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/*turn off vtf*/
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vtf = (readl(dramfreq->dramctl_base + VTFCR) >> 8) & 0x3;
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if (vtf) {
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reg_val = readl(dramfreq->dramctl_base + VTFCR);
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reg_val &= ~(0x3 << 8);
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writel(reg_val, dramfreq->dramctl_base + VTFCR);
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}
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/* set dual buffer for timing change and power save */
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reg_val = readl(dramfreq->dramcom_base + MC_MDFSCR);
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/* VTC dual buffer can not be used */
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reg_val |= (0x1U << 15);
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writel(reg_val, dramfreq->dramcom_base + MC_MDFSCR);
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/* change refresh timing */
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reg_val = readl(dramfreq->dramctl_base + RFSHTMG);
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reg_val &= ~((0xfff << 0) | (0xfff << 16));
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reg_val |= ((trfc << 0) | (trefi << 16));
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writel(reg_val, dramfreq->dramctl_base + RFSHTMG);
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/* change ODT status for power save */
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if (!((para->dram_tpr13 >> 12) & 0x1)) {
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if (freq > 400) {
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if ((para->dram_odt_en & 0x1)) {
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for (i = 0; i < n; i++) {
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//byte 0/byte 1
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reg_val = readl(dramfreq->dramctl_base + DXnGCR0(i));
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reg_val &= ~(0x3U << 4);
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reg_val |= (0x0 << 4); //ODT dynamic
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writel(reg_val, dramfreq->dramctl_base + DXnGCR0(i));
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}
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rank_num = readl(dramfreq->dramcom_base + MC_WORK_MODE) & 0x1;
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if (rank_num) {
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writel(0x303, dramfreq->dramctl_base + ODTMAP);
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} else {
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writel(0x201, dramfreq->dramctl_base + ODTMAP);
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}
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}
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} else {
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if ((para->dram_odt_en & 0x1)) {
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for (i = 0; i < n; i++) {
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//byte 0/byte 1
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reg_val = readl(dramfreq->dramctl_base + DXnGCR0(i));
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reg_val &= ~(0x3U << 4);
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reg_val |= (0x2 << 4); //ODT off
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writel(reg_val, dramfreq->dramctl_base + DXnGCR0(i));
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}
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writel(0x0, dramfreq->dramctl_base + ODTMAP);
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}
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}
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}
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//set the DRAM_CFG_REG divider in CCMU
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reg_val = readl(dramfreq->ccu_base + _DRAM_CLK_REG);
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reg_val &= ~(0xf << 0);
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reg_val |= ((div - 1) << 0);
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reg_val &= ~(0x3 << 24);
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// reg_val |= (source << 24);
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reg_val |= (0x1 << 24); //AW1821Ö»ÓÐPLL_DDR0£¬Ð´¹Ì¶¨Öµ
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writel(reg_val, dramfreq->ccu_base + _DRAM_CLK_REG);
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/* set MDFS register */
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reg_val = readl(dramfreq->dramcom_base + MC_MDFSCR);
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reg_val |= (0x1 << 4); //bypass
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// reg_val |= (0x1 << 13); //pad hold
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reg_val &= ~(0x1U << 1); //DFS mode
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writel(reg_val, dramfreq->dramcom_base + MC_MDFSCR);
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reg_val = readl(dramfreq->dramcom_base + MC_MDFSCR);
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reg_val |= (0x1U << 0); //start mdfs
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writel(reg_val, dramfreq->dramcom_base + MC_MDFSCR);
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/* wait for process finished */
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while (readl(dramfreq->dramcom_base + MC_MDFSCR) & 0x1)
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;
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/* turn off dual buffer */
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reg_val = readl(dramfreq->dramcom_base + MC_MDFSCR);
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reg_val &= ~(0x1U << 15);
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// reg_val &= ~(0x1 << 13); //pad hold
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writel(reg_val, dramfreq->dramcom_base + MC_MDFSCR);
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/*turn on vtf*/
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if (vtf) {
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reg_val = readl(dramfreq->dramctl_base + VTFCR);
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reg_val |= (0x3<<8);
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writel(reg_val, dramfreq->dramctl_base + VTFCR);
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}
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return 0;
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}
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#endif /* CONFIG_ARCH_SUN8IW18 */
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