243 lines
8.8 KiB
C
243 lines
8.8 KiB
C
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/*
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* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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*
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* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
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* the the People's Republic of China and other countries.
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* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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*
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* DISCLAIMER
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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* IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
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* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
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* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ASM_RISCV_CSR_H
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#define _ASM_RISCV_CSR_H
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#include "asm.h"
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#include "consts.h"
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/* Status register flags */
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#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
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#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
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#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
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#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
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#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
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#define SR_FS_OFF _AC(0x00000000, UL)
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#define SR_FS_INITIAL _AC(0x00002000, UL)
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#define SR_FS_CLEAN _AC(0x00004000, UL)
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#define SR_FS_DIRTY _AC(0x00006000, UL)
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#define SR_XS _AC(0x00018000, UL) /* Extension Status */
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#define SR_XS_OFF _AC(0x00000000, UL)
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#define SR_XS_INITIAL _AC(0x00008000, UL)
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#define SR_XS_CLEAN _AC(0x00010000, UL)
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#define SR_XS_DIRTY _AC(0x00018000, UL)
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#define MR_MPP _AC(0x00001800, UL) /* Previously Machine */
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#define MR_MPIE _AC(0x00000080, UL) /* Previously Machine */
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#define MR_MIE _AC(0x00000008, UL) /* Previously Machine */
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#ifndef CONFIG_64BIT
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#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */
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#else
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#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */
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#endif
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/* SATP flags */
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#ifndef CONFIG_64BIT
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#define SATP_PPN _AC(0x003FFFFF, UL)
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#define SATP_MODE_32 _AC(0x80000000, UL)
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#define SATP_MODE SATP_MODE_32
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#else
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#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
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#define SATP_MODE_39 _AC(0x8000000000000000, UL)
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#define SATP_MODE SATP_MODE_39
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#define SATP_ASID_BITS 16
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#define SATP_ASID_SHIFT 44
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#define SATP_ASID_MASK _AC(0xFFFF, UL)
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#endif
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/* SCAUSE */
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#define SCAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
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#define IRQ_U_SOFT 0
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#define IRQ_S_SOFT 1
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#define IRQ_M_SOFT 3
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#define IRQ_U_TIMER 4
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#define IRQ_S_TIMER 5
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#define IRQ_M_TIMER 7
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#define IRQ_U_EXT 8
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#define IRQ_S_EXT 9
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#define IRQ_M_EXT 11
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#define IRQ_S_PMU 17
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#define EXC_INST_MISALIGNED 0
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#define EXC_INST_ACCESS 1
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#define EXC_INST_ILLEGAL 2
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#define EXC_BREAKPOINT 3
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#define EXC_LOAD_MISALIGN 4
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#define EXC_LOAD_ACCESS 5
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#define EXC_STORE_MISALIGN 6
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#define EXC_STORE_ACCESS 7
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#define EXC_SYSCALL_FRM_U 8
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#define EXC_SYSCALL_FRM_S 9
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#define EXC_SYSCALL_FRM_M 11
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#define EXC_INST_PAGE_FAULT 12
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#define EXC_LOAD_PAGE_FAULT 13
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#define EXC_STORE_PAGE_FAULT 15
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/* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */
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#define SIE_SSIE (_AC(0x1, UL) << IRQ_S_SOFT)
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#define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER)
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#define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT)
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#define SIE_SMIE (_AC(0x1, UL) << IRQ_S_PMU)
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/* MIE (Interrupt Enable) and MIP (Interrupt Pending) flags */
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#define MIE_MSIE (_AC(0x1, UL) << IRQ_M_SOFT)
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#define MIE_MTIE (_AC(0x1, UL) << IRQ_M_TIMER)
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#define MIE_MEIE (_AC(0x1, UL) << IRQ_M_EXT)
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#define CSR_CYCLE 0xc00
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#define CSR_TIME 0xc01
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#define CSR_INSTRET 0xc02
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#define CSR_SSTATUS 0x100
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#define CSR_SIE 0x104
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#define CSR_STVEC 0x105
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#define CSR_SCOUNTEREN 0x106
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#define CSR_SSCRATCH 0x140
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#define CSR_SEPC 0x141
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#define CSR_SCAUSE 0x142
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#define CSR_STVAL 0x143
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#define CSR_SIP 0x144
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#define CSR_SATP 0x180
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#define CSR_CYCLEH 0xc80
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#define CSR_TIMEH 0xc81
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#define CSR_INSTRETH 0xc82
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#define CSR_MSTATUS 0x300U
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#define CSR_MISA 0x301U
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#define CSR_MEDELEG 0x302U
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#define CSR_MIDELEG 0x303U
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#define CSR_MIE 0x304U
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#define CSR_MTVEC 0x305U
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#define CSR_MSCRATCH 0x340U
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#define CSR_MEPC 0x341U
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#define CSR_MCAUSE 0x342U
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#define CSR_MBADADDR 0x343U
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#define CSR_MIP 0x344U
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#define CSR_MCOR 0x7c2
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#define CSR_MHCR 0x7c1
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#define CSR_MCCR2 0x7c3
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#define CSR_MHINT 0x7c5
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#define CSR_MXSTATUS 0x7c0
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#define CSR_PLIC_BASE 0xfc1
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#define CSR_MRMR 0x7c6
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#define CSR_MRVBR 0x7c7
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#define MSTATUS_UIE 0x00000001U
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#define MSTATUS_SIE 0x00000002U
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#define MSTATUS_HIE 0x00000004U
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#define MSTATUS_MIE 0x00000008U
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#define MSTATUS_UPIE 0x00000010U
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#define MSTATUS_SPIE 0x00000020U
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#define MSTATUS_HPIE 0x00000040U
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#define MSTATUS_MPIE 0x00000080U
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#define MSTATUS_SPP 0x00000100U
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#define MSTATUS_HPP 0x00000600U
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#define MSTATUS_MPP 0x00001800U
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#define MSTATUS_FS 0x00006000U
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#define MSTATUS_XS 0x00018000U
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#define MSTATUS_MPRV 0x00020000U
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#define MSTATUS_PUM 0x00040000U
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#define MSTATUS_MXR 0x00080000U
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#define MSTATUS_VM 0x1F000000U
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#define MSTATUS32_SD 0x80000000U
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#define MSTATUS64_SD 0x8000000000000000U
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#ifndef __ASSEMBLY__
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#define csr_swap(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
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: "=r" (__v) : "rK" (__v) \
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: "memory"); \
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__v; \
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})
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#define csr_read(csr) \
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({ \
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register unsigned long __v; \
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__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
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: "=r" (__v) : \
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: "memory"); \
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__v; \
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})
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#define csr_write(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \
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: : "rK" (__v) \
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: "memory"); \
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})
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#define csr_read_set(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
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: "=r" (__v) : "rK" (__v) \
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: "memory"); \
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__v; \
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})
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#define csr_set(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \
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: : "rK" (__v) \
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: "memory"); \
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})
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#define csr_read_clear(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
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: "=r" (__v) : "rK" (__v) \
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: "memory"); \
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__v; \
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})
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#define csr_clear(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \
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: : "rK" (__v) \
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: "memory"); \
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})
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_RISCV_CSR_H */
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