295 lines
7.1 KiB
ArmAsm
295 lines
7.1 KiB
ArmAsm
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/*
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* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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*
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* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
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* the the People's Republic of China and other countries.
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* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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*
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* DISCLAIMER
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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* IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
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* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
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* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <csr.h>
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#include <excep.h>
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#ifdef CONFIG_FPU_DOUBLE
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#define FLOAD fld
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#define FSTORE fsd
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#else
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#define FLOAD flw
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#define FSTORE fsw
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#endif
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/*
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* unsigned long awos_arch_task_switch(unsigned long from, unsigned long to);
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*/
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.global awos_arch_task_switch
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awos_arch_task_switch:
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addi sp, sp, -14 * 4
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sw ra, 0*4(sp)
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csrr t0, mstatus
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li t1, MR_MPIE
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not t1, t1
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li t2, MR_MPP
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and t0, t0, t1
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or t0, t0, t2
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sw t0, 1*4(sp)
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sw s0, 2*4(sp)
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sw s1, 3*4(sp)
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sw s2, 4*4(sp)
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sw s3, 5*4(sp)
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sw s4, 6*4(sp)
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sw s5, 7*4(sp)
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sw s6, 8*4(sp)
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sw s7, 9*4(sp)
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sw s8, 10*4(sp)
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sw s9, 11*4(sp)
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sw s10, 12*4(sp)
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sw s11, 13*4(sp)
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sw sp, 0(a0)
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lw sp, 0(a1)
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jal check_gp_balance
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# load context switch registers.
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lw ra, 0*4(sp)
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# load mstatus register.
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lw t0, 1*4(sp)
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csrw mstatus,t0
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csrw mepc,ra
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lw s0, 2*4(sp)
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lw s1, 3*4(sp)
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lw s2, 4*4(sp)
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lw s3, 5*4(sp)
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lw s4, 6*4(sp)
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lw s5, 7*4(sp)
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lw s6, 8*4(sp)
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lw s7, 9*4(sp)
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lw s8, 10*4(sp)
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lw s9, 11*4(sp)
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lw s10, 12*4(sp)
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lw s11, 13*4(sp)
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addi sp, sp, 4*14
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move tp, a1
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#if 1
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mret
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#else
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#pseudo of 'jalr zero, 0(ra)'
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ret
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#endif
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/*
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* void awos_arch_first_task_start(unsigned long to);
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* r0 --> to
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*/
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.global awos_arch_first_task_start
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awos_arch_first_task_start:
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la t0, melis_kernel_running
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li t1, 1
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sb t1, (t0)
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lw sp, 0(a0)
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# load context switch registers.
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lw ra, 0*4(sp)
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#load mstatus register.
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lw t0, 1*4(sp)
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csrw mstatus,t0
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csrw mepc,ra
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lw s0, 2*4(sp)
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lw s1, 3*4(sp)
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lw s2, 4*4(sp)
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lw s3, 5*4(sp)
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lw s4, 6*4(sp)
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lw s5, 7*4(sp)
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lw s6, 8*4(sp)
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lw s7, 9*4(sp)
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lw s8, 10*4(sp)
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lw s9, 11*4(sp)
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lw s10, 12*4(sp)
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lw s11, 13*4(sp)
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addi sp, sp, 4*14
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move tp, a0
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move a1, a0
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move a0, zero
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# task top exit entry to ra.
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move ra, s3
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#if 1
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mret
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#else
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#pseudo of 'jalr zero, 0(ra)'
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ret
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#endif
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/*
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* uint32_t awos_arch_chksched_start(void);
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*/
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.global awos_arch_chksched_start
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awos_arch_chksched_start:
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la t0, melis_kernel_running
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lbu a0, (t0)
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ret
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/*
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* void awos_arch_save_fpu_status(fpu_context_t *);
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*/
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.global awos_arch_save_fpu_status
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awos_arch_save_fpu_status:
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li t0, SR_FS
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csrs mstatus, t0
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frcsr t1
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FSTORE f0, FPU_CTX_F0_F0(a0)
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FSTORE f1, FPU_CTX_F1_F0(a0)
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FSTORE f2, FPU_CTX_F2_F0(a0)
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FSTORE f3, FPU_CTX_F3_F0(a0)
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FSTORE f4, FPU_CTX_F4_F0(a0)
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FSTORE f5, FPU_CTX_F5_F0(a0)
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FSTORE f6, FPU_CTX_F6_F0(a0)
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FSTORE f7, FPU_CTX_F7_F0(a0)
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FSTORE f8, FPU_CTX_F8_F0(a0)
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FSTORE f9, FPU_CTX_F9_F0(a0)
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FSTORE f10, FPU_CTX_F10_F0(a0)
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FSTORE f11, FPU_CTX_F11_F0(a0)
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FSTORE f12, FPU_CTX_F12_F0(a0)
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FSTORE f13, FPU_CTX_F13_F0(a0)
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FSTORE f14, FPU_CTX_F14_F0(a0)
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FSTORE f15, FPU_CTX_F15_F0(a0)
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FSTORE f16, FPU_CTX_F16_F0(a0)
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FSTORE f17, FPU_CTX_F17_F0(a0)
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FSTORE f18, FPU_CTX_F18_F0(a0)
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FSTORE f19, FPU_CTX_F19_F0(a0)
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FSTORE f20, FPU_CTX_F20_F0(a0)
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FSTORE f21, FPU_CTX_F21_F0(a0)
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FSTORE f22, FPU_CTX_F22_F0(a0)
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FSTORE f23, FPU_CTX_F23_F0(a0)
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FSTORE f24, FPU_CTX_F24_F0(a0)
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FSTORE f25, FPU_CTX_F25_F0(a0)
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FSTORE f26, FPU_CTX_F26_F0(a0)
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FSTORE f27, FPU_CTX_F27_F0(a0)
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FSTORE f28, FPU_CTX_F28_F0(a0)
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FSTORE f29, FPU_CTX_F29_F0(a0)
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FSTORE f30, FPU_CTX_F30_F0(a0)
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FSTORE f31, FPU_CTX_F31_F0(a0)
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sw t1, FPU_CTX_FCSR_F0(a0)
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# clr FS domain
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csrc mstatus, t0
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# clean status woulw clr sr_sw;
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li t0, SR_FS_CLEAN
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csrs mstatus, t0
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ret
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/*
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* void awos_arch_restore_fpu_status(fpu_context_t *);
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*/
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.global awos_arch_restore_fpu_status
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awos_arch_restore_fpu_status:
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li t0, SR_FS
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lw t1, FPU_CTX_FCSR_F0(a0)
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csrs mstatus, t0
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FLOAD f0, FPU_CTX_F0_F0(a0)
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FLOAD f1, FPU_CTX_F1_F0(a0)
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FLOAD f2, FPU_CTX_F2_F0(a0)
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FLOAD f3, FPU_CTX_F3_F0(a0)
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FLOAD f4, FPU_CTX_F4_F0(a0)
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FLOAD f5, FPU_CTX_F5_F0(a0)
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FLOAD f6, FPU_CTX_F6_F0(a0)
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FLOAD f7, FPU_CTX_F7_F0(a0)
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FLOAD f8, FPU_CTX_F8_F0(a0)
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FLOAD f9, FPU_CTX_F9_F0(a0)
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FLOAD f10,FPU_CTX_F10_F0(a0)
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FLOAD f11,FPU_CTX_F11_F0(a0)
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FLOAD f12,FPU_CTX_F12_F0(a0)
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FLOAD f13,FPU_CTX_F13_F0(a0)
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FLOAD f14,FPU_CTX_F14_F0(a0)
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FLOAD f15,FPU_CTX_F15_F0(a0)
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FLOAD f16,FPU_CTX_F16_F0(a0)
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FLOAD f17,FPU_CTX_F17_F0(a0)
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FLOAD f18,FPU_CTX_F18_F0(a0)
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FLOAD f19,FPU_CTX_F19_F0(a0)
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FLOAD f20,FPU_CTX_F20_F0(a0)
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FLOAD f21,FPU_CTX_F21_F0(a0)
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FLOAD f22,FPU_CTX_F22_F0(a0)
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FLOAD f23,FPU_CTX_F23_F0(a0)
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FLOAD f24,FPU_CTX_F24_F0(a0)
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FLOAD f25,FPU_CTX_F25_F0(a0)
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FLOAD f26,FPU_CTX_F26_F0(a0)
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FLOAD f27,FPU_CTX_F27_F0(a0)
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FLOAD f28,FPU_CTX_F28_F0(a0)
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FLOAD f29,FPU_CTX_F29_F0(a0)
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FLOAD f30,FPU_CTX_F30_F0(a0)
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FLOAD f31,FPU_CTX_F31_F0(a0)
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fscsr t1
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# clr FS domain
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csrc mstatus, t0
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# clean status woulw clr sr_sw;
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li t0, SR_FS_CLEAN
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csrs mstatus, t0
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ret
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/*
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* void check_gp_balance(void);
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*/
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.global check_gp_balance
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check_gp_balance:
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.gplwr:
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auipc a2, %pcrel_hi(__global_pointer$)
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addi a2, a2,%pcrel_lo(.gplwr)
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1: # x3 is gp in abi
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bne gp, a2,1b
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ret
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/*
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* void delay_10insn(void);
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*/
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.global delay_10insn
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delay_10insn:
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li a0, 10
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beqz a0, 2f
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1:
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addi a0, a0, -1
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.rept 5
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nop
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.endr
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bnez a0, 1b
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2:
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ret
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.end
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