228 lines
11 KiB
C
228 lines
11 KiB
C
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/* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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*
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* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
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*the the People's Republic of China and other countries.
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* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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*
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* DISCLAIMER
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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* IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
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* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
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* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CLK_PERIPH_H__
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#define __CLK_PERIPH_H__
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#include "clk.h"
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#define SUNXI_CLK_PERIPH_CONFIG(name, _mux_reg, _mux_shift, _mux_width, \
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_div_reg, _div_mshift, _div_mwidth, _div_nshift, _div_nwidth, \
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_gate_flags, _enable_reg, _reset_reg, _bus_gate_reg, _drm_gate_reg, \
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_enable_shift, _reset_shift, _bus_gate_shift, _dram_gate_shift, _com_gate, _com_gate_off) \
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struct sunxi_clk_periph sunxi_clk_periph_config_##name = { \
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.mux = { \
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.reg = (volatile uint32_t *)_mux_reg, \
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.shift = _mux_shift, \
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.width = _mux_width, \
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}, \
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.divider = { \
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.reg = (volatile uint32_t *)_div_reg, \
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.mshift = _div_mshift, \
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.mwidth = _div_mwidth, \
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.nshift = _div_nshift, \
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.nwidth = _div_nwidth, \
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}, \
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.gate = { \
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.flags = _gate_flags, \
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.enable = (volatile uint32_t *)_enable_reg, \
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.reset = (volatile uint32_t *)_reset_reg, \
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.bus = (volatile uint32_t *)_bus_gate_reg, \
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.dram = (volatile uint32_t *)_drm_gate_reg, \
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.enb_shift = _enable_shift, \
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.rst_shift = _reset_shift, \
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.bus_shift = _bus_gate_shift, \
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.ddr_shift = _dram_gate_shift, \
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}, \
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.com_gate = _com_gate, \
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.com_gate_off = _com_gate_off, \
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}
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#define SUNXI_CLK_PERIPH(_name, _clk, _parent_arry) \
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clk_periph_t sunxi_clk_periph_##_name = { \
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.clk_core = { \
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.clk = _clk, \
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.clk_type = HAL_CLK_PERIPH, \
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.current_parent = HAL_CLK_UNINITIALIZED, \
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.current_parent_type = 0, \
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.clk_rate = 0, \
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.parent_rate = 0, \
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.clk_enbale = HAL_CLK_STATUS_DISABLED, \
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}, \
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.parent_arry = _parent_arry, \
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.parent_arry_size = ARRAY_SIZE(_parent_arry), \
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.config = &sunxi_clk_periph_config_##_name, \
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}
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#define SUNXI_PERIPH_INIT(_name, _clk, _parent_clk, _clk_rate) \
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clk_base_t sunxi_periph_clk_init_##_name = { \
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.clk = _clk, \
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.parent = _parent_clk, \
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.clk_rate = _clk_rate, \
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}
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/**
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* struct sunxi_clk_periph_gate - peripheral gate clock
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*
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* @flags: hardware-specific flags
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* @enable: enable register
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* @reset: reset register
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* @bus: bus gating resiter
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* @dram: dram gating register
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* @enb_shift: enable gate bit shift
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* @rst_shift: reset gate bit shift
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* @bus_shift: bus gate bit shift
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* @ddr_shift: dram gate bit shift
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*
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* Flags:
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* SUNXI_PERIPH_NO_GATE - this flag indicates that module gate is not allowed for this module.
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* SUNXI_PERIPH_NO_RESET - This flag indicates that reset is not allowed for this module.
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* SUNXI_PERIPH_NO_BUS_GATE - This flag indicates that bus gate is not allowed for this module.
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* SUNXI_PERIPH_NO_DDR_GATE - This flag indicates that dram gate is not allowed for this module.
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*/
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struct sunxi_clk_periph_gate
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{
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u32 flags;
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volatile uint32_t *enable;
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volatile uint32_t *reset;
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volatile uint32_t *bus;
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volatile uint32_t *dram;
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u8 enb_shift;
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u8 rst_shift;
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u8 bus_shift;
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u8 ddr_shift;
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};
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/**
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* struct sunxi_clk_periph_div - periph divider clock
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*
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* @reg: register containing divider
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* @mshift: shift to the divider-m bit field, div = (m+1)
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* @mwidth: width of the divider-m bit field
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* @nshift: shift to the divider-n bit field, div = (1<<n)
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* @nwidth: width of the divider-n bit field
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* @lock: register lock
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*
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* Flags:
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*/
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struct sunxi_clk_periph_div
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{
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volatile uint32_t *reg;
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u8 mshift;
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u8 mwidth;
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u8 nshift;
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u8 nwidth;
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//spinlock_t *lock;
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};
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/**
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* struct sunxi_clk_periph_mux - multiplexer clock
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*
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* @reg: register controlling multiplexer
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* @shift: shift to multiplexer bit field
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* @width: width of mutliplexer bit field
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* @lock: register lock
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*
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* Clock with multiple selectable parents. Implements .get_parent, .set_parent
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* and .recalc_rate
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*
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*/
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struct sunxi_clk_periph_mux
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{
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volatile uint32_t *reg;
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u8 shift;
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u8 width;
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//spinlock_t *lock;
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};
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struct sunxi_clk_comgate
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{
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const u8 *name;
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u16 val;
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u16 mask;
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u8 share;
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u8 res;
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};
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#define BUS_GATE_SHARE 0x01
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#define RST_GATE_SHARE 0x02
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#define MBUS_GATE_SHARE 0x04
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#define MOD_GATE_SHARE 0x08
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#define IS_SHARE_BUS_GATE(x) (x->com_gate?((x->com_gate->share & BUS_GATE_SHARE)?1:0):0)
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#define IS_SHARE_RST_GATE(x) (x->com_gate?((x->com_gate->share & RST_GATE_SHARE)?1:0):0)
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#define IS_SHARE_MBUS_GATE(x) (x->com_gate?((x->com_gate->share & MBUS_GATE_SHARE)?1:0):0)
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#define IS_SHARE_MOD_GATE(x) (x->com_gate?((x->com_gate->share & MOD_GATE_SHARE)?1:0):0)
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/**
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* struct sunxi-clk-periph - peripheral clock
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*
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* @hw: handle between common and hardware-specific interfaces
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* @flags: flags used across common struct clk, please take refference of the clk-provider.h
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* @lock: lock for protecting the periph clock operations
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* @mux: mux clock
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* @gate: gate clock
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* @divider: divider clock
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* @com_gate: the shared clock
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* @com_gate_off: bit shift to mark the flag in the com_gate
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* @priv_clkops: divider clock ops
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* @priv_regops: gate clock ops
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*/
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struct sunxi_clk_periph
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{
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//struct clk_hw hw;
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//unsigned long flags;
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//spinlock_t *lock;
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struct sunxi_clk_periph_mux mux;
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struct sunxi_clk_periph_gate gate;
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struct sunxi_clk_periph_div divider;
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struct sunxi_clk_comgate *com_gate;
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u8 com_gate_off;
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//struct clk_ops *priv_clkops;
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//struct sunxi_reg_ops *priv_regops;
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};
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hal_clk_status_t sunxi_clk_periph_get_parent(clk_periph_pt clk, u8 *parent_index);
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hal_clk_status_t sunxi_clk_periph_set_parent(clk_periph_pt clk, u8 index);
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hal_clk_status_t sunxi_clk_periph_enable(clk_periph_pt clk);
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hal_clk_status_t sunxi_clk_periph_is_enabled(clk_periph_pt clk);
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hal_clk_status_t sunxi_clk_periph_disable(clk_periph_pt clk);
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hal_clk_status_t sunxi_clk_periph_recalc_rate(clk_periph_pt clk, u32 *rate);
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u32 sunxi_clk_periph_round_rate(clk_periph_pt clk, u32 rate, u32 prate);
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hal_clk_status_t sunxi_clk_periph_set_rate(clk_periph_pt clk, u32 rate);
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#endif /* __MACH_SUNXI_CLK_PERIPH_H */
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