226 lines
7.1 KiB
ArmAsm
226 lines
7.1 KiB
ArmAsm
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/*
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* Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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.syntax unified
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#ifdef CONFIG_CPU_CM33F
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.cpu cortex-m33
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.fpu softvfp
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#elif (defined CONFIG_CPU_CM4F)
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.cpu cortex-m4
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.fpu softvfp
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#else
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.cpu cortex-m3
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#endif
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.thumb
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#ifdef CONFIG_ROM
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.equ RAM_TABLE_VMA, (0x00200000 + 0xc00)
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.global memcpy
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.global ram_table_adjust
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#endif
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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/* bottom of stack */
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//.word _sstack
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#ifdef CONFIG_ROM
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/* start address for the .ram_table section. defined in linker script */
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.word __ram_table_lma_start__
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/* end address for the .ram_table section. defined in linker script */
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.word __ram_table_lma_end__
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#endif
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/*.equ BootRAM, 0xF108F85F*/
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/**
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* @brief This is the code that gets called when the processor first
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* starts execution following a reset event. Only the absolutely
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* necessary set is performed, after which the application
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* supplied main() routine is called.
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* @param None
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* @retval : None
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*/
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr r0, =_estack
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mov sp, r0 /* set stack pointer */
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#ifdef CONFIG_CPU_CM33F
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//ldr r0, =_sstack /* set stack bottom */
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//msr msplim, r0
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#endif
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#ifdef CONFIG_ROM
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ldr r3, =ram_table_adjust /* adjust ram table lma */
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blx r3
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ldr r0, =RAM_TABLE_VMA
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ldr r1, =__ram_table_lma_start__ /* must be align 4 */
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ldr r2, =__ram_table_lma_end__
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sub r2, r2, r1
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cmp r2, #0
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bne ram_table_cpy
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b startup
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ram_table_cpy:
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cmp r1, r0
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beq startup
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ldr r3, =memcpy
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blx r3
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startup:
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#endif
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bl _start
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LoopForever:
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b LoopForever
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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*
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* @param None
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* @retval : None
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*/
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.extern exception_entry
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.section .cpu_text,"ax",%progbits
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.thumb_func
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.type Default_Handler, %function
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Default_Handler:
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#ifndef CONFIG_BOOTLOADER
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CPSID F
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TST LR, #0x04
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ITE EQ
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MRSEQ R0, MSP
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MRSNE R0, PSP
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STMDB.W R0!, {R4-R11}
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MRS R1, MSP
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MRS R2, PSP
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BL exception_entry
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#endif
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/******************************************************************************
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*
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* The minimal vector table for a Cortex M3. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* 0x0000.0000.
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*
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******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word _estack
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.word Reset_Handler
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.word Default_Handler // NMI_Handler // -14
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.word Default_Handler // HardFault_Handler
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.word Default_Handler // MemManage_Handler
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.word Default_Handler // BusFault_Handler
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.word Default_Handler // UsageFault_Handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word SVC_Handler // -5
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.word Default_Handler // DebugMon_Handler
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.word 0
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.word PendSV_Handler
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.word SysTick_Handler // -1
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/* External Interrupts */
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.word Default_Handler // DMA_IRQHandler // 0
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.word Default_Handler // GPIOA_IRQHandler
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.word Default_Handler // SDC0_IRQHandler
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.word Default_Handler // MBOX_A_IRQHandler or no use
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.word Default_Handler // UART0_IRQHandler
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.word Default_Handler // UART1_IRQHandler
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.word Default_Handler // SPI0_IRQHandler
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.word Default_Handler // SPI1_IRQHandler
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.word Default_Handler // I2C0_IRQHandler
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.word Default_Handler // I2C1_IRQHandler
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.word Default_Handler // WDG_IRQHandler // 10
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.word Default_Handler // TIMER0_IRQHandler
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.word Default_Handler // TIMER1_IRQHandler
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.word Default_Handler // RTC_SecAlarm_IRQHandler
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.word Default_Handler // RTC_WDayAlarm_IRQHandler
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.word Default_Handler // CSI_IRQHandler
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.word Default_Handler // I2S_IRQHandler
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.word Default_Handler // PWM_ECT_IRQHandler
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.word Default_Handler // CE_IRQHandler
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.word Default_Handler // GPADC_IRQHandler
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.word Default_Handler // GPIOB_IRQHandler // 20
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.word Default_Handler // DMIC_IRQHandler or no use
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.word Default_Handler // IRRX_IRQHandler
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.word Default_Handler // IRTX_IRQHandler
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.word Default_Handler // MBOX_N_IRQHandler or no use
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.word Default_Handler // A_WAKEUP_IRQHandler
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.word Default_Handler // FLASHC_IRQHandler
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.word Default_Handler // N_UART_IRQHandler or UART2_IRQHandler // 27
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.word Default_Handler // SDC1_IRQHandler
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.word Default_Handler // WIFIC_IRQHandler
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.word Default_Handler // CODEC_DAC_IRQHandler // 30
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.word Default_Handler // CODEC_ADC_IRQHandler
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.word Default_Handler // AVS_IRQHandler
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.word Default_Handler // GPIOC_IRQn
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.word Default_Handler // PSRAMC_IRQn // 34
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0 // 40
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0 // 47
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