137 lines
3.9 KiB
C
137 lines
3.9 KiB
C
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/*
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* drivers/char/sunxi-owc/sunxi-owc.h
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*
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* Copyright (C) 2019 Allwinner.
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* lihuaxing <lihuaxing@allwinnertech.com>
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*
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* SUNXI OWC Register Definition
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef __SUNXI_OWC_H__
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#define __SUNXI_OWC_H__
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//#include "smartcard.h"
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//#include "sunxi-scr-user.h"
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#define OWC_MODULE_NAME "sunxi_owc_char_class"
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#define OWC_IOCTL_BASE 'O'
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#define BIT_WRITE _IOW(OWC_IOCTL_BASE, 0, u8)
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#define BIT_READ _IOR(OWC_IOCTL_BASE, 1, u8)
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#define BYTE_WRITE _IOW(OWC_IOCTL_BASE, 2, u8)
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#define BYTE_READ _IOR(OWC_IOCTL_BASE, 3, u8)
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#define HDQ_WRITE _IOW(OWC_IOCTL_BASE, 4, u8)
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#define HDQ_READ _IOR(OWC_IOCTL_BASE, 5, u8)
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/* owc registers */
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#define OW_DATA (0x000)
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#define OW_CTL (0x004)
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#define OW_SMSC (0x008)
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#define OW_SMCRC (0x00c)
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#define OW_INT_STATUS (0x010)
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#define OW_INT_CTL (0x014)
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#define OW_FCLK (0x018)
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#define OW_LC (0x01c)
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#define SM_WR_RD_TCTL (0x020)
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#define SM_RST_PRESENCE_TCTL (0x024)
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#define SP_WR_RD_TCTL (0x028)
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#define SP_BR_TCTL (0x02c)
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/* owc intterrupt config register */
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#define OWC_INT_MASK 0X3F
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#define INTEN_DGCH (0x1<<5)
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#define INTEN_ST_CRC_FINI (0X1<<4)
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#define INTEN_WR_CPL (0X1<<3)
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#define INTEN_RD_CPL (0X1<<2)
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#define INTEN_SP_TIME_OUT (0x1<<1)
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#define INTEN_ST_INIT_SP_CPL (0X1<<0)
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/* owc interrupt status */
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#define INT_DGCH_OCCUR (0x1<<5)
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#define INT_ST_CRC_FINI (0x1<<4)
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#define INT_OW_WR_CPL (0x1<<3)
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#define INT_OW_RD_CPL (0x1<<2)
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#define INT_SP_TIME_OUT (0x1<<1)
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#define INT_ST_INIT_SP_CPL (0x1<<0)
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/* owc standard timing config */
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#define TSU 0x01
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#define TREC 0x01
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#define TRDV 0x0E
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#define TLOW0 0x45
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#define TLOW1 0x01
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#define TSLOT 0x78
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#define TPDL 0x46
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#define TPDH 0x05 /* slave presence first sample:<=0x1b for DS2431 */
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#define TRSTL 0x1E9
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#define TRSTH 0x1E9
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#define TIMEOUT 1000
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/* owc HDQ timing config */
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#define RD_SAMPLE_POINT 0
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#define THW1_INT 0x20
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#define THW1_DEC 0
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#define THW0 0x87
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#define TCYCH 0xBE
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#define TB 0xBE
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#define TBR 0x28
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#define OW_FCLK_MASK (0x1F<<16)
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#define OW_FCLK_D_MASK (0xFF)
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#define SCR_BUF_SIZE 256
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#define SCR_FIFO_DEPTH 8 /* just half of hw fifo size */
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#define SCR_RX_TRANSMIT_NOYET 0
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#define SCR_RX_TRANSMIT_TMOUT 1 /* time out */
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/* ROM command */
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#define SEARCH 0xF0
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#define READ_ROM 0x33
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#define MATCH_ROM 0x55
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#define JUMP_ROM 0xCC
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#define WARN_ROM 0xEC
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enum scr_atr_status {
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SCR_ATR_RESP_INVALID,
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SCR_ATR_RESP_FAIL,
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SCR_ATR_RESP_OK,
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};
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struct sunxi_owc {
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void __iomem *reg_base;
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struct clk *mclk;
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struct clk *pclk;
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struct platform_device *pdev;
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struct pinctrl *pctrl;
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struct resource *mem_res;
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struct class *owc_dev_class;
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struct device *owc_device;
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uint32_t clk_freq;
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uint32_t func_clk;
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uint32_t irq_num;
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struct cdev cdev;
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dev_t chrdev;
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spinlock_t owc_lock;
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bool presence_status;
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bool init_status;
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wait_queue_head_t r_wait;
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wait_queue_head_t w_wait;
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wait_queue_head_t crc_wait;
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bool write_flg;
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bool single_bit;
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u8 rom_data[10];
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u8 w_data[10];
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struct completion done;
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};
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#endif
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