292 lines
10 KiB
C
292 lines
10 KiB
C
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/*
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* drivers/spi/spif-sunxi.h
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*
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* Copyright (c) 2021-2028 Allwinnertech Co., Ltd.
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* SUNXI SPIF Register Definition
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*
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* 2021.6.24 liuyu <liuyu@allwinnertech.com>
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* 2022.5.5 lujianliang <lujianliang@allwinnertech.com>
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* creat thie file and support sun8i of Allwinner.
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*/
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#ifndef _SUNXI_SPI_H_
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#define _SUNXI_SPI_H_
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#include <linux/mtd/mtd.h>
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#include <linux/spi/spi-mem.h>
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#define CONFIG_SYS_CACHELINE_SIZE (64)
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#define CONFIG_SYS_MAXDATA_SIZE (4096)
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/* SPIF Registers offsets from peripheral base address */
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#define SPIF_VER_REG (0x00) /* version number register */
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#define SPIF_GC_REG (0x04) /* global control register */
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#define SPIF_GCA_REG (0x08) /* global additional control register */
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#define SPIF_TC_REG (0x0C) /* timing control register */
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#define SPIF_TDS_REG (0x10) /* timing delay state register */
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#define SPIF_INT_EN_REG (0x14) /* interrupt enable register */
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#define SPIF_INT_STA_REG (0x18) /* interrupt status register */
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#define SPIF_CSD_REG (0x1C) /* chipselect delay register */
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#define SPIF_PHC_REG (0x20) /* trans phase configure register */
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#define SPIF_TCF_REG (0x24) /* trans configure1 register */
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#define SPIF_TCS_REG (0x28) /* trans configure2 register */
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#define SPIF_TNM_REG (0x2C) /* trans number register */
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#define SPIF_PS_REG (0x30) /* prefetch state register */
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#define SPIF_PSA_REG (0x34) /* prefetch start address register */
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#define SPIF_PEA_REG (0x38) /* prefetch end address register */
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#define SPIF_PMA_REG (0x3C) /* prefetch map address register */
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#define SPIF_DMA_CTL_REG (0x40) /* DMA control register */
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#define SPIF_DSC_REG (0x44) /* DMA descriptor start address register */
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#define SPIF_DFT_REG (0x48) /* DQS FIFO trigger level register */
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#define SPIF_CFT_REG (0x4C) /* CDC FIFO trigger level register */
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#define SPIF_CFS_REG (0x50) /* CDC FIFO status register */
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#define SPIF_BAT_REG (0x54) /* Bit-Aligned tansfer configure register */
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#define SPIF_BAC_REG (0x58) /* Bit-Aligned clock configuration register */
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#define SPIF_TB_REG (0x5C) /* TX Bit register */
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#define SPIF_RB_REG (0x60) /* RX Bit register */
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#define SPIF_RXDATA_REG (0x200) /* prefetch RX data register */
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/* SPIF global control register bit fields & masks,default value:0x0000_0100 */
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#define SPIF_GC_CFG_MODE (0x1 << 0)
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#define SPIF_GC_DMA_MODE (1)
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#define SPIF_GC_CPU_MODE (0)
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#define SPIF_GC_ADDR_MAP_MODE (0x1 << 1)
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#define SPIF_GC_NMODE_EN (0x1 << 2)
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#define SPIF_GC_PMODE_EN (0x1 << 3)
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#define SPIF_GC_CPHA (0x1 << 4)
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#define SPIF_GC_CPOL (0x1 << 5)
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#define SPIF_GC_SS_MASK (0x3 << 6) /* SPIF chip select:00-SPI_SS0;01-SPI_SS1;10-SPI_SS2;11-SPI_SS3*/
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#define SPIF_GC_CS_POL (0x1 << 8)
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#define SPIF_GC_DUMMY_BIT_POL (0x1 << 9)
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#define SPIF_GC_DQS_RX_EN (0x1 << 10)
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#define SPIF_GC_HOLD_POL (0x1 << 12)
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#define SPIF_GC_HOLD_EN (0x1 << 13)
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#define SPIF_GC_WP_POL (0x1 << 14)
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#define SPIF_GC_WP_EN (0x1 << 15)
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#define SPIF_GC_DTR_EN (0x1 << 16)
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#define SPIF_GC_RX_CFG_FBS (0x1 << 17)
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#define SPIF_GC_TX_CFG_FBS (0x1 << 18)
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#define SPIF_GC_SS_BIT_POS (6)
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#define SPIF_SCKT_DELAY_MODE (1U << 21)
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#define SPIF_DIGITAL_ANALOG_EN (1U << 20)
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#define SPIF_DIGITAL_DELAY (16)
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#define SPIF_DIGITAL_DELAY_MASK (7U << 16)
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#define SPIF_ANALOG_DL_SW_RX_EN (1U << 6)
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#define SPIF_ANALOG_DELAY (0)
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#define SPIF_ANALOG_DELAY_MASK (0x3F << 0)
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/*0x08*/
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#define SPIF_CDC_RF_RST (0x1 << 0)
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#define SPIF_CDC_WF_RST (0x1 << 1)
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#define SPIF_DQS_RF_SRST (0x1 << 2)
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#define SPIF_RESET (0x1 << 3)
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/*0x14*/
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#define SPIF_RF_RDY_INT_EN (0x1 << 0) /* read fifo is ready */
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#define SPIF_RF_ENPTY_INT_EN (0x1 << 1)
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#define SPIF_RF_FULL_INT_EN (0x1 << 2)
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#define SPIF_WF_RDY_INT_EN (0x1 << 4) /* write fifo is ready */
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#define SPIF_WF_ENPTY_INT_EN (0x1 << 5)
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#define SPIF_WF_FULL_INT_EN (0x1 << 6)
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#define SPIF_RF_OVF_INT_EN (0x1 << 8)
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#define SPIF_RF_UDF_INT_EN (0x1 << 9)
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#define SPIF_WF_OVF_INT_EN (0x1 << 10)
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#define SPIF_WF_UDF_INT_EN (0x1 << 11)
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#define SPIF_DMA_TRANS_DONE_EN (0x1 << 24)
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#define SPIF_PREFETCH_READ_EN (0x1 << 25)
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#define SPIF_INT_STA_READY_EN (SPIF_RF_RDY_INT_EN | SPIF_WF_RDY_INT_EN)
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#define SPIF_INT_STA_TC_EN (SPIF_DMA_TRANS_DONE_EN | SPIF_PREFETCH_READ_EN)
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#define SPIF_INT_STA_ERR_EN (SPIF_RF_OVF_INT_EN | SPIF_RF_UDF_INT_EN | SPIF_WF_OVF_INT_EN)
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/* 0x18 */
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#define SPIF_RF_RDY BIT(0)
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#define SPIF_RF_EMPTY BIT(1)
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#define SPIF_RF_FULL BIT(2)
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#define SPIF_WF_RDY BIT(4)
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#define SPIF_WF_EMPTY BIT(5)
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#define SPIF_WF_FULL BIT(6)
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#define SPIF_RF_OVF BIT(8)
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#define SPIF_RF_UDF BIT(9)
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#define SPIF_WF_OVF BIT(10)
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#define SPIF_WF_UDF BIT(11)
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#define SPIF_DMA_TRANS_DONE BIT(24)
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#define SPIF_PREFETCH_READ_BACK BIT(25)
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#define SPIF_INT_STA_READY (SPIF_RF_READY | SPIF_WF_READY)
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#define SPIF_INT_STA_TC (SPIF_DMA_TRANS_DONE | SPIF_PREFETCH_READ_BACK)
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#define SPIF_INT_STA_ERR (SPIF_RF_OVF | SPIF_RF_UDF | SPIF_WF_OVF)
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/* 0x1c */
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#define SPIF_CSSOT (0) /* chip select start of transfer */
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#define SPIF_CSEOT (8) /* chip select end of transfer */
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#define SPIF_CSDA (16) /* chip select de-assert */
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#define SPIF_CSSOT_DEFAULT (0x5)
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#define SPIF_CSEOT_DEFAULT (0x6)
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#define SPIF_CSDA_DEFAULT (0x6)
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/* 0x40 */
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#define SPIF_CFG_DMA_START BIT(0)
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#define SPIF_DMA_DESCRIPTOR_LEN (4)
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/* 0x48 */
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#define SPIF_DQS_EMPTY_TRIG_LEVEL (0)
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#define SPIF_DQS_FULL_TRIG_LEVEL (8)
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/* 0x4c */
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#define SPIF_RF_EMPTY_TRIG_LEVEL (0)
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#define SPIF_RF_FULL_TRIG_LEVEL (8)
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#define SPIF_WF_EMPTY_TRIG_LEVEL (16)
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#define SPIF_WF_FULL_TRIG_LEVEL (24)
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/* SPIF Timing Configure Register Bit Fields & Masks,default value:0x0000_0000 */
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#define SPIF_SAMP_DL_VAL_TX_POS (8)
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#define SPIF_SAMP_DL_VAL_RX_POS (0)
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#define SPIF_SCKR_DL_MODE_SEL (0x1 << 20)
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#define SPIF_CLK_SCKOUT_SRC_SEL (0x1 << 26)
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/* SPIF Interrupt status Register Bit Fields & Masks,default value:0x0000_0000 */
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#define DMA_TRANS_DONE_INT (0x1 << 24)
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/* SPIF Trans Phase Configure Register Bit Fields & Masks,default value:0x0000_0000 */
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#define SPIF_RX_TRANS_EN (0x1 << 8)
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#define SPIF_TX_TRANS_EN (0x1 << 12)
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#define SPIF_DUMMY_TRANS_EN (0x1 << 16)
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#define SPIF_MODE_TRANS_EN (0x1 << 20)
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#define SPIF_ADDR_TRANS_EN (0x1 << 24)
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#define SPIF_CMD_TRANS_EN (0x1 << 28)
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/* SPIF Trans Configure2 Register Bit Fields & Masks,default value:0x0000_0000 */
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#define SPIF_DATA_TRANS_POS (0)
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#define SPIF_MODE_TRANS_POS (4)
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#define SPIF_ADDR_TRANS_POS (8)
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#define SPIF_CMD_TRANS_POS (12)
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#define SPIF_MODE_OPCODE_POS (16)
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#define SPIF_CMD_OPCODE_POS (24)
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/* SPIF Trans Number Register Bit Fields & Masks,default value:0x0000_0000 */
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#define SPIF_ADDR_SIZE_MODE (0x1 << 24)
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#define SPIF_DUMMY_NUM_POS (16)
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#define SPIF_DATA_NUM_POS (0)
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/* SPIF DMA Control Register Bit Fields & Masks,default value:0x0000_0000 */
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#define CFG_DMA_START (1 << 0)
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#define DMA_DESCRIPTOR_LEN (32 << 4)
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/* DMA descriptor0 Bit Fields & Masks */
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#define HBURST_SINGLE_TYPE (0x0 << 4)
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#define HBURST_INCR4_TYPE (0x3 << 4)
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#define HBURST_INCR8_TYPE (0x5 << 4)
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#define HBURST_INCR16_TYPE (0x7 << 4)
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#define HBURST_TYPE (0x7 << 4)
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#define DMA_RW_PROCESS (0x1 << 1) /* 0:Read 1:Write */
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#define DMA_FINISH_FLASG (0x1 << 0) /* The Last One Descriptor */
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/* DMA descriptor1 Bit Fields & Masks */
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#define DMA_BLK_LEN_8B (0x0 << 16)
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#define DMA_BLK_LEN_16B (0x1 << 16)
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#define DMA_BLK_LEN_32B (0x2 << 16)
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#define DMA_BLK_LEN_64B (0x3 << 16)
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#define DMA_BLK_LEN (0xffff << 16)
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#define DMA_DATA_LEN_POS (0)
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#define DMA_DATA_LEN (0xffff)
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/* DMA descriptor7 Bit Fields & Masks */
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#define SPIF_DES_NORMAL_EN (0x1 << 28)
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#define SPIF_OCTAL_MODE (8)
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#define SPIF_QUAD_MODE (4)
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#define SPIF_DUEL_MODE (2)
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#define SPIF_SINGLE_MODE (1)
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#define SPIF_MIN_TRANS_NUM (8)
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#define NOR_PAGE_SIZE (256)
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#define DESC_PER_DISTRIBUTION_MAX_NUM (16)
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#define SAMP_MODE_DL_DEFAULT (0xaaaaffff)
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struct sunxi_spif_data {
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u32 min_speed_hz;
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u32 max_speed_hz;
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u32 cs_num; /* the total num of spi chip select */
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u32 sample_mode;
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u32 sample_delay;
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};
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/*
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* dma descriptor 0~3 : set the dma config
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* you can set the register 0x20 0x24 0x28 0x2c to set too
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* dma descriptor 4~7 : set the spif controller transfer config
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*/
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struct dma_descriptor {
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u32 hburst_rw_flag;
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u32 block_data_len; /* dma blk len and dma data len */
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u32 data_addr; /* data buff */
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u32 next_des_addr; /* the next dma desc */
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u32 trans_phase; /* trans en, can be instead by 0x20 */
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u32 flash_addr; /* the spi device's addr, can be instead by 0x24 */
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u32 cmd_mode_buswidth; /* opcode and trans type, can be instead by 0x28 */
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u32 addr_dummy_data_count; /* can be instead by 0x2c */
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};
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struct dma_desc_cache {
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struct list_head desc_list;
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struct dma_descriptor *dma_desc;
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dma_addr_t desc_phys; /* the request dma descriptor phys addr */
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};
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#define sunxi_spif_transfer_t spi_mem_op
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struct sunxi_spif {
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struct platform_device *pdev;
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struct spi_master *master;
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struct spi_device *spi;
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struct completion done; /* wakup another spi transfer */
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struct task_struct *task;
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struct sunxi_spif_data *data;
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spinlock_t lock;
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void __iomem *base_addr;
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struct dma_pool *pool;
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struct dma_descriptor *dma_desc[DESC_PER_DISTRIBUTION_MAX_NUM];
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dma_addr_t desc_phys[DESC_PER_DISTRIBUTION_MAX_NUM]; /* the request dma descriptor phys addr */
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struct list_head desc_cache_list;
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u32 spif_register[24];
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int result; /* the spi trans result */
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char dev_name[48];
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/* @cache buf (aw1886)
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* The amount of data to be transmitted at a time is greater than 8,
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* which is used for data cache in the read state
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*/
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char *cache_buf;
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dma_addr_t cache_phys; /* the request dma descriptor phys addr */
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char *data_buf;
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dma_addr_t data_phys; /* the request dma descriptor phys addr */
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char *temporary_data_cache;
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dma_addr_t temporary_data_phys; /* the request dma descriptor phys addr */
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/* dts data */
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struct regulator *regulator;
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struct pinctrl *pctrl;
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struct clk *pclk; /* PLL clock */
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struct clk *mclk; /* spi module clock */
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struct reset_control *rstc;
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u32 base_addr_phy;
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u32 irq;
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u32 working_mode;
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#define PREFETCH_READ_MODE 0x1
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#define DQS 0x2
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char regulator_id[16];
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};
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extern void sunxi_spif_update_sample_delay_para(struct mtd_info *mtd, struct spi_device *spi);
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extern int sunxi_spif_controller_ops(struct spi_device *spi, struct spi_transfer *t);
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#endif
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