591 lines
15 KiB
Plaintext
591 lines
15 KiB
Plaintext
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#include <dt-bindings/clock/sunxi-clk.h>
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/{
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clocks {
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compatible = "allwinner,clk-init";
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device_type = "clocks";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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reg = <0x0 0x03001000 0x0 0x1000>, /*cpux space*/
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<0x0 0x07010000 0x0 0x400>, /*cpus space*/
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<0x0 0x07000000 0x0 0x200>;
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/*
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* sdm info:
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* for example:
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pll_npux4 {
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sdm-enable = <1>;
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sdm-factor = <4>;
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freq-mod = <TR_N>;
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sdm-freq = <FREQ_32>;
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};
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*/
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/* list all clk which can set sdm */
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sdm_info: sdm_info {
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};
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/* register fixed rate clock */
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clk_losc: losc {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "losc";
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};
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clk_iosc: iosc {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-clock";
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clock-frequency = <16000000>;
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clock-output-names = "iosc";
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};
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clk_hosc: hosc {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "hosc";
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};
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clk_pll_periph0div25m:pll_periph0div25m {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-clock";
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clock-frequency = <25000000>;
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clock-output-names = "pll_periph0div25m";
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};
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clk_osc48m: osc48m {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-clock";
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clock-frequency = <48000000>;
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clock-output-names = "osc48m";
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};
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/* register allwinner,pll-clock */
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clk_pll_cpu: pll_cpu {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_cpu";
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};
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clk_pll_ddr0: pll_ddr0 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_ddr0";
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};
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clk_pll_periph0: pll_periph0 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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assigned-clock-rates = <600000000>;
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lock-mode = "new";
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clock-output-names = "pll_periph0";
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};
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clk_pll_uni: pll_uni {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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assigned-clock-rates = <600000000>;
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lock-mode = "new";
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clock-output-names = "pll_uni";
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};
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clk_pll_video0: pll_video0 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_video0";
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};
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clk_pll_audio: pll_audio {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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assigned-clocks = <&clk_pll_audio>;
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assigned-clock-rates = <22579200>;
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lock-mode = "new";
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clock-output-names = "pll_audio";
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};
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clk_pll_csi: pll_csi {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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assigned-clocks = <&clk_pll_csi>;
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assigned-clock-rates = <540000000>;
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lock-mode = "new";
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clock-output-names = "pll_csi";
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};
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/* register fixed factor clock */
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clk_pll_periph0x2: pll_periph0x2 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_periph0>;
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clock-mult = <2>;
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clock-div = <1>;
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clock-output-names = "pll_periph0x2";
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};
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clk_periph32k: periph32k {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_periph0>;
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clock-mult = <2>;
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clock-div = <36621>;
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clock-output-names = "periph32k";
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};
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clk_pll_unix2: pll_unix2 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_uni>;
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clock-mult = <2>;
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clock-div = <1>;
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clock-output-names = "pll_unix2";
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};
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clk_pll_audiox4: pll_audiox4 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_audio>;
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clock-mult = <4>;
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clock-div = <1>;
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clock-output-names = "pll_audiox4";
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};
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clk_pll_audiox2: pll_audiox2 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_audio>;
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clock-mult = <2>;
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clock-div = <1>;
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clock-output-names = "pll_audiox2";
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};
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clk_pll_video0x4: pll_video0x4 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_video0>;
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clock-mult = <4>;
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clock-div = <1>;
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clock-output-names = "pll_video0x4";
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};
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clk_mbus: mbus {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_ddr0>;
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clock-mult = <1>;
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clock-div = <4>;
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clock-output-names = "mbus";
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};
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clk_hoscd2: hoscd2 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_hosc>;
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clock-mult = <1>;
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clock-div = <2>;
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clock-output-names = "hoscd2";
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};
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clk_osc48md4: osc48md4 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_osc48m>;
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clock-mult = <1>;
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clock-div = <4>;
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clock-output-names = "osc48md4";
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};
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/* register allwinner,periph-clock */
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clk_cpu: cpu {
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#clock-cells = <0>;
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compatible = "allwinner,cpu-clock";
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clock-output-names = "cpu";
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};
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clk_axi: axi {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "axi";
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};
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clk_cpuapb: cpuapb {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "cpuapb";
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};
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clk_psi: psi {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "psi";
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};
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clk_ahb1: ahb1 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "ahb1";
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};
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clk_ahb2: ahb2 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "ahb2";
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};
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clk_ahb3: ahb3 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "ahb3";
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};
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clk_apb1: apb1 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "apb1";
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};
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clk_apb2: apb2 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "apb2";
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};
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clk_de: de {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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assigned-clocks = <&clk_de>;
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/*assigned-clock-parents = <&clk_pll_de>;*/
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assigned-clock-rates = <300000000>;
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clock-output-names = "de";
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};
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clk_g2d: g2d {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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assigned-clock-rates = <300000000>;
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assigned-clocks = <&clk_g2d>;
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clock-output-names = "g2d";
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};
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clk_ve: ve {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "ve";
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};
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clk_ce: ce {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "ce";
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};
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clk_eise: eise {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "eise";
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};
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clk_nna: nna {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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assigned-clocks = <&clk_nna>;
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assigned-clock-parents = <&clk_pll_periph0x2>;
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clock-output-names = "nna";
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};
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clk_nna_rst: nna_rts {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "nna_rst";
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};
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clk_isp: isp {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "isp";
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};
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clk_dma: dma {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "dma";
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};
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clk_hstimer: hstimer {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "hstimer";
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};
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clk_avs: avs {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "avs";
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};
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clk_dbgsys: dbgsys {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "dbgsys";
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};
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clk_pwm: pwm {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "pwm";
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};
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clk_iommu: iommu {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "iommu";
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};
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clk_sdram: sdram {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdram";
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};
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clk_sdmmc0_mod: sdmmc0_mod {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdmmc0_mod";
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};
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clk_sdmmc0_bus: sdmmc0_bus {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdmmc0_bus";
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};
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clk_sdmmc0_rst: sdmmc0_rst {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdmmc0_rst";
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};
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clk_sdmmc1_mod: sdmmc1_mod {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdmmc1_mod";
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};
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clk_sdmmc1_bus: sdmmc1_bus {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdmmc1_bus";
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};
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clk_sdmmc1_rst: sdmmc1_rst {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdmmc1_rst";
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};
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clk_sdmmc2_mod: sdmmc2_mod {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdmmc2_mod";
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};
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clk_sdmmc2_bus: sdmmc2_bus {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdmmc2_bus";
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};
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clk_sdmmc2_rst: sdmmc2_rst {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdmmc2_rst";
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};
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clk_uart0: uart0 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "uart0";
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};
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clk_uart1: uart1 {
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||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "uart1";
|
||
|
|
};
|
||
|
|
clk_uart2: uart2 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "uart2";
|
||
|
|
};
|
||
|
|
clk_uart3: uart3 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "uart3";
|
||
|
|
};
|
||
|
|
clk_twi0: twi0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "twi0";
|
||
|
|
};
|
||
|
|
clk_twi1: twi1 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "twi1";
|
||
|
|
};
|
||
|
|
clk_twi2: twi2 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "twi2";
|
||
|
|
};
|
||
|
|
clk_twi3: twi3 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "twi3";
|
||
|
|
};
|
||
|
|
clk_spi0: spi0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "spi0";
|
||
|
|
};
|
||
|
|
clk_spi1: spi1 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "spi1";
|
||
|
|
};
|
||
|
|
clk_spi2: spi2 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "spi2";
|
||
|
|
};
|
||
|
|
clk_ephy_25m: ephy_25m {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "ephy_25m";
|
||
|
|
};
|
||
|
|
clk_gmac: gmac {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "gmac";
|
||
|
|
};
|
||
|
|
clk_gpadc: gpadc {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "gpadc";
|
||
|
|
};
|
||
|
|
clk_ths: ths {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "ths";
|
||
|
|
};
|
||
|
|
clk_i2s0: i2s0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "i2s0";
|
||
|
|
};
|
||
|
|
clk_i2s1: i2s1 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "i2s1";
|
||
|
|
};
|
||
|
|
clk_codec_1x: codec_1x {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "codec_1x";
|
||
|
|
};
|
||
|
|
clk_codec_4x: codec_4x {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "codec_4x";
|
||
|
|
};
|
||
|
|
clk_usbphy0: usbphy0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbphy0";
|
||
|
|
};
|
||
|
|
clk_usbohci0: usbohci0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbohci0";
|
||
|
|
};
|
||
|
|
clk_usbohci0_12m: usbohci0_12m {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbohci0_12m";
|
||
|
|
};
|
||
|
|
clk_usbehci0: usbehci0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbehci0";
|
||
|
|
};
|
||
|
|
clk_usbotg: usbotg {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbotg";
|
||
|
|
};
|
||
|
|
clk_mipi_dphy0: mipi_dphy0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "mipi_dphy0";
|
||
|
|
};
|
||
|
|
clk_mipi_host0: mipi_host0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
assigned-clocks = <&clk_mipi_host0>;
|
||
|
|
assigned-clock-parents = <&clk_hosc>;
|
||
|
|
clock-output-names = "mipi_host0";
|
||
|
|
};
|
||
|
|
clk_display_top: display_top {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "display_top";
|
||
|
|
};
|
||
|
|
clk_tcon_lcd: tcon_lcd {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "tcon_lcd";
|
||
|
|
};
|
||
|
|
clk_csi_top: csi_top {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "csi_top";
|
||
|
|
};
|
||
|
|
clk_csi_master0: csi_master0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "csi_master0";
|
||
|
|
};
|
||
|
|
clk_csi_master1: csi_master1 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "csi_master1";
|
||
|
|
};
|
||
|
|
clk_dspo: dspo {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
assigned-clocks = <&clk_dspo>;
|
||
|
|
assigned-clock-parents = <&clk_pll_video0>;
|
||
|
|
clock-output-names = "dspo";
|
||
|
|
};
|
||
|
|
clk_pio: pio {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "pio";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* cpus space clocks from PRCM-SPEC */
|
||
|
|
clk_cpurowc: cpurowc {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-cpus-clock";
|
||
|
|
clock-output-names = "cpurowc";
|
||
|
|
};
|
||
|
|
clk_stwi: stwi {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-cpus-clock";
|
||
|
|
clock-output-names = "stwi";
|
||
|
|
};
|
||
|
|
clk_losc_out: losc_out {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-cpus-clock";
|
||
|
|
clock-output-names = "losc_out";
|
||
|
|
};
|
||
|
|
/* clk below are read only , just to keep a clock tree */
|
||
|
|
clk_cpurcpus_pll: cpurcpus_pll {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-cpus-clock";
|
||
|
|
clock-output-names = "cpurcpus_pll";
|
||
|
|
};
|
||
|
|
clk_cpurcpus: cpurcpus {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-cpus-clock";
|
||
|
|
clock-output-names = "cpurcpus";
|
||
|
|
};
|
||
|
|
clk_cpurahbs: cpurahbs {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-cpus-clock";
|
||
|
|
clock-output-names = "cpurahbs";
|
||
|
|
};
|
||
|
|
clk_cpurapbs1: cpurapbs1 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-cpus-clock";
|
||
|
|
clock-output-names = "cpurapbs1";
|
||
|
|
};
|
||
|
|
clk_cpurapbs2_pll: cpurapbs2_pll {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-cpus-clock";
|
||
|
|
clock-output-names = "cpurapbs2_pll";
|
||
|
|
};
|
||
|
|
clk_cpurapbs2: cpurapbs2 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-cpus-clock";
|
||
|
|
clock-output-names = "cpurapbs2";
|
||
|
|
};
|
||
|
|
clk_cpurpio: cpurpio {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-cpus-clock";
|
||
|
|
clock-output-names = "cpurpio";
|
||
|
|
};
|
||
|
|
clk_spwm: spwm {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-cpus-clock";
|
||
|
|
clock-output-names = "spwm";
|
||
|
|
};
|
||
|
|
clk_dcxo_out: dcxo_out {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-cpus-clock";
|
||
|
|
clock-output-names = "dcxo_out";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|