764 lines
19 KiB
Plaintext
764 lines
19 KiB
Plaintext
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#include <dt-bindings/clock/sunxi-clk.h>
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/{
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clocks {
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compatible = "allwinner,clk-init";
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device_type = "clocks";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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reg = <0x0 0x02001000 0x0 0x1000>, /* cpux-ccu space */
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<0x0 0x07010000 0x0 0x400>, /* cpus-ccu space */
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<0x0 0x07090000 0x0 0x400>; /* rtc-ccu space */
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/*
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* sdm info:
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* for example:
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* pll_npux4 {
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* sdm-enable = <1>;
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* sdm-factor = <4>; // 0.4%
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* freq-mod = <TR_N>;
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* sdm-freq = <FREQ_32>;
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* };
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*/
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/* list all clk which can set sdm */
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/*
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sdm_info: sdm_info {
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pll_periph0x2 {
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sdm-enable = <1>;
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};
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pll_periph0800m {
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sdm-enable = <3>;
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sdm-factor = <8>;
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};
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pll_periph0480m {
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sdm-enable = <1>;
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sdm-factor = <8>;
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};
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pll_video0x4 {
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sdm-enable = <1>;
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sdm-factor = <1>;
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};
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pll_csix4 {
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sdm-enable = <1>;
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sdm-factor = <1>;
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};
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pll_audio_div2 {
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sdm-enable = <1>;
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sdm-factor = <1>;
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};
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pll_audio_div5 {
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sdm-enable = <1>;
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sdm-factor = <1>;
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};
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pll_npux4 {
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sdm-enable = <1>;
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sdm-factor = <1>;
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};
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};
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*/
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/* register fixed rate clock*/
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clk_ext_losc: ext_losc {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "ext_losc";
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};
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clk_iosc: iosc {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-clock";
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clock-frequency = <16000000>;
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clock-output-names = "iosc";
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};
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clk_hosc: hosc {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "hosc";
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};
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clk_hoscdiv32k: hoscdiv32k {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "hoscdiv32k";
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};
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clk_osc48m: osc48m {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-clock";
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clock-frequency = <48000000>;
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clock-output-names = "osc48m";
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};
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/* register allwinner,pll-clock */
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clk_pll_cpu: pll_cpu {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_cpu";
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};
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clk_pll_ddr0: pll_ddr0 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_ddr0";
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};
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clk_pll_periph0x2: pll_periph0x2 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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assigned-clock-rates = <1200000000>;
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lock-mode = "new";
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clock-output-names = "pll_periph0x2";
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};
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clk_pll_periph0800m: pll_periph0800m {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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assigned-clock-rates = <800000000>;
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lock-mode = "new";
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clock-output-names = "pll_periph0800m";
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};
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clk_pll_periph0480m: pll_periph0480m {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_periph0480m";
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};
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clk_pll_video0x4: pll_video0x4 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_video0x4";
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};
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clk_pll_csix4: pll_csix4 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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assigned-clock-rates = <1188000000>;
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lock-mode = "new";
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clock-output-names = "pll_csix4";
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};
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clk_pll_audio_div2: pll_audio_div2 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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assigned-clock-rates = <1536000000>;
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lock-mode = "new";
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clock-output-names = "pll_audio_div2";
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};
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clk_pll_audio_div5: pll_audio_div5 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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assigned-clock-rates = <614400000>;
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lock-mode = "new";
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clock-output-names = "pll_audio_div5";
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};
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clk_pll_npux4: pll_npux4 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_npux4";
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assigned-clock-rates = <1392000000>;
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assigned-clocks = <&clk_pll_npux4>;
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};
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/* register fixed factor clock */
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clk_iosc32k: iosc32k {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_iosc>;
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clock-mult = <1>;
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clock-div = <500>;
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clock-output-names = "iosc32k";
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};
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clk_pll_periph0600m: pll_periph0600m {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_periph0x2>;
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clock-mult = <1>;
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clock-div = <2>;
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clock-output-names = "pll_periph0600m";
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};
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clk_pll_periph0400m: pll_periph0400m {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_periph0x2>;
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clock-mult = <1>;
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clock-div = <3>;
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clock-output-names = "pll_periph0400m";
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};
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clk_pll_periph0300m: pll_periph0300m {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_periph0600m>;
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clock-mult = <1>;
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clock-div = <2>;
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clock-output-names = "pll_periph0300m";
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};
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clk_pll_periph0200m: pll_periph0200m {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_periph0400m>;
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clock-mult = <1>;
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clock-div = <2>;
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clock-output-names = "pll_periph0200m";
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};
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clk_pll_periph0160m: pll_periph0160m {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_periph0480m>;
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clock-mult = <1>;
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clock-div = <3>;
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clock-output-names = "pll_periph0160m";
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};
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clk_pll_periph0150m: pll_periph0150m {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_periph0300m>;
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clock-mult = <1>;
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clock-div = <2>;
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clock-output-names = "pll_periph0150m";
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};
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clk_pll_periph0150m_div6: pll_periph0150m_div6 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_periph0150m>;
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clock-mult = <1>;
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clock-div = <6>;
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clock-output-names = "pll_periph0150m_div6";
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};
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clk_pll_periph0160m_div10: pll_periph0160m_div10 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_periph0160m>;
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clock-mult = <1>;
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clock-div = <10>;
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clock-output-names = "pll_periph0160m_div10";
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};
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clk_pll_video0x2: pll_video0x2 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_video0x4>;
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clock-mult = <1>;
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clock-div = <2>;
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clock-output-names = "pll_video0x2";
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};
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clk_pll_video0: pll_video0 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_video0x4>;
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clock-mult = <1>;
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clock-div = <4>;
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clock-output-names = "pll_video0";
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};
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clk_pll_npux2: pll_npux2 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_npux4>;
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clock-mult = <1>;
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clock-div = <2>;
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clock-output-names = "pll_npux2";
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};
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clk_pll_npu: pll_npu {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_npux4>;
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clock-mult = <1>;
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clock-div = <4>;
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clock-output-names = "pll_npu";
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};
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clk_hoscd2: hoscd2 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_hosc>;
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clock-mult = <1>;
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clock-div = <2>;
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clock-output-names = "hoscd2";
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};
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clk_osc48md4: osc48md4 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_osc48m>;
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clock-mult = <1>;
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clock-div = <4>;
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clock-output-names = "osc48md4";
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};
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clk_sdramd4: sdramd4 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_sdram>;
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clock-mult = <1>;
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clock-div = <4>;
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clock-output-names = "sdramd4";
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};
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/* register allwinner,periph-clock */
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clk_cpu: cpu {
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#clock-cells = <0>;
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compatible = "allwinner,cpu-clock";
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clock-output-names = "cpu";
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};
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clk_axi: axi {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "axi";
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};
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clk_cpuapb: cpuapb {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "cpuapb";
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};
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clk_ahb: ahb {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "ahb";
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};
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clk_apb0: apb0 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "apb0";
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};
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clk_apb1: apb1 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "apb1";
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};
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clk_de: de {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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assigned-clock-rates = <300000000>;
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clock-output-names = "de";
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assigned-clock-parents = <&clk_pll_periph0300m>;
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assigned-clocks = <&clk_de>;
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};
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clk_g2d: g2d {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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assigned-clock-rates = <300000000>;
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clock-output-names = "g2d";
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assigned-clock-parents = <&clk_pll_periph0300m>;
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assigned-clocks = <&clk_g2d>;
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};
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clk_ce: ce {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "ce";
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};
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clk_ve: ve {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "ve";
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};
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clk_npu: npu {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "npu";
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assigned-clock-parents = <&clk_pll_npux4>;
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assigned-clock-rates = <348000000>;
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assigned-clocks = <&clk_npu>;
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};
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clk_dma: dma {
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#clock-cells = <0>;
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|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "dma";
|
||
|
|
};
|
||
|
|
clk_msgbox0: msgbox0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "msgbox0";
|
||
|
|
};
|
||
|
|
clk_msgbox1: msgbox1 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "msgbox1";
|
||
|
|
};
|
||
|
|
clk_spinlock: spinlock {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "spinlock";
|
||
|
|
};
|
||
|
|
clk_hstimer: hstimer {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "hstimer";
|
||
|
|
};
|
||
|
|
clk_avs: avs {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "avs";
|
||
|
|
};
|
||
|
|
clk_dbgsys: dbgsys {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "dbgsys";
|
||
|
|
};
|
||
|
|
clk_pwm: pwm {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "pwm";
|
||
|
|
};
|
||
|
|
clk_iommu: iommu {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "iommu";
|
||
|
|
};
|
||
|
|
|
||
|
|
clk_sdram: sdram {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "sdram";
|
||
|
|
};
|
||
|
|
clk_sdmmc0_mod: sdmmc0_mod {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "sdmmc0_mod";
|
||
|
|
};
|
||
|
|
clk_sdmmc0_bus: sdmmc0_bus {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "sdmmc0_bus";
|
||
|
|
};
|
||
|
|
clk_sdmmc0_rst: sdmmc0_rst {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "sdmmc0_rst";
|
||
|
|
};
|
||
|
|
clk_sdmmc1_mod: sdmmc1_mod {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "sdmmc1_mod";
|
||
|
|
};
|
||
|
|
clk_sdmmc1_bus: sdmmc1_bus {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "sdmmc1_bus";
|
||
|
|
};
|
||
|
|
clk_sdmmc1_rst: sdmmc1_rst {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "sdmmc1_rst";
|
||
|
|
};
|
||
|
|
clk_sdmmc2_mod: sdmmc2_mod {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "sdmmc2_mod";
|
||
|
|
};
|
||
|
|
clk_sdmmc2_bus: sdmmc2_bus {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "sdmmc2_bus";
|
||
|
|
};
|
||
|
|
clk_sdmmc2_rst: sdmmc2_rst {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "sdmmc2_rst";
|
||
|
|
};
|
||
|
|
|
||
|
|
clk_uart0: uart0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "uart0";
|
||
|
|
};
|
||
|
|
clk_uart1: uart1 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "uart1";
|
||
|
|
};
|
||
|
|
clk_uart2: uart2 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "uart2";
|
||
|
|
};
|
||
|
|
clk_uart3: uart3 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "uart3";
|
||
|
|
};
|
||
|
|
clk_twi0: twi0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "twi0";
|
||
|
|
};
|
||
|
|
clk_twi1: twi1 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "twi1";
|
||
|
|
};
|
||
|
|
clk_twi2: twi2 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "twi2";
|
||
|
|
};
|
||
|
|
clk_twi3: twi3 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "twi3";
|
||
|
|
};
|
||
|
|
clk_twi4: twi4 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "twi4";
|
||
|
|
};
|
||
|
|
clk_spi0: spi0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "spi0";
|
||
|
|
};
|
||
|
|
clk_spi1: spi1 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "spi1";
|
||
|
|
};
|
||
|
|
clk_spi2: spi2 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "spi2";
|
||
|
|
};
|
||
|
|
clk_spi3: spi3 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "spi3";
|
||
|
|
};
|
||
|
|
clk_spif: spif {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "spif";
|
||
|
|
};
|
||
|
|
clk_gmac_25m: gmac_25m {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "gmac_25m";
|
||
|
|
};
|
||
|
|
clk_gmac: gmac {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "gmac";
|
||
|
|
};
|
||
|
|
clk_gpadc: gpadc {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
assigned-clock-rates = <24000000>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "gpadc";
|
||
|
|
assigned-clocks = <&clk_gpadc>;
|
||
|
|
};
|
||
|
|
clk_ths: ths {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "ths";
|
||
|
|
};
|
||
|
|
clk_pll_audiox4: pll_audiox4 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "pll_audiox4";
|
||
|
|
};
|
||
|
|
clk_pll_audio: pll_audio {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "pll_audio";
|
||
|
|
};
|
||
|
|
clk_i2s0: i2s0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "i2s0";
|
||
|
|
};
|
||
|
|
clk_i2s1: i2s1 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "i2s1";
|
||
|
|
};
|
||
|
|
clk_dmic: dmic {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "dmic";
|
||
|
|
};
|
||
|
|
clk_codec_dac: codec_dac {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "codec_dac";
|
||
|
|
};
|
||
|
|
clk_codec_adc: codec_adc {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "codec_adc";
|
||
|
|
};
|
||
|
|
clk_usbphy0: usbphy0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbphy0";
|
||
|
|
};
|
||
|
|
clk_usbohci0: usbohci0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbohci0";
|
||
|
|
};
|
||
|
|
clk_usbohci0_12m: usbohci0_12m {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbohci0_12m";
|
||
|
|
};
|
||
|
|
clk_usbehci0: usbehci0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbehci0";
|
||
|
|
};
|
||
|
|
clk_usbotg: usbotg {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbotg";
|
||
|
|
};
|
||
|
|
clk_dpss_top: dpss_top {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "dpss_top";
|
||
|
|
};
|
||
|
|
clk_mipi_dsi: mipi_dsi {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
assigned-clocks = <&clk_mipi_dsi>;
|
||
|
|
assigned-clock-parents = <&clk_pll_periph0150m>;
|
||
|
|
// assigned-clock-rates = <150000000>;
|
||
|
|
clock-output-names = "mipi_dsi";
|
||
|
|
};
|
||
|
|
clk_tcon_lcd: tcon_lcd {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "tcon_lcd";
|
||
|
|
};
|
||
|
|
clk_csi_top: csi_top {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "csi_top";
|
||
|
|
};
|
||
|
|
clk_csi_master0: csi_master0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "csi_master0";
|
||
|
|
};
|
||
|
|
clk_csi_master1: csi_master1 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "csi_master1";
|
||
|
|
};
|
||
|
|
clk_csi_master2: csi_master2 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "csi_master2";
|
||
|
|
};
|
||
|
|
clk_isp: isp {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "isp";
|
||
|
|
};
|
||
|
|
clk_wiegand: wiegand {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "wiegand";
|
||
|
|
};
|
||
|
|
clk_e907_gate: e907_gate{
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "e907_gate";
|
||
|
|
};
|
||
|
|
clk_e907: e907{
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "e907";
|
||
|
|
};
|
||
|
|
clk_e907_axi: e907_axi{
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "e907_axi";
|
||
|
|
};
|
||
|
|
clk_fanout_25m: fanout_25m{
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "fanout_25m";
|
||
|
|
};
|
||
|
|
clk_fanout_16m: fanout_16m{
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "fanout_16m";
|
||
|
|
};
|
||
|
|
clk_fanout_12m: fanout_12m{
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "fanout_12m";
|
||
|
|
};
|
||
|
|
clk_fanout_24m: fanout_24m{
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "fanout_24m";
|
||
|
|
};
|
||
|
|
clk_fanout_27m: fanout_27m{
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "fanout_27m";
|
||
|
|
};
|
||
|
|
clk_fanout_pclk: fanout_pclk{
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "fanout_pclk";
|
||
|
|
};
|
||
|
|
clk_fanout0: fanout0{
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "fanout0";
|
||
|
|
};
|
||
|
|
clk_fanout1: fanout1{
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "fanout1";
|
||
|
|
};
|
||
|
|
clk_fanout2: fanout2{
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "fanout2";
|
||
|
|
};
|
||
|
|
/*cpus space clocks from PRCM-SPEC*/
|
||
|
|
clk_cpurahbs: cpurahbs {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-cpus-clock";
|
||
|
|
clock-output-names = "cpurahbs";
|
||
|
|
};
|
||
|
|
clk_cpurapbs0: cpurapbs0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-cpus-clock";
|
||
|
|
clock-output-names = "cpurapbs0";
|
||
|
|
};
|
||
|
|
clk_cpurtwd: cpurtwd {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-cpus-clock";
|
||
|
|
clock-output-names = "cpurtwd";
|
||
|
|
};
|
||
|
|
clk_cpurppu: cpurppu {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-cpus-clock";
|
||
|
|
clock-output-names = "cpurppu";
|
||
|
|
};
|
||
|
|
clk_cpurrtc: cpurrtc {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-cpus-clock";
|
||
|
|
clock-output-names = "cpurrtc";
|
||
|
|
};
|
||
|
|
clk_cpurcpus: cpurcpus {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-cpus-clock";
|
||
|
|
clock-output-names = "cpurcpus";
|
||
|
|
};
|
||
|
|
/* rtc clk */
|
||
|
|
clk_losc: losc {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-rtc-clock";
|
||
|
|
clock-output-names = "losc";
|
||
|
|
};
|
||
|
|
clk_losc_out: losc_out {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-rtc-clock";
|
||
|
|
clock-output-names = "losc_out";
|
||
|
|
};
|
||
|
|
clk_hosc32k: hosc32k {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-rtc-clock";
|
||
|
|
clock-output-names = "hosc32k";
|
||
|
|
};
|
||
|
|
clk_rtc_spi: rtc_spi {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-rtc-clock";
|
||
|
|
clock-output-names = "rtc_spi";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|