455 lines
15 KiB
C
455 lines
15 KiB
C
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/*
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* linux-4.9/drivers/media/platform/sunxi-vin/top_reg.c
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*
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* Copyright (c) 2007-2017 Allwinnertech Co., Ltd.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include "top_reg_i.h"
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#include "top_reg.h"
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#include "utility/vin_io.h"
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/*isp_id isp_input pasrer_id parser_ch*/
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static char isp_input[4][4][4][4] = {
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#if defined(CONFIG_ARCH_SUN50IW3P1) || defined(CONFIG_ARCH_SUN50IW6P1)
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/*isp0 input0~3*/
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/*parser0*/ /*parse1*/ /*parser2*/ /*parser3*/
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{
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{{0, 0, 0, 0}, {1, 2, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
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{{0, 0, 0, 0}, {0, 1, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
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{{0, 0, 0, 0}, {0, 0, 1, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
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{{0, 0, 0, 0}, {0, 0, 0, 1}, {0, 0, 0, 0}, {0, 0, 0, 0} }
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},
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/*isp1 input0~3*/
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{
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{{1, 2, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
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{{0, 0, 0, 0}, {0, 1, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
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{{0, 0, 0, 0}, {0, 0, 1, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
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{{0, 0, 0, 0}, {0, 0, 0, 1}, {0, 0, 0, 0}, {0, 0, 0, 0} }
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},
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#elif defined (CONFIG_ARCH_SUN8IW15P1) || defined (CONFIG_ARCH_SUN8IW17P1) || defined (CONFIG_ARCH_SUN8IW16P1)
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/*isp0 input0~3*/
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{
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{{0, 4, 0, 0}, {1, 5, 0, 0}, {2, 6, 0, 0}, {3, 7, 0, 0} },
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{{0, 0, 0, 0}, {0, 1, 0, 0}, {0, 2, 0, 0}, {0, 3, 0, 0} },
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{{0, 0, 0, 0}, {0, 0, 1, 0}, {0, 0, 2, 0}, {0, 0, 3, 0} },
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{{0, 0, 0, 0}, {0, 0, 0, 1}, {0, 0, 0, 2}, {0, 0, 0, 3} }
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},
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/*isp1 input0~3*/
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{
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{{0, 4, 0, 0}, {1, 5, 0, 0}, {2, 6, 0, 0}, {3, 7, 0, 0} },
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{{0, 0, 0, 0}, {0, 1, 0, 0}, {0, 2, 0, 0}, {0, 3, 0, 0} },
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{{0, 0, 0, 0}, {0, 0, 1, 0}, {0, 0, 2, 0}, {0, 0, 3, 0} },
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{{0, 0, 0, 0}, {0, 0, 0, 1}, {0, 0, 0, 2}, {0, 0, 0, 3} }
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},
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/*isp2 input0~3*/
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{
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{{0, 4, 0, 0}, {1, 5, 0, 0}, {2, 6, 0, 0}, {3, 7, 0, 0} },
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{{0, 0, 0, 0}, {0, 1, 0, 0}, {0, 2, 0, 0}, {0, 3, 0, 0} },
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{{0, 0, 0, 0}, {0, 0, 1, 0}, {0, 0, 2, 0}, {0, 0, 3, 0} },
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{{0, 0, 0, 0}, {0, 0, 0, 1}, {0, 0, 0, 2}, {0, 0, 0, 3} }
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},
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/*isp3 input0~3*/
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{
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{{0, 4, 0, 0}, {1, 5, 0, 0}, {2, 6, 0, 0}, {3, 7, 0, 0} },
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{{0, 0, 0, 0}, {0, 1, 0, 0}, {0, 2, 0, 0}, {0, 3, 0, 0} },
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{{0, 0, 0, 0}, {0, 0, 1, 0}, {0, 0, 2, 0}, {0, 0, 3, 0} },
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{{0, 0, 0, 0}, {0, 0, 0, 1}, {0, 0, 0, 2}, {0, 0, 0, 3} }
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}
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#else
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/*isp0 input0~3*/
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{
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }
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},
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/*isp1 input0~3*/
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{
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }
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},
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/*isp2 input0~3*/
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{
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }
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},
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/*isp3 input0~3*/
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{
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }
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},
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#endif
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};
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/*vipp_id isp_id isp_ch*/
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static char vipp_input[8][4][4] = {
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#if defined(CONFIG_ARCH_SUN50IW3P1) || defined(CONFIG_ARCH_SUN50IW6P1)
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/*vipp0*/
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/*isp0*/ /*isp1*/ /*isp2*/ /*isp3*/
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{{0, 0, 0, 0}, {1, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
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{{0, 2, 0, 0}, {1, 3, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
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{{0, 0, 2, 0}, {1, 0, 3, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
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{{0, 0, 0, 2}, {1, 4, 0, 3}, {0, 0, 0, 0}, {0, 0, 0, 0} },
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#elif defined (CONFIG_ARCH_SUN8IW15P1) || defined (CONFIG_ARCH_SUN8IW17P1) || defined (CONFIG_ARCH_SUN8IW16P1)
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{{0, 0, 0, 0}, {1, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
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{{0, 2, 0, 0}, {1, 3, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
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{{0, 0, 2, 0}, {1, 0, 3, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
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{{0, 0, 0, 2}, {1, 4, 0, 3}, {0, 0, 0, 0}, {0, 0, 0, 0} },
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{{0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {1, 0, 0, 0} },
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{{0, 0, 0, 0}, {0, 0, 0, 0}, {0, 2, 0, 0}, {1, 3, 0, 0} },
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{{0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 2, 0}, {1, 0, 3, 0} },
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{{0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 2}, {1, 4, 0, 3} }
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#else
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
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#endif
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};
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#if defined (CONFIG_ARCH_SUN50IW9P1)
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static char dma_input[8][4][4] = {
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/*parser0*/ /*parser1*/ /*parser2*/ /*parser3*/
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }, /*dma0*/
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }, /*dma1*/
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }, /*dma2*/
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }, /*dma3*/
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }, /*dma4*/
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }, /*dma5*/
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }, /*dma6*/
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{{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} } /*dma7*/
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};
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#endif
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volatile void __iomem *csic_top_base[MAX_CSIC_TOP_NUM];
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volatile void __iomem *csic_ccu_base;
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/*
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* functions about top register
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*/
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int csic_top_set_base_addr(unsigned int sel, unsigned long addr)
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{
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if (sel > MAX_CSIC_TOP_NUM - 1)
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return -1;
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csic_top_base[sel] = (volatile void __iomem *)addr;
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return 0;
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}
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void csic_top_enable(unsigned int sel)
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{
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vin_reg_clr_set(csic_top_base[sel] + CSIC_TOP_EN_REG_OFF,
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CSIC_TOP_EN_MASK, 1 << CSIC_TOP_EN);
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}
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void csic_top_disable(unsigned int sel)
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{
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vin_reg_clr_set(csic_top_base[sel] + CSIC_TOP_EN_REG_OFF,
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CSIC_TOP_EN_MASK, 0 << CSIC_TOP_EN);
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}
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void csic_isp_bridge_enable(unsigned int sel)
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{
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vin_reg_clr_set(csic_top_base[sel] + CSIC_TOP_EN_REG_OFF,
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CSIC_ISP_BRIDGE_EN_MASK, 1 << CSIC_ISP_BRIDGE_EN);
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}
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void csic_isp_bridge_disable(unsigned int sel)
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{
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vin_reg_clr_set(csic_top_base[sel] + CSIC_TOP_EN_REG_OFF,
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CSIC_ISP_BRIDGE_EN_MASK, 0 << CSIC_ISP_BRIDGE_EN);
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}
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void csic_top_sram_pwdn(unsigned int sel, unsigned int en)
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{
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vin_reg_clr_set(csic_top_base[sel] + CSIC_TOP_EN_REG_OFF,
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CSIC_SRAM_PWDN_MASK, en << CSIC_SRAM_PWDN);
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}
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void csic_top_version_read_en(unsigned int sel, unsigned int en)
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{
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vin_reg_clr_set(csic_top_base[sel] + CSIC_TOP_EN_REG_OFF,
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CSIC_VER_EN_MASK, en << CSIC_VER_EN);
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}
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void csic_isp_input_select(unsigned int sel, unsigned int isp, unsigned int in,
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unsigned int psr, unsigned int ch)
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{
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vin_reg_writel(csic_top_base[sel] + CSIC_ISP0_IN0_REG_OFF + isp * 16 + in * 4,
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isp_input[isp][in][psr][ch]);
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}
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void csic_vipp_input_select(unsigned int sel, unsigned int vipp,
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unsigned int isp, unsigned int ch)
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{
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vin_reg_writel(csic_top_base[sel] + CSIC_VIPP0_IN_REG_OFF + vipp * 4,
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vipp_input[vipp][isp][ch]);
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}
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void csic_dma_input_select(unsigned int sel, unsigned int dma,
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unsigned int parser, unsigned int ch)
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{
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#if defined (CONFIG_ARCH_SUN50IW9P1)
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vin_reg_writel(csic_top_base[sel] + CSIC_VIPP0_IN_REG_OFF + dma * 4,
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dma_input[dma][parser][ch]);
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#endif
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}
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void csic_feature_list_get(unsigned int sel, struct csic_feature_list *fl)
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{
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unsigned int reg_val = 0;
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reg_val = vin_reg_readl(csic_top_base[sel] + CSIC_FEATURE_REG_OFF);
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fl->dma_num = (reg_val & CSIC_DMA_NUM_MASK) >> CSIC_DMA_NUM;
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fl->vipp_num = (reg_val & CSIC_VIPP_NUM_MASK) >> CSIC_VIPP_NUM;
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fl->isp_num = (reg_val & CSIC_ISP_NUM_MASK) >> CSIC_ISP_NUM;
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fl->ncsi_num = (reg_val & CSIC_NCSI_NUM_MASK) >> CSIC_NCSI_NUM;
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fl->mcsi_num = (reg_val & CSIC_MCSI_NUM_MASK) >> CSIC_MCSI_NUM;
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fl->parser_num = (reg_val & CSIC_PARSER_NUM_MASK) >> CSIC_PARSER_NUM;
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}
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void csic_version_get(unsigned int sel, struct csic_version *v)
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{
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unsigned int reg_val = 0;
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reg_val = vin_reg_readl(csic_top_base[sel] + CSIC_VER_REG_OFF);
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v->ver_small = (reg_val & CSIC_VER_SMALL_MASK) >> CSIC_VER_SMALL;
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v->ver_big = (reg_val & CSIC_VER_BIG_MASK) >> CSIC_VER_BIG;
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}
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void csic_mbus_req_mex_set(unsigned int sel, unsigned int data)
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{
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#if !defined CONFIG_ARCH_SUN8IW15P1 && !defined CONFIG_ARCH_SUN8IW16P1 && !defined CONFIG_ARCH_SUN8IW17P1 && !defined CONFIG_ARCH_SUN50IW9P1 && !defined CONFIG_ARCH_SUN50IW3P1 && !defined CONFIG_ARCH_SUN50IW6P1
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|
vin_reg_clr_set(csic_top_base[sel] + CSIC_MBUS_REQ_MAX,
|
||
|
|
MCSI_MEM_REQ_MAX_MASK, data << MCSI_MEM_REQ_MAX);
|
||
|
|
vin_reg_clr_set(csic_top_base[sel] + CSIC_MBUS_REQ_MAX,
|
||
|
|
MCSI_MEM_1_REQ_MAX_MASK, data << MCSI_MEM_1_REQ_MAX);
|
||
|
|
vin_reg_clr_set(csic_top_base[sel] + CSIC_MBUS_REQ_MAX,
|
||
|
|
MISP_MEM_REQ_MAX_MASK, data << MISP_MEM_REQ_MAX);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_mulp_mode_en(unsigned int sel, unsigned int en)
|
||
|
|
{
|
||
|
|
vin_reg_clr_set(csic_top_base[sel] + CSIC_MULP_MODE_REG_OFF,
|
||
|
|
CSIC_MULP_EN_MASK, en << CSIC_MULP_EN);
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_mulp_dma_cs(unsigned int sel, enum csic_mulp_cs cs)
|
||
|
|
{
|
||
|
|
vin_reg_clr_set(csic_top_base[sel] + CSIC_MULP_MODE_REG_OFF,
|
||
|
|
CSIC_MULP_CS_MASK, cs << CSIC_MULP_CS);
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_mulp_int_enable(unsigned int sel, enum csis_mulp_int interrupt)
|
||
|
|
{
|
||
|
|
vin_reg_clr_set(csic_top_base[sel] + CSIC_MULP_INT_REG_OFF,
|
||
|
|
CSIC_MULP_INT_EN_MASK, interrupt << CSIC_MULP_INT_EN);
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_mulp_int_disable(unsigned int sel, enum csis_mulp_int interrupt)
|
||
|
|
{
|
||
|
|
vin_reg_clr_set(csic_top_base[sel] + CSIC_MULP_INT_REG_OFF,
|
||
|
|
CSIC_MULP_INT_EN_MASK, ~interrupt << CSIC_MULP_INT_EN);
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_mulp_int_get_status(unsigned int sel, struct cisc_mulp_int_status *status)
|
||
|
|
{
|
||
|
|
unsigned int reg_val = vin_reg_readl(csic_top_base[sel] + CSIC_MULP_INT_REG_OFF);
|
||
|
|
|
||
|
|
status->mulf_done = (reg_val & CSIC_MULP_DONE_PD_MASK) >> CSIC_MULP_DONE_PD;
|
||
|
|
status->mulf_err = (reg_val & CSIC_MULP_ERR_PD_MASK) >> CSIC_MULP_ERR_PD;
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_mulp_int_clear_status(unsigned int sel, enum csis_mulp_int interrupt)
|
||
|
|
{
|
||
|
|
vin_reg_clr_set(csic_top_base[sel] + CSIC_MULP_INT_REG_OFF,
|
||
|
|
CSIC_MULP_INT_PD_MASK, interrupt << CSIC_MULP_DONE_PD);
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_ptn_generation_en(unsigned int sel, unsigned int en)
|
||
|
|
{
|
||
|
|
vin_reg_clr_set(csic_top_base[sel] + CSIC_PTN_GEN_EN_REG_OFF,
|
||
|
|
CSIC_PTN_GEN_CYCLE_MASK, 0xff << CSIC_PTN_GEN_CYCLE);
|
||
|
|
vin_reg_clr_set(csic_top_base[sel] + CSIC_PTN_GEN_EN_REG_OFF,
|
||
|
|
CSIC_PTN_GEN_EN_MASK, en << CSIC_PTN_GEN_EN);
|
||
|
|
vin_reg_clr_set(csic_top_base[sel] + CSIC_PTN_GEN_EN_REG_OFF,
|
||
|
|
CSIC_PTN_GEN_START_MASK, en << CSIC_PTN_GEN_START);
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_ptn_control(unsigned int sel, int mode, int dw, int port)
|
||
|
|
{
|
||
|
|
vin_reg_clr_set(csic_top_base[sel] + CSIC_PTN_CTRL_REG_OFF,
|
||
|
|
CSIC_PTN_GEN_DLY_MASK, 4 << CSIC_PTN_GEN_DLY);
|
||
|
|
vin_reg_clr_set(csic_top_base[sel] + CSIC_PTN_CTRL_REG_OFF,
|
||
|
|
CSIC_PTN_CLK_DIV_MASK, 3 << CSIC_PTN_CLK_DIV);
|
||
|
|
vin_reg_clr_set(csic_top_base[sel] + CSIC_PTN_CTRL_REG_OFF,
|
||
|
|
CSIC_PTN_MODE_MASK, mode << CSIC_PTN_MODE);
|
||
|
|
vin_reg_clr_set(csic_top_base[sel] + CSIC_PTN_CTRL_REG_OFF,
|
||
|
|
CSIC_PTN_DATA_WIDTH_MASK, dw << CSIC_PTN_DATA_WIDTH);
|
||
|
|
vin_reg_clr_set(csic_top_base[sel] + CSIC_PTN_CTRL_REG_OFF,
|
||
|
|
CSIC_PTN_PORT_SEL_MASK, port << CSIC_PTN_PORT_SEL);
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_ptn_length(unsigned int sel, unsigned int len)
|
||
|
|
{
|
||
|
|
vin_reg_writel(csic_top_base[sel] + CSIC_PTN_LEN_REG_OFF, len);
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_ptn_addr(unsigned int sel, unsigned long dma_addr)
|
||
|
|
{
|
||
|
|
vin_reg_writel(csic_top_base[sel] + CSIC_PTN_ADDR_REG_OFF, dma_addr >> 2);
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_ptn_size(unsigned int sel, unsigned int w, unsigned int h)
|
||
|
|
{
|
||
|
|
return;
|
||
|
|
vin_reg_clr_set(csic_top_base[sel] + CSIC_PTN_SIZE_REG_OFF,
|
||
|
|
CSIC_PTN_WIDTH_MASK, w << CSIC_PTN_WIDTH);
|
||
|
|
vin_reg_clr_set(csic_top_base[sel] + CSIC_PTN_SIZE_REG_OFF,
|
||
|
|
CSIC_PTN_HEIGHT_MASK, h << CSIC_PTN_HEIGHT);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* functions about ccu register
|
||
|
|
*/
|
||
|
|
int csic_ccu_set_base_addr(unsigned long addr)
|
||
|
|
{
|
||
|
|
csic_ccu_base = (volatile void __iomem *)addr;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_ccu_clk_gating_enable(void)
|
||
|
|
{
|
||
|
|
vin_reg_clr_set(csic_ccu_base + CSIC_CCU_MODE_REG_OFF,
|
||
|
|
CSIC_CCU_CLK_GATING_DISABLE_MASK, 0 << CSIC_CCU_CLK_GATING_DISABLE);
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_ccu_clk_gating_disable(void)
|
||
|
|
{
|
||
|
|
vin_reg_clr_set(csic_ccu_base + CSIC_CCU_MODE_REG_OFF,
|
||
|
|
CSIC_CCU_CLK_GATING_DISABLE_MASK, 1 << CSIC_CCU_CLK_GATING_DISABLE);
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_ccu_mcsi_clk_mode(unsigned int mode)
|
||
|
|
{
|
||
|
|
vin_reg_clr_set(csic_ccu_base + CSIC_CCU_MODE_REG_OFF,
|
||
|
|
CSIC_MCSI_CLK_MODE_MASK, mode << CSIC_MCSI_CLK_MODE);
|
||
|
|
vin_reg_clr_set(csic_ccu_base + CSIC_CCU_MODE_REG_OFF,
|
||
|
|
CSIC_MCSI_POST_CLK_MODE_MASK, mode << CSIC_MCSI_POST_CLK_MODE);
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_ccu_mcsi_combo_clk_en(unsigned int sel, unsigned int en)
|
||
|
|
{
|
||
|
|
vin_reg_clr_set(csic_ccu_base + CSIC_CCU_PARSER_CLK_EN_REG_OFF,
|
||
|
|
CSIC_MCSI_COMBO0_CLK_EN_MASK << sel, en << (CSIC_MCSI_COMBO0_CLK_EN + sel));
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_ccu_mcsi_mipi_clk_en(unsigned int sel, unsigned int en)
|
||
|
|
{
|
||
|
|
vin_reg_clr_set(csic_ccu_base + CSIC_CCU_PARSER_CLK_EN_REG_OFF,
|
||
|
|
CSIC_MCSI_MIPI0_CLK_EN_MASK << sel, en << (CSIC_MCSI_MIPI0_CLK_EN + sel));
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_ccu_mcsi_parser_clk_en(unsigned int sel, unsigned int en)
|
||
|
|
{
|
||
|
|
vin_reg_clr_set(csic_ccu_base + CSIC_CCU_PARSER_CLK_EN_REG_OFF,
|
||
|
|
CSIC_MCSI_PARSER0_CLK_EN_MASK << sel, en << (CSIC_MCSI_PARSER0_CLK_EN + sel));
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_ccu_misp_isp_clk_en(unsigned int sel, unsigned int en)
|
||
|
|
{
|
||
|
|
vin_reg_clr_set(csic_ccu_base + CSIC_CCU_ISP_CLK_EN_REG_OFF,
|
||
|
|
CSIC_MISP0_CLK_EN_MASK << sel, en << (CSIC_MISP0_CLK_EN + sel));
|
||
|
|
vin_reg_clr_set(csic_ccu_base + CSIC_CCU_ISP_CLK_EN_REG_OFF,
|
||
|
|
CSIC_MISP0_BRIDGE_CLK_EN_MASK << sel, en << (CSIC_MISP0_BRIDGE_CLK_EN + sel));
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_ccu_mcsi_post_clk_enable(unsigned int sel)
|
||
|
|
{
|
||
|
|
vin_reg_clr_set(csic_ccu_base + CSIC_CCU_POST0_CLK_EN_REG_OFF + sel*4,
|
||
|
|
CSIC_MCSI_POST0_CLK_EN_MASK, 1 << CSIC_MCSI_POST0_CLK_EN);
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_ccu_mcsi_post_clk_disable(unsigned int sel)
|
||
|
|
{
|
||
|
|
vin_reg_clr_set(csic_ccu_base + CSIC_CCU_POST0_CLK_EN_REG_OFF + sel*4,
|
||
|
|
CSIC_MCSI_POST0_CLK_EN_MASK, 0 << CSIC_MCSI_POST0_CLK_EN);
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_ccu_bk_clk_en(unsigned int sel, unsigned int en)
|
||
|
|
{
|
||
|
|
if (sel < 4)
|
||
|
|
vin_reg_clr_set(csic_ccu_base + CSIC_CCU_POST0_CLK_EN_REG_OFF,
|
||
|
|
CSIC_MCSI_BK0_CLK_EN_MASK << sel, en << (CSIC_MCSI_BK0_CLK_EN + sel));
|
||
|
|
else
|
||
|
|
vin_reg_clr_set(csic_ccu_base + CSIC_CCU_POST0_CLK_EN_REG_OFF + 0x4,
|
||
|
|
CSIC_MCSI_BK0_CLK_EN_MASK << (sel-4), en << (CSIC_MCSI_BK0_CLK_EN + (sel-4)));
|
||
|
|
}
|
||
|
|
|
||
|
|
void csic_ccu_vipp_clk_en(unsigned int sel, unsigned int en)
|
||
|
|
{
|
||
|
|
if (sel < 4)
|
||
|
|
vin_reg_clr_set(csic_ccu_base + CSIC_CCU_POST0_CLK_EN_REG_OFF,
|
||
|
|
CSIC_MCSI_VIPP0_CLK_EN_MASK << sel, en << (CSIC_MCSI_VIPP0_CLK_EN + sel));
|
||
|
|
else
|
||
|
|
vin_reg_clr_set(csic_ccu_base + CSIC_CCU_POST0_CLK_EN_REG_OFF + 0x4,
|
||
|
|
CSIC_MCSI_VIPP0_CLK_EN_MASK << (sel-4), en << (CSIC_MCSI_VIPP0_CLK_EN + (sel-4)));
|
||
|
|
}
|
||
|
|
|