530 lines
14 KiB
C
530 lines
14 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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#define pr_fmt(fmt) "sunxi-spinand-phy: " fmt
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mtd/aw-spinand.h>
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#if IS_ENABLED(CONFIG_AW_SPINAND_ENABLE_PHY_CRC16)
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#include <linux/crc16.h>
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#endif
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#include "physic.h"
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#define INVALID_CACHE ((unsigned int)(-1))
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static void update_cache_info(struct aw_spinand_cache *cache,
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struct aw_spinand_chip_request *req)
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{
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if (req && (req->databuf || req->oobbuf)) {
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cache->block = req->block;
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cache->page = req->page;
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cache->area = INVALID_CACHE_ALL_AREA;
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if (req->databuf)
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cache->area |= VALID_CACHE_DATA;
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if (req->oobbuf)
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cache->area |= VALID_CACHE_OOB;
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pr_debug("update cache: phy blk %u page %u with%s%s\n",
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req->block, req->page,
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req->databuf ? " data" : "",
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req->oobbuf ? " oob" : "");
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} else {
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cache->block = INVALID_CACHE;
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cache->page = INVALID_CACHE;
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cache->area = INVALID_CACHE_ALL_AREA;
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pr_info("clear cache\n");
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}
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}
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/* the request must bases on single physical page/block */
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#if IS_ENABLED(CONFIG_AW_MTD_SPINAND_OOB_RAW_SPARE)
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static int aw_spinand_cache_copy_to_cache(struct aw_spinand_chip *chip,
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struct aw_spinand_chip_request *req)
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{
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unsigned int len;
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struct aw_spinand_cache *cache = chip->cache;
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unsigned char *databuf = cache->databuf;
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unsigned char *oobbuf = databuf + cache->data_maxlen;
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memset(databuf, 0xFF, cache->data_maxlen);
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if (req->databuf && req->datalen) {
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len = min(req->datalen, cache->data_maxlen - req->pageoff);
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memcpy(databuf + req->pageoff, req->databuf, len);
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}
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memset(oobbuf, 0xFF, cache->oob_maxlen);
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if (req->oobbuf && req->ooblen) {
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len = min(req->ooblen, cache->oob_maxlen);
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memcpy(oobbuf, req->oobbuf, len);
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}
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/* we must update cache information when update cache buffer */
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update_cache_info(cache, req);
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return 0;
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}
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/* the request must bases on single physical page/block */
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static int aw_spinand_cache_copy_from_cache(struct aw_spinand_chip *chip,
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struct aw_spinand_chip_request *req)
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{
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unsigned int len;
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struct aw_spinand_cache *cache = chip->cache;
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if (req->datalen && req->databuf) {
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len = min(req->datalen, cache->data_maxlen - req->pageoff);
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memcpy(req->databuf, cache->databuf + req->pageoff, len);
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}
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if (req->oobbuf && req->ooblen) {
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len = min(req->ooblen, cache->oob_maxlen);
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memcpy(req->oobbuf, cache->oobbuf, len);
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}
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return 0;
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}
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#else
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static int aw_spinand_cache_copy_to_cache(struct aw_spinand_chip *chip,
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struct aw_spinand_chip_request *req)
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{
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unsigned int len;
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struct aw_spinand_cache *cache = chip->cache;
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BUG_ON(req->pageoff + req->datalen > cache->data_maxlen);
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BUG_ON(req->ooblen > cache->oob_maxlen);
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memset(cache->databuf, 0xFF, cache->data_maxlen);
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if (req->databuf && req->datalen) {
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len = min(req->datalen, cache->data_maxlen - req->pageoff);
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memcpy(cache->databuf + req->pageoff, req->databuf, len);
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}
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memset(cache->oobbuf, 0xFF, cache->oob_maxlen);
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if (req->oobbuf && req->ooblen) {
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if (req->mode != AW_SPINAND_MTD_OPS_RAW) {
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int ret;
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struct aw_spinand_ecc *ecc = chip->ecc;
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struct aw_spinand_info *info = chip->info;
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struct aw_spinand_phy_info *pinfo = info->phy_info;
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len = min3(req->ooblen, cache->oob_maxlen,
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(unsigned int)AW_OOB_SIZE_PER_PHY_PAGE);
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ret = ecc->copy_to_oob(pinfo->EccProtectedType,
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cache->oobbuf, req->oobbuf, len);
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if (unlikely(ret))
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return ret;
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} else {
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len = min3(req->ooblen, cache->oob_maxlen,
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(unsigned int)AW_OOB_SIZE_PER_PHY_PAGE);
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memcpy(cache->oobbuf, req->oobbuf, len);
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}
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}
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/* we must update cache information when update cache buffer */
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update_cache_info(cache, req);
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return 0;
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}
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/* the request must bases on single physical page/block */
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static int aw_spinand_cache_copy_from_cache(struct aw_spinand_chip *chip,
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struct aw_spinand_chip_request *req)
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{
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unsigned int len;
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struct aw_spinand_cache *cache = chip->cache;
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WARN_ON(!cache->match_cache(chip, req));
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if (req->datalen && req->databuf) {
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len = min(req->datalen, cache->data_maxlen - req->pageoff);
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memcpy(req->databuf, cache->databuf + req->pageoff, len);
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}
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if (req->oobbuf && req->ooblen) {
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if (req->mode != AW_SPINAND_MTD_OPS_RAW) {
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int ret;
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struct aw_spinand_ecc *ecc = chip->ecc;
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struct aw_spinand_info *info = chip->info;
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struct aw_spinand_phy_info *pinfo = info->phy_info;
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len = min3(req->ooblen, cache->oob_maxlen,
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(unsigned int)AW_OOB_SIZE_PER_PHY_PAGE);
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ret = ecc->copy_from_oob(pinfo->EccProtectedType,
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req->oobbuf, cache->oobbuf, len);
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if (unlikely(ret))
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return ret;
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} else {
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len = min3(req->ooblen, cache->oob_maxlen,
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(unsigned int)AW_OOB_SIZE_PER_PHY_PAGE);
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memcpy(req->oobbuf, cache->oobbuf, len);
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}
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}
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return 0;
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}
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#endif
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static bool aw_spinand_cache_match_cache(struct aw_spinand_chip *chip,
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struct aw_spinand_chip_request *req)
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{
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struct aw_spinand_cache *cache = chip->cache;
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if (cache->block == INVALID_CACHE || cache->page == INVALID_CACHE)
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return false;
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if (req->block != cache->block || req->page != cache->page)
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return false;
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if (req->databuf && !(cache->area & VALID_CACHE_DATA))
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return false;
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if (req->oobbuf && !(cache->area & VALID_CACHE_OOB))
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return false;
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return true;
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}
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static int aw_spinand_cahce_write_to_cache_do(struct aw_spinand_chip *chip,
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void *buf, unsigned int len, unsigned int column,
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struct aw_spinand_chip_request *req)
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{
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struct aw_spinand_info *info = chip->info;
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struct aw_spinand_phy_info *pinfo = info->phy_info;
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unsigned char txbuf[3];
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struct spi_message msg;
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struct spi_transfer t[2] = {};
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spi_message_init(&msg);
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if (chip->tx_bit == SPI_NBITS_QUAD)
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txbuf[0] = column ? SPI_NAND_RANDOM_PP_X4 : SPI_NAND_PP_X4;
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else
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txbuf[0] = column ? SPI_NAND_RANDOM_PP : SPI_NAND_PP;
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txbuf[1] = (column >> 8) & 0xFF;
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txbuf[2] = column & 0xFF;
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if ((pinfo->OperationOpt & SPINAND_TWO_PLANE_SELECT) &&
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(req->block % 2 == 1))
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txbuf[1] |= SPI_SELECT_ODDNUM_BLACK;
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t[0].tx_buf = txbuf;
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t[0].len = 3;
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spi_message_add_tail(&t[0], &msg);
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t[1].tx_buf = buf;
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t[1].len = len;
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t[1].tx_nbits = chip->tx_bit;
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spi_message_add_tail(&t[1], &msg);
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return spi_sync(chip->spi, &msg);
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}
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static int write_to_cache_half_page_twice(struct aw_spinand_chip *chip,
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struct aw_spinand_chip_request *req)
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{
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int ret;
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struct aw_spinand_info *info = chip->info;
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struct aw_spinand_cache *cache = chip->cache;
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unsigned int column = 0, half_page_size;
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half_page_size = info->phy_page_size(chip) >> 1;
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/* the first half page */
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ret = aw_spinand_cahce_write_to_cache_do(chip, cache->databuf,
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half_page_size, column, req);
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if (ret)
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return ret;
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/* the secend half page */
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column += half_page_size;
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return aw_spinand_cahce_write_to_cache_do(chip,
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cache->databuf + half_page_size,
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half_page_size + info->phy_oob_size(chip),
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column, req);
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}
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static int write_to_cache_whole_page_once(struct aw_spinand_chip *chip,
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struct aw_spinand_chip_request *req)
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{
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struct aw_spinand_info *info = chip->info;
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struct aw_spinand_cache *cache = chip->cache;
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/* write the whole page */
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return aw_spinand_cahce_write_to_cache_do(chip, cache->databuf,
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info->phy_page_size(chip) + info->phy_oob_size(chip),
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0, req);
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}
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#if IS_ENABLED(CONFIG_AW_SPINAND_ENABLE_PHY_CRC16)
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static int aw_spinand_chip_verify_crc(struct aw_spinand_chip *chip,
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struct aw_spinand_chip_request *req)
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{
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struct aw_spinand_cache *cache = chip->cache;
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__u16 crc = 0, crc_verify = 0;
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if (!req->databuf || !req->oobbuf)
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return 0;
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crc_verify = ((unsigned char *)req->oobbuf)[AW_CRC16_OOB_OFFSET] << 8;
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crc_verify += ((unsigned char *)req->oobbuf)[AW_CRC16_OOB_OFFSET + 1];
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/* we should check cache->databuf rather than req->databuf */
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crc = crc16(0, cache->databuf, cache->data_maxlen);
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/*
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* If databuf are all 0xFF, the CRC16 value will be 0xA041.
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* In this case, we should return directly
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*/
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if (crc_verify == (__u16)0xFFFF && crc == (__u16)0xA041)
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return 0;
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/*
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* CRC16 is used for debug
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* So, we just print warning, do not do anything now
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*/
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if (crc != crc_verify) {
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pr_warn("phy blk %u page %u crc16 check failed: want 0x%04x get 0x%04x\n",
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req->block, req->page, crc_verify, crc);
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aw_spinand_hexdump(KERN_WARNING, "oob: ", req->oobbuf,
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req->ooblen);
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aw_spinand_hexdump(KERN_WARNING, "data: ", cache->databuf,
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cache->data_maxlen);
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return -EINVAL;
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}
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pr_debug("phy blk %u page %u crc16 check pass\n", req->block,
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req->page);
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return 0;
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}
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static int aw_spinand_chip_update_crc(struct aw_spinand_chip *chip,
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struct aw_spinand_chip_request *req)
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{
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struct aw_spinand_info *info = chip->info;
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__u16 crc = 0;
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crc = crc16(0, req->databuf, info->phy_page_size(chip));
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((char *)req->oobbuf)[AW_CRC16_OOB_OFFSET] = crc >> 8;
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((char *)req->oobbuf)[AW_CRC16_OOB_OFFSET + 1] = crc & 0xFF;
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pr_debug("record blk %u page %u crc16 0x%04x\n", req->block, req->page, crc);
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return 0;
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}
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#endif
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/*
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* 3 step:
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* a) copy data from req to cache->databuf/oobbuf
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* b) update cache->block/page
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* c) send write cache command to spinand
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*/
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static int aw_spinand_cache_write_to_cache(struct aw_spinand_chip *chip,
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struct aw_spinand_chip_request *req)
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{
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int ret;
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const char *manufacture;
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struct aw_spinand_info *info = chip->info;
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struct aw_spinand_cache *cache = chip->cache;
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#if IS_ENABLED(CONFIG_AW_SPINAND_ENABLE_PHY_CRC16)
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unsigned char oob[AW_OOB_SIZE_PER_PHY_PAGE] = {0xFF};
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#endif
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#if IS_ENABLED(CONFIG_AW_SPINAND_ENABLE_PHY_CRC16)
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if (!req->oobbuf) {
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req->oobbuf = oob;
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req->ooblen = AW_OOB_SIZE_PER_PHY_PAGE;
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}
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aw_spinand_chip_update_crc(chip, req);
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#endif
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ret = cache->copy_to_cache(chip, req);
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if (ret)
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goto err;
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manufacture = info->manufacture(chip);
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if (!strcmp(manufacture, "Winbond"))
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/*
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* Winbond spinand has a feature:
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* Data cache in spinand is divide to 2 parts to inprove speed.
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* We work with winbond engineers, however, still have no idea
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* why the spinand will get wrong data, always 2 bytes 0xFF on
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* the head of the 2rd part on cache.
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* To fix it, we are recommended to write twice, half of data
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* each time
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*/
|
||
|
|
ret = write_to_cache_half_page_twice(chip, req);
|
||
|
|
else
|
||
|
|
ret = write_to_cache_whole_page_once(chip, req);
|
||
|
|
if (ret)
|
||
|
|
goto err;
|
||
|
|
|
||
|
|
/* we must update cache information when update cache buffer */
|
||
|
|
update_cache_info(cache, req);
|
||
|
|
#if IS_ENABLED(CONFIG_AW_SPINAND_ENABLE_PHY_CRC16)
|
||
|
|
if (req->oobbuf == oob) {
|
||
|
|
req->oobbuf = NULL;
|
||
|
|
req->ooblen = req->oobleft = 0;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
return 0;
|
||
|
|
err:
|
||
|
|
/*
|
||
|
|
* the cache buffer is invalid now as we do not know
|
||
|
|
* what had done to cache buffer
|
||
|
|
*/
|
||
|
|
update_cache_info(cache, NULL);
|
||
|
|
#if IS_ENABLED(CONFIG_AW_SPINAND_ENABLE_PHY_CRC16)
|
||
|
|
if (req->oobbuf == oob) {
|
||
|
|
req->oobbuf = NULL;
|
||
|
|
req->ooblen = req->oobleft = 0;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* 3 step:
|
||
|
|
* a) copy data from req to cache->databuf/oobbuf
|
||
|
|
* b) update cache->block/page
|
||
|
|
* c) send write cache command to spinand
|
||
|
|
*/
|
||
|
|
static int aw_spinand_cache_read_from_cache(struct aw_spinand_chip *chip,
|
||
|
|
struct aw_spinand_chip_request *req)
|
||
|
|
{
|
||
|
|
unsigned int rbytes = 0;
|
||
|
|
void *rbuf = NULL;
|
||
|
|
int column = 0, ret;
|
||
|
|
unsigned char txbuf[5];
|
||
|
|
struct aw_spinand_info *info = chip->info;
|
||
|
|
struct aw_spinand_phy_info *pinfo = info->phy_info;
|
||
|
|
struct aw_spinand_cache *cache = chip->cache;
|
||
|
|
struct spi_message msg;
|
||
|
|
struct spi_transfer t[2] = {};
|
||
|
|
#if IS_ENABLED(CONFIG_AW_SPINAND_ENABLE_PHY_CRC16)
|
||
|
|
unsigned char oob[AW_OOB_SIZE_PER_PHY_PAGE] = {0xFF};
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_AW_SPINAND_ENABLE_PHY_CRC16)
|
||
|
|
if (req->databuf && !req->oobbuf) {
|
||
|
|
req->oobbuf = oob;
|
||
|
|
req->ooblen = AW_OOB_SIZE_PER_PHY_PAGE;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
if (req->datalen) {
|
||
|
|
rbuf = cache->databuf;
|
||
|
|
rbytes = cache->data_maxlen;
|
||
|
|
column = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (req->ooblen) {
|
||
|
|
rbytes += cache->oob_maxlen;
|
||
|
|
/* just oob without data */
|
||
|
|
if (!rbuf) {
|
||
|
|
rbuf = cache->oobbuf;
|
||
|
|
column = info->phy_page_size(chip);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
spi_message_init(&msg);
|
||
|
|
|
||
|
|
if (chip->rx_bit == SPI_NBITS_QUAD)
|
||
|
|
txbuf[0] = SPI_NAND_READ_X4;
|
||
|
|
else if (chip->rx_bit == SPI_NBITS_DUAL)
|
||
|
|
txbuf[0] = SPI_NAND_READ_X2;
|
||
|
|
else
|
||
|
|
txbuf[0] = SPI_NAND_FAST_READ_X1;
|
||
|
|
|
||
|
|
if (pinfo->OperationOpt & SPINAND_ONEDUMMY_AFTER_RANDOMREAD) {
|
||
|
|
/* 1byte dummy */
|
||
|
|
txbuf[1] = 0x00;
|
||
|
|
txbuf[2] = (column >> 8) & 0xFF;
|
||
|
|
txbuf[3] = column & 0xFF;
|
||
|
|
txbuf[4] = 0x00;
|
||
|
|
t[0].len = 5;
|
||
|
|
} else {
|
||
|
|
txbuf[1] = (column >> 8) & 0xFF;
|
||
|
|
txbuf[2] = column & 0xFF;
|
||
|
|
txbuf[3] = 0x00;
|
||
|
|
if ((pinfo->OperationOpt & SPINAND_TWO_PLANE_SELECT) &&
|
||
|
|
(req->block % 2 == 1))
|
||
|
|
txbuf[1] |= SPI_SELECT_ODDNUM_BLACK;
|
||
|
|
t[0].len = 4;
|
||
|
|
}
|
||
|
|
|
||
|
|
t[0].tx_buf = txbuf;
|
||
|
|
spi_message_add_tail(&t[0], &msg);
|
||
|
|
|
||
|
|
/* to select the signal line count */
|
||
|
|
t[1].rx_nbits = chip->rx_bit;
|
||
|
|
t[1].rx_buf = rbuf;
|
||
|
|
t[1].len = rbytes;
|
||
|
|
spi_message_add_tail(&t[1], &msg);
|
||
|
|
|
||
|
|
ret = spi_sync(chip->spi, &msg);
|
||
|
|
if (ret) {
|
||
|
|
/*
|
||
|
|
* the cache buffer is invalid now as we do not know
|
||
|
|
* what spi system had done to cache buffer
|
||
|
|
*/
|
||
|
|
update_cache_info(cache, NULL);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* we must update cache information when update cache buffer */
|
||
|
|
update_cache_info(cache, req);
|
||
|
|
|
||
|
|
/* no need to update cache information as no change happened */
|
||
|
|
ret = cache->copy_from_cache(chip, req);
|
||
|
|
if (unlikely(ret))
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_AW_SPINAND_ENABLE_PHY_CRC16)
|
||
|
|
aw_spinand_chip_verify_crc(chip, req);
|
||
|
|
if (req->oobbuf == oob) {
|
||
|
|
req->oobbuf = NULL;
|
||
|
|
req->ooblen = req->oobleft = 0;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* see what these funcions do on somewhere defined struct aw_spinand_cache */
|
||
|
|
struct aw_spinand_cache aw_spinand_cache = {
|
||
|
|
.match_cache = aw_spinand_cache_match_cache,
|
||
|
|
.copy_to_cache = aw_spinand_cache_copy_to_cache,
|
||
|
|
.copy_from_cache = aw_spinand_cache_copy_from_cache,
|
||
|
|
.read_from_cache = aw_spinand_cache_read_from_cache,
|
||
|
|
.write_to_cache = aw_spinand_cache_write_to_cache,
|
||
|
|
};
|
||
|
|
|
||
|
|
int aw_spinand_chip_cache_init(struct aw_spinand_chip *chip)
|
||
|
|
{
|
||
|
|
struct aw_spinand_info *info = chip->info;
|
||
|
|
struct aw_spinand_cache *cache = &aw_spinand_cache;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* this cache is only used for single physical page,
|
||
|
|
* no need to allocate super page for multiplane.
|
||
|
|
* If multiplane enabled, the read/write operation will be
|
||
|
|
* cut into 2 single page.
|
||
|
|
*/
|
||
|
|
cache->data_maxlen = info->phy_page_size(chip);
|
||
|
|
cache->oob_maxlen = info->phy_oob_size(chip);
|
||
|
|
cache->databuf = kzalloc(cache->data_maxlen + cache->oob_maxlen,
|
||
|
|
GFP_KERNEL);
|
||
|
|
if (!cache->databuf)
|
||
|
|
goto err;
|
||
|
|
|
||
|
|
cache->oobbuf = cache->databuf + cache->data_maxlen;
|
||
|
|
chip->cache = cache;
|
||
|
|
return 0;
|
||
|
|
err:
|
||
|
|
pr_err("init cache failed\n");
|
||
|
|
return -ENOMEM;
|
||
|
|
}
|
||
|
|
|
||
|
|
void aw_spinand_chip_cache_exit(struct aw_spinand_chip *chip)
|
||
|
|
{
|
||
|
|
struct aw_spinand_cache *cache = chip->cache;
|
||
|
|
|
||
|
|
kfree(cache->databuf);
|
||
|
|
cache->databuf = cache->oobbuf = NULL;
|
||
|
|
chip->cache = NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
MODULE_AUTHOR("liaoweixiong <liaoweixiong@allwinnertech.com>");
|
||
|
|
MODULE_DESCRIPTION("Commond physic layer for Allwinner's spinand driver");
|