164 lines
10 KiB
C
164 lines
10 KiB
C
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/*
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* SPDX-License-Identifier: GPL-2.0
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* Copyright (c) 2007-2017 Allwinnertech Co., Ltd.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include "nand_scan.h"
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#include "nand_physic_fun.h"
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#include "nand_type_spinand.h"
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struct spi_nand_function spi_nand_function0 = {
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m0_spi_nand_reset,
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m0_spi_nand_read_status,
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m0_spi_nand_setstatus,
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m0_spi_nand_getblocklock,
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m0_spi_nand_setblocklock,
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m0_spi_nand_getotp,
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m0_spi_nand_setotp,
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m0_spi_nand_getoutdriver,
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m0_spi_nand_setoutdriver,
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m0_erase_single_block,
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m0_write_single_page,
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m0_read_single_page,
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};
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struct spi_nand_function spi_nand_function1 = {
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m1_spi_nand_reset,
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m1_spi_nand_read_status,
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m1_spi_nand_setstatus,
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m1_spi_nand_getblocklock,
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m1_spi_nand_setblocklock,
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m1_spi_nand_getotp,
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m1_spi_nand_setotp,
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m1_spi_nand_getoutdriver,
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m1_spi_nand_setoutdriver,
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m1_erase_single_block,
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m1_write_single_page,
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m1_read_single_page,
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};
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struct spi_nand_function spi_nand_function2 = {
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m2_spi_nand_reset,
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m2_spi_nand_read_status,
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m2_spi_nand_setstatus,
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m2_spi_nand_getblocklock,
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m2_spi_nand_setblocklock,
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m2_spi_nand_getotp,
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m2_spi_nand_setotp,
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m2_spi_nand_getoutdriver,
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m2_spi_nand_setoutdriver,
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m2_erase_single_block,
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m2_write_single_page,
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m2_read_single_page,
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};
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struct spi_nand_function spi_nand_function3 = {
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m3_spi_nand_reset,
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m3_spi_nand_read_status,
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m3_spi_nand_setstatus,
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m3_spi_nand_getblocklock,
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m3_spi_nand_setblocklock,
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m3_spi_nand_getotp,
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m3_spi_nand_setotp,
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m3_spi_nand_getoutdriver,
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m3_spi_nand_setoutdriver,
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m3_erase_single_block,
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m3_write_single_page,
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m3_read_single_page,
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};
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//==============================================================================
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// define the physical architecture parameter for all kinds of nand flash
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//==============================================================================
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//==============================================================================
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//============================ GIGADEVICE & MIRA NAND FLASH ==============================
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//==============================================================================
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struct __NandPhyInfoPar_t GigaDeviceNandTbl[] = {
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// NAND_CHIP_ID DieCnt SecCnt PagCnt BlkCnt OpOpt Freq mode pagewithbadflag function offset maxerasetime maxecc ecclimit idnumber
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//------------------------------------------------------------------------------------------------------------------------
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//no support because of no testing
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//{ {0xc8, 0xf1, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 1024, 0x007d, 100, 0, 0, &spi_nand_function0 , 1, 50000, 8, 8, 0x000000},//GD5F1GQ4UAYIG
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//{ {0xc8, 0xf2, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 2048, 0x047d, 12, 0, 0, &spi_nand_function0 , 1, 50000, 8, 8, 0x000001},//GD5F2GQ4UAYIG
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//{ {0xc8, 0xf4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 4096, 0x007d, 100, 0, 0, &spi_nand_function0 , 1, 50000, 8, 8, 0x000002},//GD5F4GQ4UAYIG
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//{ {0xc8, 0xb4, 0x68, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 8, 64, 2048, 0x017d, 100, 0, 0, &spi_nand_function2 , 1, 50000, 8, 5, 0x000003},//GD5F4GQ4UCYIXX
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//{ {0xc8, 0x20, 0x7f, 0x7f, 0x7f, 0xff, 0xff, 0xff }, 1, 4, 64, 512, 0x007d, 100, 0, 1, &spi_nand_function3 , 1, 50000, 1, 1, 0x000004},//PSU12S20BN
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{ {0xc8, 0x52, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 2048, 0x0002D, 60, 0, 0, &spi_nand_function3, 1, 100000, 4, 1, 0x000000},//GD5F2GQ5UExxG
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{ {0xc8, 0xd1, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 1024, 0x006d, 60, 0, 0, &spi_nand_function0, 1, 50000, 8, 4, 0x000001},//GD5F1GQ4UBYIG, GD004 test ok on fpga
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{ {0xc8, 0x01, 0x7f, 0x7f, 0x7f, 0xff, 0xff, 0xff }, 1, 4, 64, 1024, 0x6c, 60, 0, 1, &spi_nand_function0, 1, 90000, 1, 1, 0x000002},//F50L1G41LB(2M)
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//------------------------------------------------------------------------------------------------------------------------
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{ {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 0, 0, 0, 0, 0x0000, 0, 0, 0, 0, 0}, // NULL
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};
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//==============================================================================
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//============================ ATO NAND FLASH ==============================
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//==============================================================================
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struct __NandPhyInfoPar_t AtoNandTbl[] = {
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// NAND_CHIP_ID DieCnt SecCnt PagCnt BlkCnt OpOpt Freq mode pagewithbadflag function offset maxerasetime maxecc ecclimit idnumber
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//------------------------------------------------------------------------------------------------------------------------
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//no support because of no testing
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//{ {0x9b, 0x12, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 1024, 0x007c, 100, 0, 0, &spi_nand_function0, 1, 100000, 0x010000 },//ATO25D1GA
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//------------------------------------------------------------------------------------------------------------------------
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{ {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 0, 0, 0, 0, 0x0000, 0, 0, 0, 0, 0}, // NULL
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};
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//==============================================================================
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//============================ Micron NAND FLASH ==============================
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//==============================================================================
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struct __NandPhyInfoPar_t MicronNandTbl[] = {
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// NAND_CHIP_ID DieCnt SecCnt PagCnt BlkCnt OpOpt Freq mode pagewithbadflag function offset maxerasetime maxecc ecclimit idnumber
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//------------------------------------------------------------------------------------------------------------------------
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//no support because of no testing
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//{ {0x2c, 0x12, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 1024, 0x00fd, 40, 0, 0, &spi_nand_function1, 1, 50000, 4, 1, 0x020000 },//MT29F1G01AAADD
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// { {0x2c, 0x22, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 2048, 0x00fd, 40, 0, 0, &spi_nand_function1, 1, 50000, 4, 1, 0x020001 },//MT29F2G01AAAED
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//{ {0x2c, 0x32, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 4096, 0x00fd, 40, 0, 0, &spi_nand_function1, 1, 50000, 4, 1, 0x020002 },//MT29F4G01AAADD
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//------------------------------------------------------------------------------------------------------------------------
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{ {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 0, 0, 0, 0, 0x0000, 0, 0, 0, 0, 0}, // NULL
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};
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//==============================================================================
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//============================ Mxic NAND FLASH ==============================
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//==============================================================================
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struct __NandPhyInfoPar_t MxicNandTbl[] = {
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// NAND_CHIP_ID DieCnt SecCnt PagCnt BlkCnt OpOpt Freq mode pagewithbadflag function offset maxerasetime maxecc ecclimit idnumber
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//------------------------------------------------------------------------------------------------------------------------
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{ {0xc2, 0x12, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 1024, 0x067c, 75, 0, 1, &spi_nand_function0, 1, 65000, 4, 1, 0x030000 },//MX35LF1GE4AB
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{ {0xc2, 0x22, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 2048, 0x06fc, 75, 0, 1, &spi_nand_function1, 1, 65000, 4, 1, 0x030001 },//MX35LF2GE4AB
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//------------------------------------------------------------------------------------------------------------------------
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{ {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 0, 0, 0, 0, 0x0000, 0, 0, 0, 0, 0}, // NULL
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};
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//==============================================================================
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//============================ Winbond NAND FLASH ==============================
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//==============================================================================
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struct __NandPhyInfoPar_t WinbondNandTbl[] = {
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// NAND_CHIP_ID DieCnt SecCnt PagCnt BlkCnt OpOpt Freq mode pagewithbadflag function offset maxerasetime maxecc ecclimit idnumber
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//------------------------------------------------------------------------------------------------------------------------
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//{ {0xef, 0xaa, 0x21, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64, 1024, 0x007d, 75, 0, 0, &spi_nand_function0, 1, 65000, 4, 1, 0x040000 },//W25N01GVSF1G
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//------------------------------------------------------------------------------------------------------------------------
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{ {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 0, 0, 0, 0, 0x0000, 0, 0, 0, 0, 0}, // NULL
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};
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//==============================================================================
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//============================= DEFAULT NAND FLASH =============================
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//==============================================================================
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struct __NandPhyInfoPar_t DefaultNandTbl[] = {
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// NAND_CHIP_ID DieCnt SecCnt PagCnt BlkCnt OpOpt Freq mode pagewithbadflag function offset maxerasetime maxecc ecclimit idnumber
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//-----------------------------------------------------------------------------------------------------------------------
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{ {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 0, 0, 0, 0, 0x0000, 0, 0, 0, NULL, 0, 0, 0x000000}, //default
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};
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