283 lines
13 KiB
C
283 lines
13 KiB
C
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/* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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*
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* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
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*the the People's Republic of China and other countries.
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* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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*
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* DISCLAIMER
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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* IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
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* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
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* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CLK_FACTORS_H__
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#define __CLK_FACTORS_H__
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#include "clk.h"
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struct sunxi_clk_factor_freq
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{
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u32 factor;
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u32 freq;
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};
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#define FACTOR_ALL(nv, ns, nw, kv, ks, kw, mv, ms, mw, \
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pv, ps, pw, d1v, d1s, d1w, d2v, d2s, d2w) \
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((((nv & ((1 << nw) - 1)) << ns) | \
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((kv & ((1 << kw) - 1)) << ks) | \
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((mv & ((1 << mw) - 1)) << ms) | \
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((pv & ((1 << pw) - 1)) << ps) | \
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((d1v & ((1 << d1w) - 1)) << d1s) | \
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((d2v & ((1 << d2w) - 1)) << d2s)))
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#define F_N8X8_P16x2(nv, pv) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, pv, 16, 2, 0, 0, 0, 0, 0, 0))
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#define F_N8X8_D1V1X1_D2V0X1(nv, d1v, d2v) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, d1v, 1, 1, d2v, 0, 1))
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#define F_N8X8_D1V1X1(nv, d1v) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, d1v, 1, 1, 0, 0, 0))
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#define F_N8X8_D1V4X2_D2V0X2(nv, d1v, d2v) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, d1v, 4, 2, d2v, 0, 2))
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#define F_N8X8_P16X6_D1V1X1_D2V0X1(nv, pv, d1v, d2v) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, pv, 16, 6, d1v, 1, 1, d2v, 0, 1))
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#define PLLCPU(n, p, freq) {F_N8X8_P16x2(n, p), freq}
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#define PLLDDR(n, d1, d2, freq) {F_N8X8_D1V1X1_D2V0X1(n, d1, d2), freq}
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#define PLLPERIPH0(n, d1, d2, freq) {F_N8X8_D1V1X1_D2V0X1(n, d1, d2), freq}
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#define PLLPERIPH1(n, d1, d2, freq) {F_N8X8_D1V1X1_D2V0X1(n, d1, d2), freq}
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#define PLLVIDEO0(n, d1, freq) {F_N8X8_D1V1X1(n, d1), freq}
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#define PLLAUDIO(n, p, d1, d2, freq) {F_N8X8_P16X6_D1V1X1_D2V0X1(n, p, d1, d2), freq}
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#define PLLCSI(n, d1, freq) {F_N8X8_D1V1X1(n, d1), freq}
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#define PLLNPU(n, d1, freq) {F_N8X8_D1V1X1(n, d1), freq}
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#define SUNXI_CLK_FACTORS_CONFIG(name, _nshift, _nwidth, _kshift, _kwidth, \
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_mshift, _mwidth, _pshift, _pwidth, _d1shift, _d1width, \
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_d2shift, _d2width, _frac, _outshift, _modeshift, \
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_enshift, _sdmshift, _sdmwidth, _sdmpat, _sdmval, \
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_mux_inshift, _out_enshift) \
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struct sunxi_clk_factors_config sunxi_clk_factor_config_##name = { \
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.nshift = _nshift, \
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.nwidth = _nwidth, \
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.kshift = _kshift, \
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.kwidth = _kwidth, \
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.mshift = _mshift, \
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.mwidth = _mwidth, \
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.pshift = _pshift, \
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.pwidth = _pwidth, \
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.d1shift = _d1shift, \
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.d1width = _d1width, \
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.d2shift = _d2shift, \
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.d2width = _d2width, \
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.frac = _frac, \
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.outshift = _outshift, \
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.modeshift = _modeshift, \
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.enshift = _enshift, \
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.sdmshift = _sdmshift, \
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.sdmwidth = _sdmwidth, \
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.sdmpat = _sdmpat, \
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.sdmval = _sdmval, \
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.updshift = 0, \
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.mux_inshift = _mux_inshift, \
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.out_enshift = _out_enshift, \
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}
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#define SUNXI_CLK_FACTORS_INIT(_name, _reg, _lock_reg, _lock_bit, _pll_lock_ctrl_reg, _lock_en_bit ) \
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struct factor_init_data sunxi_clk_factor_init_##_name = { \
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.reg =_reg, \
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.lock_reg = _lock_reg, \
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.pll_lock_ctrl_reg = _pll_lock_ctrl_reg, \
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.lock_bit = _lock_bit, \
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.lock_en_bit = _lock_en_bit, \
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.lock_mode = PLL_LOCK_NEW_MODE, \
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.config = &sunxi_clk_factor_config_##_name, \
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.get_factors = &get_factors_##_name, \
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.calc_rate = &calc_rate_##_name, \
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}
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#define SUNXI_CLK_FACTOR(_name, _clk, _current_parent, _current_parent_type, _clk_rate, _parent_rate ) \
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clk_factor_t sunxi_clk_factor_##_name = { \
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.clk_core = { \
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.clk = _clk, \
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.clk_type = HAL_CLK_FACTOR, \
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.current_parent = _current_parent, \
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.current_parent_type = _current_parent_type, \
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.clk_rate = _clk_rate, \
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.parent_rate = _parent_rate, \
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.clk_enbale = HAL_CLK_STATUS_DISABLED, \
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}, \
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.factor_data = &sunxi_clk_factor_init_##_name, \
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}
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/*no-change-from-linux*/
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typedef enum pll_lock_mode
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{
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PLL_LOCK_NEW_MODE = 0x0,
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PLL_LOCK_OLD_MODE,
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PLL_LOCK_NONE_MODE,
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PLL_LOCK_MODE_MAX,
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} pll_lock_mode_e;
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/**
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* struct clk_factors_value - factor value
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*
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* @factorn: factor-n value
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* @factork: factor-k value
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* @factorm: factor-m value
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* @factorp: factor-p value
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* @factord1: factor-d1 value
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* @factord2: factor-d2 value
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* @frac_mode: fraction mode value
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* @frac_freq: fraction frequnecy value
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*/
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/*no-change-from-linux*/
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struct clk_factors_value
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{
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u16 factorn;
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u16 factork;
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u16 factorm;
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u16 factorp;
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u16 factord1;
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u16 factord2;
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u16 frac_mode;
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u16 frac_freq;
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};
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/**
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* struct sunxi_clk_factors_config - factor config
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*
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* @nshift: shift to factor-n bit field
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* @nwidth: width of factor-n bit field
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* @kshift: shift to factor-k bit field
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* @kwidth: width of factor-k bit field
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* @mshift: shift to factor-m bit field
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* @mwidth: width of factor-m bit field
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* @pshift: shift to factor-p bit field
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* @pwidth: width of factor-p bit field
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* @d1shift: shift to factor-d1 bit field
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* @d1width: width of factor-d1 bit field
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* @d2shift: shift to factor-d2 bit field
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* @d2width: width of factor-d2 bit field
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* @frac: flag of fraction
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* @outshift: shift to frequency select bit field
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* @modeshift: shift to fraction/integer mode select
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* @enshift: shift to factor enable bit field
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* @lockshift: shift to factor lock status bit filed
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* @sdmshift: shift to factor sdm enable bit filed
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* @sdmwidth shift to factor sdm width bit filed
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* @sdmpat sdmpat reg address offset
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* @sdmval sdm default value
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* @updshift shift to update bit (especial for ddr/ddr0/ddr1)
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* @delay for flat factors delay.
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* @mux_inshift shift to multiplexer(multiple 24M source clocks) bit field
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* @out_enshift shift to enable pll clock output bit field
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*/
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/*no-change-from-linux*/
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struct sunxi_clk_factors_config
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{
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u8 nshift;
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u8 nwidth;
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u8 kshift;
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u8 kwidth;
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u8 mshift;
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u8 mwidth;
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u8 pshift;
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u8 pwidth;
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u8 d1shift;
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u8 d1width;
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u8 d2shift;
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u8 d2width;
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u8 frac;
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u8 outshift;
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u8 modeshift;
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u8 enshift;
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u8 lockshift;
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u8 sdmshift;
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u8 sdmwidth;
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volatile uint32_t *sdmpat;
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u32 sdmval;
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u32 updshift;
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u32 delay;
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u32 mux_inshift;
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u32 out_enshift;
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};
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/**
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* struct factor_init_data - factor init data
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*
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* @name: name of the clock
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* @parent_name:name of the parent
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* @num_parents:counter of the parents
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* @flags: factor optimal configurations
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* @reg: register address for the factor
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* @lock_reg: register address for check if the pll has locked
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* @lock_bit: bit offset of the lock_reg, to check if the the pll has locked
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* @pll_lock_ctrl_reg: pll lock control register, this function is first used on
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* the sun50i, to enable the function of pll hardlock
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* @lock_en_bit:bit offset of the pll_lock_ctrl_reg, to enable the function
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* @config: configuration of the factor
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* @get_factors:function for get factors parameter under a given frequency
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* @calc_rate: function for calculate the factor frequency
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* @priv_ops: private operations hook for the special factor
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* @priv_regops:register operation hook for read/write the register
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*
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*/
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struct factor_init_data
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{
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//const char *name;
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//const char **parent_names;
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//int num_parents;
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//unsigned long flags;
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volatile uint32_t *reg;
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volatile uint32_t *lock_reg;
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volatile uint32_t *pll_lock_ctrl_reg;
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u8 lock_bit;
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u8 lock_en_bit;
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pll_lock_mode_e lock_mode;
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struct sunxi_clk_factors_config *config;
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int (*get_factors)(u32 rate, u32 parent_rate, struct clk_factors_value *factor);
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int (*calc_rate)(u32 parent_rate, struct clk_factors_value *factor);
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//struct clk_ops *priv_ops;
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//struct sunxi_reg_ops *priv_regops;
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};
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hal_clk_status_t sunxi_clk_fators_enable(clk_factor_pt clk);
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hal_clk_status_t sunxi_clk_fators_disable(clk_factor_pt clk);
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hal_clk_status_t sunxi_clk_fators_is_enabled(clk_factor_pt clk);
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hal_clk_status_t sunxi_clk_factors_recalc_rate(clk_factor_pt clk, u32 *rate);
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hal_clk_status_t sunxi_clk_factors_set_rate(clk_factor_pt clk, u32 rate);
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u32 sunxi_clk_factors_round_rate(clk_factor_pt clk, u32 rate);
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int sunxi_clk_com_ftr_sr(struct sunxi_clk_factors_config *f_config,
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struct clk_factors_value *factor,
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struct sunxi_clk_factor_freq table[],
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unsigned long index, unsigned long tbl_count);
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#endif
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