221 lines
6.1 KiB
C
221 lines
6.1 KiB
C
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/*
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* (C) Copyright 2018
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* wangwei <wangwei@allwinnertech.com>
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*/
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#include <common.h>
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#include <private_boot0.h>
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#include <private_uboot.h>
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#include <private_toc.h>
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#include <private_tee.h>
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#include <arch/clock.h>
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#include <arch/uart.h>
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#include <arch/dram.h>
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#include <arch/rtc.h>
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#include <arch/gpio.h>
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#include <board_helper.h>
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#include <config.h>
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#include <boot_param.h>
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__u8 uboot_backup;
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static void update_uboot_info(phys_addr_t uboot_base, phys_addr_t optee_base,
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phys_addr_t monitor_base, phys_addr_t rtos_base, u32 dram_size,
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u16 pmu_type, u16 uart_input, u16 key_input);
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static int boot0_clear_env(void);
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__maybe_unused int load_kernel_from_spinor(u32 *);
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__maybe_unused void startup_kernel(u32, u32);
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static void print_commit_log(void)
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{
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printf("HELLO! BOOT0 is starting!\n");
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printf("BOOT0 commit : %s\n", BT0_head.hash);
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sunxi_set_printf_debug_mode(BT0_head.prvt_head.debug_mode, 0);
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}
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void main(void)
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{
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int dram_size;
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int status;
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phys_addr_t uboot_base = 0, optee_base = 0, monitor_base = 0, \
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rtos_base = 0, opensbi_base = 0, cpus_rtos_base = 0;
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u16 pmu_type = 0, key_input = 0; /* TODO: set real value */
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sunxi_board_init_early();
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sunxi_serial_init(BT0_head.prvt_head.uart_port, (void *)BT0_head.prvt_head.uart_ctrl, 6);
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print_commit_log();
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status = sunxi_board_init();
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if (status)
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goto _BOOT_ERROR;
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if (rtc_probe_fel_flag()) {
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rtc_clear_fel_flag();
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goto _BOOT_ERROR;
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#ifdef CFG_SUNXI_PHY_KEY
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#ifdef CFG_LRADC_KEY
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} else if (check_update_key(&key_input)) {
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goto _BOOT_ERROR;
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#endif
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#endif
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}
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if (BT0_head.prvt_head.enable_jtag) {
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printf("enable_jtag\n");
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boot_set_gpio((normal_gpio_cfg *)BT0_head.prvt_head.jtag_gpio, 5, 1);
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}
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char uart_input_value = get_uart_input(); /* Prevent DRAM jamming */
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if (uart_input_value == '2') {
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printf("detected_f user input 2\n");
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goto _BOOT_ERROR;
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}
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sunxi_bootparam_load();
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#ifdef FPGA_PLATFORM
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dram_size = sunxi_fpga_dram_init((void *)sunxi_bootparam_get_dram_buf());
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#else
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dram_size = init_DRAM(0, (void *)sunxi_bootparam_get_dram_buf());
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#endif
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if (!dram_size) {
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printf("init dram fail\n");
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goto _BOOT_ERROR;
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} else {
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if (BT0_head.dram_size > 0)
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dram_size = BT0_head.dram_size;
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printf("dram size =%d\n", dram_size);
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}
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#ifdef CFG_SUNXI_STANDBY_WORKAROUND
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handler_super_standby();
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#endif
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uart_input_value = get_uart_input();
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if (uart_input_value == '2') {
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sunxi_set_printf_debug_mode(3, 0);
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printf("detected_r user input 2\n");
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goto _BOOT_ERROR;
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} else if (uart_input_value == 'd') {
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sunxi_set_printf_debug_mode(8, 1);
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printf("detected user input d\n");
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} else if (uart_input_value == 'q') {
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printf("detected user input q\n");
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sunxi_set_printf_debug_mode(0, 1);
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}
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mmu_enable(dram_size);
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malloc_init(CONFIG_HEAP_BASE, CONFIG_HEAP_SIZE);
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status = sunxi_board_late_init();
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if (status)
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goto _BOOT_ERROR;
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status = load_package();
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if (status == 0)
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load_image(&uboot_base, &optee_base, &monitor_base, &rtos_base, &opensbi_base, &cpus_rtos_base);
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else
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goto _BOOT_ERROR;
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#if defined(CFG_RISCV_E907) || defined(CFG_RISCV_E906) || defined(CFG_RISCV_C906)
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#ifdef CFG_SUNXI_FDT
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extern void boot_riscv(phys_addr_t base, unsigned long fdt_addr);
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if (cpus_rtos_base != 0)
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boot_riscv(cpus_rtos_base, (unsigned long)working_fdt);
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#endif
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#endif
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update_uboot_info(uboot_base, optee_base, monitor_base, rtos_base, dram_size,
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pmu_type, uart_input_value, key_input);
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#if CFG_BOOT0_LOAD_KERNEL
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exist_uboot_jmp_cardproduct(uboot_base);
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void load_and_run_kernel(u32 optee_base, u32 opensbi_base, u32 monitor_base);
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load_and_run_kernel(optee_base, opensbi_base, monitor_base);
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//already jump to kernel, should never return, if so, go FEL
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goto _BOOT_ERROR;
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#endif
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mmu_disable();
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printf("Jump to second Boot.\n");
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if (opensbi_base) {
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boot0_jmp_opensbi(opensbi_base, uboot_base);
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} else if (monitor_base) {
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struct spare_monitor_head *monitor_head =
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(struct spare_monitor_head *)((phys_addr_t)monitor_base);
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monitor_head->secureos_base = optee_base;
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monitor_head->nboot_base = uboot_base;
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boot0_jmp_monitor(monitor_base);
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} else if (optee_base)
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boot0_jmp_optee(optee_base, uboot_base);
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else if (rtos_base) {
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printf("jump to rtos\n");
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boot0_jmp(rtos_base);
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}
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else
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boot0_jmp(uboot_base);
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while(1);
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_BOOT_ERROR:
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boot0_clear_env();
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boot0_jmp(FEL_BASE);
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}
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static void update_uboot_info(phys_addr_t uboot_base, phys_addr_t optee_base,
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phys_addr_t monitor_base, phys_addr_t rtos_base, u32 dram_size,
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u16 pmu_type, u16 uart_input, u16 key_input)
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{
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if (rtos_base)
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return;
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uboot_head_t *header = (uboot_head_t *) uboot_base;
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struct sbrom_toc1_head_info *toc1_head = (struct sbrom_toc1_head_info *)CONFIG_BOOTPKG_BASE;
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if (uboot_base) {
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#ifdef CFG_SUNXI_BOOT_PARAM
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sunxi_bootparam_format_and_transfer(
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(void *)(uboot_base + SUNXI_BOOTPARAM_OFFSET));
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#endif
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header->boot_data.boot_package_size = toc1_head->valid_len;
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header->boot_data.dram_scan_size = dram_size;
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memcpy((void *)header->boot_data.dram_para,
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(void *)sunxi_bootparam_get_dram_buf(), 32 * sizeof(int));
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if (monitor_base)
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header->boot_data.monitor_exist = 1;
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if (optee_base) {
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struct spare_optee_head *tee_head =
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(struct spare_optee_head *)optee_base;
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header->boot_data.secureos_exist = 1;
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tee_head->dram_size = dram_size;
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tee_head->drm_size = BT0_head.secure_dram_mbytes;
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tee_head->uart_port = BT0_head.prvt_head.uart_port;
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}
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#ifndef CONFIG_RISCV
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header->boot_data.func_mask |= get_uboot_func_mask(UBOOT_FUNC_MASK_ALL);
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#endif
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update_flash_para(uboot_base);
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header->boot_data.uart_port = BT0_head.prvt_head.uart_port;
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memcpy((void *)header->boot_data.uart_gpio, BT0_head.prvt_head.uart_ctrl, 2*sizeof(normal_gpio_cfg));
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header->boot_data.pmu_type = pmu_type;
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header->boot_data.uart_input = uart_input;
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header->boot_data.key_input = key_input;
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header->boot_data.debug_mode = sunxi_get_debug_mode_for_uboot();
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if (get_card_work_mode() != NOUSE_CARDMODE)
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header->boot_data.work_mode = get_card_work_mode();
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header->boot_data.uboot_backup = uboot_backup;
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}
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}
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static int boot0_clear_env(void)
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{
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sunxi_board_exit();
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sunxi_board_clock_reset();
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mmu_disable();
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mdelay(10);
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return 0;
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}
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