192 lines
4.9 KiB
ArmAsm
192 lines
4.9 KiB
ArmAsm
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/*
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* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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*
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* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
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* the the People's Republic of China and other countries.
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* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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*
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* DISCLAIMER
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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* IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
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* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
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* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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.section .text.entry, "ax", @progbits
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.align 8
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.option norvc
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.global handle_exception
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handle_exception:
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# save interrupted context to current thread stack
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addi sp, sp, -34 * 4
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sw x1, 1 * 4(sp)
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sw x3, 3 * 4(sp)
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sw x4, 4 * 4(sp)
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sw x5, 5 * 4(sp)
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sw x6, 6 * 4(sp)
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sw x7, 7 * 4(sp)
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sw x8, 8 * 4(sp)
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sw x9, 9 * 4(sp)
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sw x10, 10 * 4(sp)
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sw x11, 11 * 4(sp)
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sw x12, 12 * 4(sp)
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sw x13, 13 * 4(sp)
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sw x14, 14 * 4(sp)
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sw x15, 15 * 4(sp)
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sw x16, 16 * 4(sp)
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sw x17, 17 * 4(sp)
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sw x18, 18 * 4(sp)
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sw x19, 19 * 4(sp)
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sw x20, 20 * 4(sp)
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sw x21, 21 * 4(sp)
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sw x22, 22 * 4(sp)
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sw x23, 23 * 4(sp)
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sw x24, 24 * 4(sp)
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sw x25, 25 * 4(sp)
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sw x26, 26 * 4(sp)
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sw x27, 27 * 4(sp)
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sw x28, 28 * 4(sp)
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sw x29, 29 * 4(sp)
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sw x30, 30 * 4(sp)
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sw x31, 31 * 4(sp)
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csrr a0, mepc
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sw a0, 0 * 4(sp)
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csrr a1, mstatus
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sw a1, 32 * 4(sp)
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csrr a2, mscratch
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sw a2, 33 * 4(sp)
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# backup stack pointer for later check.
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move s0, sp
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move a0, sp
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addi a0, a0, 34 * 4
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sw a0, 2 * 4(sp)
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csrr a0, mstatus
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call fpu_save_inirq
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#re-backup the sstatus in chance clean the fpustatus.
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csrr s1, mstatus
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sw s1, 32 * 4(s0)
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# check bit[63], 0:interrupt, 1:exceptions
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csrr a0, mcause
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bge a0, zero, .exception
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.interrupt:
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# handle interrupts.
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call hal_interrupt_enter
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csrr a0, mcause
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csrr a1, mepc
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csrr a2, mtval
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move a3, s0
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call riscv_cpu_handle_interrupt
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call hal_interrupt_leave
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j .restore_all
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.exception:
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# handle syscall and exceptions.
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csrr a0, mcause
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csrr a1, mepc
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csrr a2, mtval
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move a3, s0
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call riscv_cpu_handle_exception
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nop
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.restore_all:
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csrr a0, sstatus
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call fpu_restore_inirq
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# guanatee SPP bit was set, means we are from supervisor mode.
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csrr a0, sstatus
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ori a0, a0, 0x100
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csrw sstatus, a0
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# keep sstatus not change inirq.
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0:
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bne a0, s1, 0b
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# keep stack balance.
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1:
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bne sp, s0, 1b
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#.option push
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#.option norelax
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# la a0, __global_pointer$
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#.option pop
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.gplwr:
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auipc a0, %pcrel_hi(__global_pointer$)
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addi a0, a0,%pcrel_lo(.gplwr)
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2: # x3 is gp in abi
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bne gp, a0,2b
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jal schedule_preempt_inirq
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# resotre interrupted context
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lw a0, 0 * 4(sp)
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csrw sepc, a0
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lw x1, 1 * 4(sp)
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lw a0, 32 * 4(sp)
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csrw sstatus, a0
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lw a0, 33 * 4(sp)
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csrw sscratch, a0
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lw x3, 3 * 4(sp)
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lw x4, 4 * 4(sp)
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lw x5, 5 * 4(sp)
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lw x6, 6 * 4(sp)
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lw x7, 7 * 4(sp)
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lw x8, 8 * 4(sp)
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lw x9, 9 * 4(sp)
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lw x10, 10 * 4(sp)
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lw x11, 11 * 4(sp)
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lw x12, 12 * 4(sp)
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lw x13, 13 * 4(sp)
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lw x14, 14 * 4(sp)
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lw x15, 15 * 4(sp)
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lw x16, 16 * 4(sp)
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lw x17, 17 * 4(sp)
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lw x18, 18 * 4(sp)
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lw x19, 19 * 4(sp)
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lw x20, 20 * 4(sp)
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lw x21, 21 * 4(sp)
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lw x22, 22 * 4(sp)
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lw x23, 23 * 4(sp)
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lw x24, 24 * 4(sp)
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lw x25, 25 * 4(sp)
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lw x26, 26 * 4(sp)
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lw x27, 27 * 4(sp)
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lw x28, 28 * 4(sp)
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lw x29, 29 * 4(sp)
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lw x30, 30 * 4(sp)
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lw x31, 31 * 4(sp)
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addi sp, sp, 34 * 4
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sret
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.end
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