445 lines
11 KiB
C
445 lines
11 KiB
C
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/*
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* drivers/usb/sunxi_usb/usbc/usbc_phy.c
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* (C) Copyright 2010-2015
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* daniel, 2009.10.21
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*
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* usb common ops.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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*/
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#include "usbc_i.h"
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#include "linux/sunxi-sid.h"
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/**
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* define USB PHY controller reg bit
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*/
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/* Common Control Bits for Both PHYs */
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#define USBC_PHY_PLL_BW 0x03
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#define USBC_PHY_RES45_CAL_EN 0x0c
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/* Private Control Bits for Each PHY */
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#define USBC_PHY_TX_AMPLITUDE_TUNE 0x20
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#define USBC_PHY_TX_SLEWRATE_TUNE 0x22
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#define USBC_PHY_VBUSVALID_TH_SEL 0x25
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#define USBC_PHY_PULLUP_RES_SEL 0x27
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#define USBC_PHY_OTG_FUNC_EN 0x28
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#define USBC_PHY_VBUS_DET_EN 0x29
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#define USBC_PHY_DISCON_TH_SEL 0x2a
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/* usb PHY common set, initialize */
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void USBC_PHY_SetCommonConfig(void)
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{
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}
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/**
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* usb PHY specific set
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* @hUSB: handle returned by USBC_open_otg,
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* include some key data that the USBC need.
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*
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*/
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void USBC_PHY_SetPrivateConfig(__hdle hUSB)
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{
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}
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/**
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* get PHY's common setting. for debug, to see if PHY is set correctly.
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*
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* return the 32bit usb PHY common setting value.
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*/
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__u32 USBC_PHY_GetCommonConfig(void)
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{
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__u32 reg_val = 0;
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return reg_val;
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}
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/**
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* write usb PHY0's phy reg setting. mainly for phy0 standby.
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*
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* return the data wrote
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*/
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static __u32 usb_phy0_write(__u32 addr,
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__u32 data, __u32 dmask, void __iomem *usbc_base_addr)
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{
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__u32 i = 0;
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data = data & 0x0f;
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addr = addr & 0x0f;
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dmask = dmask & 0x0f;
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USBC_Writeb((dmask<<4)|data, usbc_base_addr + 0x404 + 2);
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USBC_Writeb(addr|0x10, usbc_base_addr + 0x404);
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for (i = 0; i < 5 ; i++)
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;
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USBC_Writeb(addr|0x30, usbc_base_addr + 0x404);
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for (i = 0 ; i < 5 ; i++)
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;
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USBC_Writeb(addr|0x10, usbc_base_addr + 0x404);
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for (i = 0 ; i < 5 ; i++)
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;
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return (USBC_Readb(usbc_base_addr + 0x404 + 3) & 0x0f);
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}
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/**
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* Standby the usb phy with the input usb phy index number
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* @phy_index: usb phy index number, which used to select the phy to standby
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*
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*/
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void USBC_phy_Standby(__hdle hUSB, __u32 phy_index)
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{
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__usbc_otg_t *usbc_otg = (__usbc_otg_t *)hUSB;
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if (phy_index == 0) {
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usb_phy0_write(0xB, 0x8, 0xf, usbc_otg->base_addr);
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usb_phy0_write(0x7, 0xf, 0xf, usbc_otg->base_addr);
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usb_phy0_write(0x1, 0xf, 0xf, usbc_otg->base_addr);
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usb_phy0_write(0x2, 0xf, 0xf, usbc_otg->base_addr);
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}
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}
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/**
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* Recover the standby phy with the input index number
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* @phy_index: usb phy index number
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*
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*/
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void USBC_Phy_Standby_Recover(__hdle hUSB, __u32 phy_index)
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{
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__u32 i;
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if (phy_index == 0) {
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for (i = 0; i < 0x10; i++)
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;
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}
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}
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static __u32 USBC_Phy_TpWrite(__u32 usbc_no, __u32 addr, __u32 data, __u32 len)
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{
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void __iomem *otgc_base = NULL;
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void __iomem *phyctl_val = NULL;
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__u32 temp = 0, dtmp = 0;
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__u32 j = 0;
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otgc_base = get_otgc_vbase();
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if (otgc_base == NULL)
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return 0;
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phyctl_val = otgc_base + USBPHYC_REG_o_PHYCTL;
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dtmp = data;
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for (j = 0; j < len; j++) {
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/* set the bit address to be write */
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temp = USBC_Readl(phyctl_val);
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temp &= ~(0xff << 8);
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temp |= ((addr + j) << 8);
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USBC_Writel(temp, phyctl_val);
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temp = USBC_Readb(phyctl_val);
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temp &= ~(0x1 << 7);
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temp |= (dtmp & 0x1) << 7;
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temp &= ~(0x1 << (usbc_no << 1));
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USBC_Writeb(temp, phyctl_val);
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temp = USBC_Readb(phyctl_val);
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temp |= (0x1 << (usbc_no << 1));
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USBC_Writeb(temp, phyctl_val);
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temp = USBC_Readb(phyctl_val);
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temp &= ~(0x1 << (usbc_no << 1));
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USBC_Writeb(temp, phyctl_val);
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dtmp >>= 1;
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}
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return data;
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}
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static __u32 USBC_Phy_Write(__u32 usbc_no, __u32 addr, __u32 data, __u32 len)
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{
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return USBC_Phy_TpWrite(usbc_no, addr, data, len);
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}
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void UsbPhyCtl(void __iomem *regs)
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{
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__u32 reg_val = 0;
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reg_val = USBC_Readl(regs + USBPHYC_REG_o_PHYCTL);
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reg_val |= (0x01 << USBC_PHY_CTL_VBUSVLDEXT);
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USBC_Writel(reg_val, (regs + USBPHYC_REG_o_PHYCTL));
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}
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void USBC_PHY_Set_Ctl(void __iomem *regs, __u32 mask)
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{
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__u32 reg_val = 0;
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reg_val = USBC_Readl(regs + USBPHYC_REG_o_PHYCTL);
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reg_val |= (0x01 << mask);
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USBC_Writel(reg_val, (regs + USBPHYC_REG_o_PHYCTL));
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}
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void USBC_PHY_Clear_Ctl(void __iomem *regs, __u32 mask)
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{
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__u32 reg_val = 0;
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reg_val = USBC_Readl(regs + USBPHYC_REG_o_PHYCTL);
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reg_val &= ~(0x01 << mask);
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USBC_Writel(reg_val, (regs + USBPHYC_REG_o_PHYCTL));
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}
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void UsbPhyInit(__u32 usbc_no)
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{
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/* adjust the 45 ohm resistor */
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if (usbc_no == 0)
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USBC_Phy_Write(usbc_no, 0x0c, 0x01, 1);
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/* adjust USB0 PHY range and rate */
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USBC_Phy_Write(usbc_no, 0x20, 0x14, 5);
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/* adjust disconnect threshold */
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USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
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/* by wangjx */
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}
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void UsbPhyEndReset(__u32 usbc_no)
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{
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int i;
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if (usbc_no == 0) {
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/**
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* Disable Sequelch Detect for a while
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* before Release USB Reset.
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*/
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USBC_Phy_Write(usbc_no, 0x3c, 0x2, 2);
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for (i = 0; i < 0x100; i++)
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;
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USBC_Phy_Write(usbc_no, 0x3c, 0x0, 2);
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}
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}
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void usb_otg_phy_txtune(void __iomem *regs)
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{
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__u32 reg_val = 0;
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reg_val = USBC_Readl(regs + USBC_REG_o_PHYTUNE);
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#if defined(CONFIG_ARCH_SUN8IW18)
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reg_val |= (0x01 << 1);
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#else
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reg_val |= 0x03 << 2; /* TXRESTUNE */
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#endif
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reg_val &= ~(0xf << 8);
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reg_val |= 0xc << 8; /* TXVREFTUNE */
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USBC_Writel(reg_val, (regs + USBC_REG_o_PHYTUNE));
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}
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#if defined(CONFIG_ARCH_SUN8IW21)
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/*for new phy*/
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static int usbc_new_phyx_tp_write(void __iomem *regs,
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int addr, int data, int len)
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{
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int temp = 0;
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int j = 0;
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int dtmp = 0;
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/*device: 0x410(phy_ctl)*/
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dtmp = data;
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for (j = 0; j < len; j++) {
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temp = USBC_Readb(regs + USBPHYC_REG_o_PHYCTL);
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temp |= (0x1 << 1);
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USBC_Writeb(temp, regs + USBPHYC_REG_o_PHYCTL);
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USBC_Writeb(addr + j, regs + USBPHYC_REG_o_PHYCTL + 1);
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temp = USBC_Readb(regs + USBPHYC_REG_o_PHYCTL);
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temp &= ~(0x1 << 0);
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USBC_Writeb(temp, regs + USBPHYC_REG_o_PHYCTL);
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temp = USBC_Readb(regs + USBPHYC_REG_o_PHYCTL);
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temp &= ~(0x1 << 7);
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temp |= (dtmp & 0x1) << 7;
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USBC_Writeb(temp, regs + USBPHYC_REG_o_PHYCTL);
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temp |= (0x1 << 0);
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USBC_Writeb(temp, regs + USBPHYC_REG_o_PHYCTL);
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temp &= ~(0x1 << 0);
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USBC_Writeb(temp, regs + USBPHYC_REG_o_PHYCTL);
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temp = USBC_Readb(regs + USBPHYC_REG_o_PHYCTL);
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temp &= ~(0x1 << 1);
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USBC_Writeb(temp, regs + USBPHYC_REG_o_PHYCTL);
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dtmp >>= 1;
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}
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return 0;
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}
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static int usbc_new_phyx_tp_read(void __iomem *regs, int addr, int len)
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{
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int temp = 0;
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int i = 0;
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int j = 0;
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int ret = 0;
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temp = USBC_Readb(regs + USBPHYC_REG_o_PHYCTL);
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temp |= (0x1 << 1);
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USBC_Writeb(temp, regs + USBPHYC_REG_o_PHYCTL);
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for (j = len; j > 0; j--) {
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USBC_Writeb((addr + j - 1), regs + USBPHYC_REG_o_PHYCTL + 1);
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for (i = 0; i < 0x4; i++)
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;
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temp = USBC_Readb(regs + USBC_REG_o_PHYSTATUS);
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ret <<= 1;
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ret |= (temp & 0x1);
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}
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temp = USBC_Readb(regs + USBPHYC_REG_o_PHYCTL);
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temp &= ~(0x1 << 1);
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USBC_Writeb(temp, regs + USBPHYC_REG_o_PHYCTL);
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return ret;
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}
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void usbc_new_phyx_write(void __iomem *regs, u32 data)
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{
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u32 temp = 0, ptmp = 0, rtmp = 0;
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temp = data & PHY_RANGE_TRAN_MASK;
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temp >>= (2 + 4);
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ptmp = data & PHY_RANGE_PREE_MASK;
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ptmp >>= 4;
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rtmp = data & PHY_RANGE_RESI_MASK;
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/* tranceive data */
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usbc_new_phyx_tp_write(regs, 0x60, temp, 0x4);
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DMSG_INFO("write to trancevie data: 0x%x\n", temp);
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usbc_new_phyx_tp_write(regs, 0x64, ptmp, 0x2);
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DMSG_INFO("write to preemphasis data: 0x%x\n", ptmp);
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usbc_new_phyx_tp_write(regs, 0x43, 0x0, 0x1);
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usbc_new_phyx_tp_write(regs, 0x41, 0x0, 0x1);
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usbc_new_phyx_tp_write(regs, 0x40, 0x0, 0x1);
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usbc_new_phyx_tp_write(regs, 0x44, rtmp, 0x4);
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DMSG_INFO("write to resistance data: 0x%x\n", rtmp);
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usbc_new_phyx_tp_write(regs, 0x43, 0x1, 0x1);
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}
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u32 usbc_new_phyx_read(void __iomem *regs)
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{
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u32 temp = 0, ptmp = 0, rtmp = 0, ret = 0;
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temp = usbc_new_phyx_tp_read(regs, 0x60, 0x4);
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ptmp = usbc_new_phyx_tp_read(regs, 0x64, 0x2);
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rtmp = usbc_new_phyx_tp_read(regs, 0x44, 0x4);
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DMSG_INFO("trancevie[9:6]:0x%x, preemphasis[5:4]:0x%x, resistance[3:0]:0x%x\n",
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temp, ptmp, rtmp);
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temp <<= (2 + 4);
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ptmp <<= 4;
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ret = temp | ptmp | rtmp;
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
void usbc_new_phy_init(void __iomem *regs)
|
||
|
|
{
|
||
|
|
int value = 0;
|
||
|
|
u32 efuse_val = 0;
|
||
|
|
|
||
|
|
pr_debug("addr:%x,len:%x,value:%x\n", 0x03, 0x06,
|
||
|
|
usbc_new_phyx_tp_read(regs, 0x03, 0x06));
|
||
|
|
pr_debug("addr:%x,len:%x,value:%x\n", 0x16, 0x03,
|
||
|
|
usbc_new_phyx_tp_read(regs, 0x16, 0x03));
|
||
|
|
pr_debug("addr:%x,len:%x,value:%x\n", 0x0b, 0x08,
|
||
|
|
usbc_new_phyx_tp_read(regs, 0x0b, 0x08));
|
||
|
|
pr_debug("addr:%x,len:%x,value:%x\n", 0x09, 0x03,
|
||
|
|
usbc_new_phyx_tp_read(regs, 0x09, 0x03));
|
||
|
|
|
||
|
|
sunxi_get_module_param_from_sid(&efuse_val, EFUSE_OFFSET, 4);
|
||
|
|
pr_debug("efuse_val:0x%x\n", efuse_val);
|
||
|
|
|
||
|
|
usbc_new_phyx_tp_write(regs, 0x03, 0x3f, 0x06);
|
||
|
|
pr_debug("addr:%x,len:%x,value:%x\n", 0x03, 0x3f,
|
||
|
|
usbc_new_phyx_tp_read(regs, 0x03, 0x06));
|
||
|
|
|
||
|
|
usbc_new_phyx_tp_write(regs, 0x1c, 0x03, 0x03);
|
||
|
|
pr_debug("addr:%x,len:%x,value:%x\n", 0x1c, 0x03,
|
||
|
|
usbc_new_phyx_tp_read(regs, 0x1c, 0x03));
|
||
|
|
|
||
|
|
if (efuse_val & SUNXI_USB_PHY_EFUSE_ADJUST) {
|
||
|
|
/* Already calibrate completely, don't have to distinguish iref mode and vref mode */
|
||
|
|
pr_debug("USB phy already calibrate completely\n");
|
||
|
|
|
||
|
|
/* usbc-0 */
|
||
|
|
value = (efuse_val & SUNXI_USB_PHY_EFUSE_USB0TX) >> 9;
|
||
|
|
usbc_new_phyx_tp_write(regs, 0x60, value, 0x04);
|
||
|
|
|
||
|
|
value = (efuse_val & SUNXI_USB_PHY_EFUSE_RES) >> 5;
|
||
|
|
usbc_new_phyx_tp_write(regs, 0x44, value, 0x04);
|
||
|
|
|
||
|
|
pr_debug("addr:%x,len:%x,value:%x\n", 0x60, 0x04,
|
||
|
|
usbc_new_phyx_tp_read(regs, 0x60, 0x04));
|
||
|
|
pr_debug("addr:%x,len:%x,value:%x\n", 0x44, 0x04,
|
||
|
|
usbc_new_phyx_tp_read(regs, 0x44, 0x04));
|
||
|
|
} else {
|
||
|
|
pr_debug("USB phy don't calibrate\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
pr_debug("addr:%x,len:%x,value:%x\n", 0x03, 0x06,
|
||
|
|
usbc_new_phyx_tp_read(regs, 0x03, 0x06));
|
||
|
|
pr_debug("addr:%x,len:%x,value:%x\n", 0x16, 0x03,
|
||
|
|
usbc_new_phyx_tp_read(regs, 0x16, 0x03));
|
||
|
|
pr_debug("addr:%x,len:%x,value:%x\n", 0x0b, 0x08,
|
||
|
|
usbc_new_phyx_tp_read(regs, 0x0b, 0x08));
|
||
|
|
pr_debug("addr:%x,len:%x,value:%x\n", 0x09, 0x03,
|
||
|
|
usbc_new_phyx_tp_read(regs, 0x09, 0x03));
|
||
|
|
}
|
||
|
|
|
||
|
|
void usbc_new_phy_res_cal(void __iomem *regs)
|
||
|
|
{
|
||
|
|
int value;
|
||
|
|
|
||
|
|
/*clear software res cail*/
|
||
|
|
usbc_new_phyx_tp_write(regs, 0x43, 0x0, 0x01);
|
||
|
|
usbc_new_phyx_tp_write(regs, 0x41, 0x0, 0x01);
|
||
|
|
usbc_new_phyx_tp_write(regs, 0x40, 0x0, 0x01);
|
||
|
|
/*res cail*/
|
||
|
|
usbc_new_phyx_tp_write(regs, 0x40, 0x01, 0x01);
|
||
|
|
mdelay(1);
|
||
|
|
usbc_new_phyx_tp_write(regs, 0x41, 0x01, 0x01);
|
||
|
|
|
||
|
|
while (1) {
|
||
|
|
if (usbc_new_phyx_tp_read(regs, 0x42, 0x01))
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*set res*/
|
||
|
|
value = usbc_new_phyx_tp_read(regs, 0x49, 0x04);
|
||
|
|
pr_debug("addr:%x,,value:%x\n", 0x49, value);
|
||
|
|
usbc_new_phyx_tp_write(regs, 0x44, value, 0x04);
|
||
|
|
usbc_new_phyx_tp_write(regs, 0x41, 0x0, 0x01);
|
||
|
|
usbc_new_phyx_tp_write(regs, 0x40, 0x0, 0x01);
|
||
|
|
usbc_new_phyx_tp_write(regs, 0x43, 0x01, 0x01);
|
||
|
|
}
|
||
|
|
#endif
|