451 lines
12 KiB
Plaintext
451 lines
12 KiB
Plaintext
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/*
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* Allwinner Technology CO., Ltd. sun8iw20p1 platform
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*
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* modify base on juno.dts
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "sun8iw20p1-clk.dtsi"
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/*#include "sun8iw20p1-pinctrl.dtsi"*/
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#include <dt-bindings/thermal/thermal.h>
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/ {
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model = "sun8iw20";
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compatible = "allwinner,r528", "arm,sun8iw20p1";
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#address-cells = <2>;
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#size-cells = <2>;
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soc: soc@29000000 {
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#address-cells = <2>;
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#size-cells = <2>;
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power_sply:power_sply@4500000c {
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device_type = "power_sply";
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};
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power_delay:power_delay@4500024 {
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device_type = "power_delay";
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};
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platform:platform@45000004 {
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device_type = "platform";
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};
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target:target@45000008 {
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device_type = "target";
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};
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charger0:charger0@45000010 {
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device_type = "charger0";
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};
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card_boot:card_boot@45000014 {
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device_type = "card_boot";
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logical_start = <40960>;
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/* sprite_gpio0 = <&pio PH 6 1 0xffffffff 0xffffffff 1>; */
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sprite_gpio0 = <&pio 0x7 0x6 0x1 0xffffffff 0xffffffff 0x1>;
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};
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gpio_bias:gpio_bias@45000018 {
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device_type = "gpio_bias";
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};
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fastboot_key:fastboot_key@4500001c {
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device_type = "fastboot_key";
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key_max = <42>;
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key_min = <38>;
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};
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recovery_key:recovery_key@45000020 {
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device_type = "recovery_key";
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key_max = <31>;
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key_min = <28>;
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};
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pio: pinctrl@0300b000 {
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compatible = "allwinner,sun8iw20p1-pinctrl";
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device_type = "pio";
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gpio-controller;
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#size-cells = <0>;
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#gpio-cells = <6>;
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/* takes the debounce time in usec as argument */
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input-debounce = <0 0 0 0 0 0 0 0 0>;
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r_pio: pinctrl@07022000 {
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s_twi0_pins_a: s_twi0@0 {
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allwinner,pins = "PL0", "PL1";
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allwinner,pname = "s_twi0_scl", "s_twi0_sda";
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allwinner,function = "s_twi0";
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allwinner,muxsel = <2>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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s_twi0_pins_b: s_twi0@1 {
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allwinner,pins = "PL0", "PL1";
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allwinner,function = "io_disabled";
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allwinner,muxsel = <7>;
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allwinner,drive = <1>;
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allwinner,pull = <0>;
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};
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};
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sdc0_pins_a: sdc0@0 {
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};
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sdc0_pins_b: sdc0@1 {
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};
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sdc0_pins_c: sdc0@2 {
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};
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sdc2_pins_a: sdc2@0 {
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};
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sdc2_pins_b: sdc2@1 {
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};
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sdc2_pins_c: sdc2@2 {
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};
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nand0_pins_a: nand0@0 {
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};
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nand0_pins_b: nand0@1 {
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};
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nand0_pins_c: nand0@2 {
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};
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spi0_pins_a: spi0@0 {
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};
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spi0_pins_b: spi0@1 {
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};
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spi0_pins_c: spi0@2 {
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};
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spi1_pins_a: spi1@0 {
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};
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spi1_pins_b: spi1@1 {
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};
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spi1_pins_c: spi1@2 {
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};
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twi6: s_twi@0x07081400 {
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};
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rgb24_pins_a: rgb24@0 {
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allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", \
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"PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", \
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"PD20", "PD21", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7";
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allwinner,pname = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", \
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"PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", \
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"PD20", "PD21", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7";
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allwinner,function = "rgb18";
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allwinner,muxsel = <2>;
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allwinner,drive = <3>;
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allwinner,pull = <0>;
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};
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rgb24_pins_b: rgb24@1 {
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allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", \
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"PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", \
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"PD20", "PD21", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7";
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allwinner,pname = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", \
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"PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", \
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"PD20", "PD21", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7";
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allwinner,function = "rgb18_suspend";
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allwinner,muxsel = <15>;
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allwinner,drive = <1>;
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allwinner,pull = <0>;
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};
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rgb18_pins_a: rgb18@0 {
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allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", \
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"PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", \
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"PD20", "PD21";
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allwinner,pname = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", \
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"PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", \
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"PD20", "PD21";
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allwinner,function = "rgb18";
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allwinner,muxsel = <2>;
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allwinner,drive = <3>;
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allwinner,pull = <0>;
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};
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rgb18_pins_b: rgb18@1 {
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allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", \
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"PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", \
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"PD20", "PD21";
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allwinner,pname = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", \
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"PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", \
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"PD20", "PD21";
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allwinner,function = "rgb18_suspend";
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allwinner,muxsel = <15>;
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allwinner,drive = <1>;
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allwinner,pull = <0>;
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};
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lvds0_pins_a: lvds0@0 {
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allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
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allwinner,pname = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
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allwinner,function = "lvds0";
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allwinner,muxsel = <3>;
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allwinner,drive = <3>;
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allwinner,pull = <0>;
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};
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lvds0_pins_b: lvds0@1 {
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allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
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allwinner,pname = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
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allwinner,function = "io_disabled";
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allwinner,muxsel = <15>;
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allwinner,drive = <3>;
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allwinner,pull = <0>;
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};
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dsi2lane_pins_a: dsi2lane@0 {
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allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5";
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allwinner,pname = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5";
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allwinner,function = "dsi2lane";
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allwinner,muxsel = <4>;
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allwinner,drive = <3>;
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allwinner,pull = <0>;
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};
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dsi2lane_pins_b: dsi2lane@1 {
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allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5";
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allwinner,pname = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5";
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allwinner,function = "dsi2lane_suspend";
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allwinner,muxsel = <15>;
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allwinner,drive = <1>;
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allwinner,pull = <0>;
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};
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dsi4lane_pins_a: dsi4lane@0 {
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allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
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allwinner,pname = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
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allwinner,function = "dsi4lane";
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allwinner,muxsel = <4>;
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allwinner,drive = <3>;
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allwinner,pull = <0>;
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};
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dsi4lane_pins_b: dsi4lane@1 {
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allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
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allwinner,pname = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
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allwinner,function = "dsi4lane_suspend";
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allwinner,muxsel = <15>;
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allwinner,drive = <1>;
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allwinner,pull = <0>;
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};
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pwm7_pin_a: pwm7@0 {
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};
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pwm7_pin_b: pwm7@1 {
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};
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pwm3_pin_a: pwm3@0 {
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};
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pwm3_pin_b: pwm3@1 {
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};
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twi0: twi0@250200 {
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};
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};
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pwm: pwm@2000c00 {
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#pwm-cells = <0x3>;
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compatible = "allwinner,sunxi-pwm";
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reg = <0x0 0x02000c00 0x0 0x400>;
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pwm-number = <8>;
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pwm-base = <0x0>;
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sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>,
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<&pwm5>, <&pwm6>, <&pwm7>;
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};
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pwm0: pwm0@2000c10 {
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compatible = "allwinner,sunxi-pwm0";
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pinctrl-names = "active", "sleep";
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reg = <0x0 0x02000c10 0x0 0x4>;
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reg_base = <0x02000c00>;
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};
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pwm1: pwm1@2000c11 {
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compatible = "allwinner,sunxi-pwm1";
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pinctrl-names = "active", "sleep";
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reg = <0x0 0x02000c11 0x0 0x4>;
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reg_base = <0x02000c00>;
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};
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pwm2: pwm2@2000c12 {
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compatible = "allwinner,sunxi-pwm2";
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pinctrl-names = "active", "sleep";
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reg = <0x0 0x02000c12 0x0 0x4>;
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reg_base = <0x02000c00>;
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};
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pwm3: pwm3@2000c13 {
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compatible = "allwinner,sunxi-pwm3";
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pinctrl-names = "active", "sleep";
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reg = <0x0 0x02000c13 0x0 0x4>;
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reg_base = <0x02000c00>;
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};
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pwm4: pwm4@2000c14 {
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compatible = "allwinner,sunxi-pwm4";
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pinctrl-names = "active", "sleep";
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reg = <0x0 0x02000c14 0x0 0x4>;
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reg_base = <0x02000c00>;
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};
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pwm5: pwm5@2000c15 {
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compatible = "allwinner,sunxi-pwm5";
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pinctrl-names = "active", "sleep";
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reg = <0x0 0x02000c15 0x0 0x4>;
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reg_base = <0x02000c00>;
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};
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pwm6: pwm6@2000c16 {
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compatible = "allwinner,sunxi-pwm6";
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pinctrl-names = "active", "sleep";
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reg = <0x0 0x02000c16 0x0 0x4>;
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reg_base = <0x02000c00>;
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};
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pwm7: pwm7@2000c17 {
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compatible = "allwinner,sunxi-pwm7";
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pinctrl-names = "active", "sleep";
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reg = <0x0 0x02000c17 0x0 0x4>;
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reg_base = <0x02000c00>;
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};
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card0_boot_para:card0_boot_para@2 {
|
||
|
|
device_type = "card0_boot_para";
|
||
|
|
};
|
||
|
|
|
||
|
|
card2_boot_para:card2_boot_para@3 {
|
||
|
|
device_type = "card2_boot_para";
|
||
|
|
};
|
||
|
|
|
||
|
|
nand0:nand0@04011000 {
|
||
|
|
device_type = "nand0";
|
||
|
|
};
|
||
|
|
|
||
|
|
spi0: spi@4025000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "allwinner,sun20i-spi";
|
||
|
|
device_type = "spi0";
|
||
|
|
reg = <0x0 0x04025000 0x0 0x300>;
|
||
|
|
//interrupts-extended = <&plic0 31 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
//clocks = <&ccu CLK_PLL_PERIPH0>, <&ccu CLK_SPI0>, <&ccu CLK_BUS_SPI0>;
|
||
|
|
//clock-names = "pll", "mod", "bus";
|
||
|
|
//resets = <&ccu RST_BUS_SPI0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
spi1: spi1@4026000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "allwinner,sun20i-spi";
|
||
|
|
device_type = "spi1";
|
||
|
|
reg = <0x0 0x04026000 0x0 0x300>;
|
||
|
|
};
|
||
|
|
|
||
|
|
disp: disp@0x5000000 {
|
||
|
|
compatible = "allwinner,sunxi-disp";
|
||
|
|
reg = <0x0 0x05000000 0x0 0x3fffff>, /* de0 */
|
||
|
|
<0x0 0x05460000 0x0 0xfff>, /*display_if_top*/
|
||
|
|
<0x0 0x05461000 0x0 0xfff>, /* tcon-lcd0 */
|
||
|
|
<0x0 0x05470000 0x0 0xfff>, /* tcon-tv */
|
||
|
|
<0x0 0x05450000 0x0 0x1fff>; /* dsi0*/
|
||
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,/*tcon-lcd0*/
|
||
|
|
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,/*tcon-tv */
|
||
|
|
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;/*dsi*/
|
||
|
|
interrupt-parent = <&gic>;
|
||
|
|
|
||
|
|
clocks = <&clk_de>,
|
||
|
|
<&clk_dpss_top>,
|
||
|
|
<&clk_tcon_lcd>,
|
||
|
|
<&clk_tcon_tv>,
|
||
|
|
<&clk_lvds>,
|
||
|
|
<&clk_mipi_host0>;
|
||
|
|
|
||
|
|
boot_disp = <0>;
|
||
|
|
boot_disp1 = <0>;
|
||
|
|
boot_disp2 = <0>;
|
||
|
|
fb_base = <0>;
|
||
|
|
/* iommus = <&mmu_aw 2 0>;*/
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
lcd0: lcd0@5461000 {
|
||
|
|
#address-cells = <2>;
|
||
|
|
#size-cells = <2>;
|
||
|
|
|
||
|
|
compatible = "allwinner,sunxi-lcd0";
|
||
|
|
reg = <0x0 0x05461000 0x0 0xfff>;
|
||
|
|
pinctrl-names = "active","sleep";
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
lcd1: lcd1@1 {
|
||
|
|
compatible = "allwinner,sunxi-lcd1";
|
||
|
|
reg = <0x0 0x1c0c000 0x0 0x0>; /* Fake registers to avoid dtc compiling warnings */
|
||
|
|
pinctrl-names = "active","sleep";
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
hdmi: hdmi@5500000 {
|
||
|
|
compatible = "allwinner,sunxi-hdmi";
|
||
|
|
reg = <0x0 0x05500000 0x0 0xfffff>;
|
||
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-parent = <&gic>;
|
||
|
|
clocks = <&clk_hdmi_slow>,
|
||
|
|
<&clk_hdmi_cec>,
|
||
|
|
<&clk_tcon_tv>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
eink: eink@6400000 {
|
||
|
|
compatible = "allwinner,sunxi-eink";
|
||
|
|
pinctrl-names = "active","sleep";
|
||
|
|
reg = <0x0 0x06400000 0x0 0x01ffff>,/* eink */
|
||
|
|
<0x0 0x06000000 0x0 0x3fffff>;/* de */
|
||
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, /* eink */
|
||
|
|
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; /* de */
|
||
|
|
clocks = <&clk_de>,
|
||
|
|
<&clk_ee>,
|
||
|
|
<&clk_panel>;
|
||
|
|
/* iommus = <&mmu_aw 6 1>; */
|
||
|
|
interrupt-parent = <&gic>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
gic: interrupt-controller@3020000 {
|
||
|
|
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
|
||
|
|
#interrupt-cells = <3>;
|
||
|
|
#address-cells = <0>;
|
||
|
|
device_type = "gic";
|
||
|
|
interrupt-controller;
|
||
|
|
reg = <0x0 0x03021000 0 0x1000>, /* GIC Dist */
|
||
|
|
<0x0 0x03022000 0 0x2000>, /* GIC CPU */
|
||
|
|
<0x0 0x03024000 0 0x2000>, /* GIC VCPU Control */
|
||
|
|
<0x0 0x03026000 0 0x2000>; /* GIC VCPU */
|
||
|
|
interrupts = <GIC_PPI 9 0xf04>; /* GIC Maintenence IRQ */
|
||
|
|
interrupt-parent = <&gic>;
|
||
|
|
};
|
||
|
|
aliases:aliases@45100000 {
|
||
|
|
};
|
||
|
|
|
||
|
|
};
|
||
|
|
|
||
|
|
#include ".board-uboot.dts"
|