377 lines
13 KiB
C
377 lines
13 KiB
C
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/**
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* @file hal_adc.h
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* @author XRADIO IOT WLAN Team
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*/
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/*
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* Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DRIVER_CHIP_HAL_ADC_H_
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#define _DRIVER_CHIP_HAL_ADC_H_
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#include "driver/chip/hal_def.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief ADC channel definition
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*/
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typedef enum {
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ADC_CHANNEL_0 = 0,
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ADC_CHANNEL_1 = 1,
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ADC_CHANNEL_2 = 2,
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ADC_CHANNEL_3 = 3,
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ADC_CHANNEL_4 = 4,
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ADC_CHANNEL_5 = 5,
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ADC_CHANNEL_6 = 6,
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ADC_CHANNEL_8 = 8,
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ADC_CHANNEL_NUM
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} ADC_Channel;
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/* ADC channel for VBAT voltage detection */
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#define ADC_CHANNEL_VBAT ADC_CHANNEL_8
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/**
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* @brief ADC register block structure
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*/
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typedef struct {
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__IO uint32_t SAMPLE_RATE; /* offset: 0x00, GPADC sample rate configure register */
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__IO uint32_t CTRL; /* offset: 0x04, GPADC control Register */
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__IO uint32_t CMP_SEL_EN; /* offset: 0x08, GPADC compare and select enable register */
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__IO uint32_t FIFO_CTRL; /* offset: 0x0C, GPADC FIFO interrupt control register */
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__IO uint32_t FIFO_STATUS; /* offset: 0x10, GPADC FIFO interrupt status register */
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__IO uint32_t FIFO_DATA; /* offset: 0x14, GPADC FIFO data register */
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__IO uint32_t CALIB_DATA; /* offset: 0x18, GPADC calibration data register */
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__IO uint32_t RESERVED0;
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__IO uint32_t LOW_CONFIG; /* offset: 0x20, GPADC data low interrupt configure register */
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__IO uint32_t HIGH_CONFIG; /* offset: 0x24, GPADC data high interrupt configure register */
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__IO uint32_t DATA_CONFIG; /* offset: 0x28, GPADC data interrupt configure register */
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__IO uint32_t RESERVED1;
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__IO uint32_t LOW_STATUS; /* offset: 0x30, GPADC data low interrupt status register */
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__IO uint32_t HIGH_STATUS; /* offset: 0x34, GPADC data high interrupt status register */
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__IO uint32_t DATA_STATUS; /* offset: 0x38, GPADC data interrupt status register */
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__IO uint32_t RESERVED2;
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__IO uint32_t CMP_DATA[ADC_CHANNEL_NUM]; /* offset: 0x40, GPADC CH n compare data register */
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__IO uint32_t RESERVED3[7];
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__I uint32_t DATA[ADC_CHANNEL_NUM]; /* offset: 0x80, GPADC CH n data register */
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} ADC_T;
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#define ADC ((ADC_T *)GPADC_BASE) /* address: 0x40043000 */
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/* ADC->SAMPLE_RATE */
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#define ADC_FS_DIV_SHIFT 16
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#define ADC_FS_DIV_MASK (0xFFFFU << ADC_FS_DIV_SHIFT)
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#define ADC_TACQ_SHIFT 0
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#define ADC_TACQ_MASK (0xFFFFU << ADC_TACQ_SHIFT)
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/* ADC->CTRL */
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#define ADC_FIRST_DELAY_SHIFT 24
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#define ADC_FIRST_DELAY_MASK (0xFFU << ADC_FIRST_DELAY_SHIFT)
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#define ADC_OP_BIAS_SHIFT 20
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#define ADC_OP_BIAS_MASK (0x3U << ADC_OP_BIAS_SHIFT)
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#define ADC_WORK_MODE_SHIFT 18
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#define ADC_WORK_MODE_MASK (0x3U << ADC_WORK_MODE_SHIFT)
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typedef enum {
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ADC_SINGLE_CONV = 0U,
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ADC_SINGLE_CYCLE = 1U,
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ADC_CONTI_CONV = 2U,
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ADC_BURST_CONV = 3U
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} ADC_WorkMode;
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#define ADC_CALIB_EN_BIT HAL_BIT(17)
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#define ADC_EN_BIT HAL_BIT(16)
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#define ADC_VBAT_EN_BIT HAL_BIT(5)
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#if (CONFIG_CHIP_ARCH_VER > 1)
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#define ADC_VREF_MODE_SEL_SHIFT 1
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#define ADC_VREF_MODE_SEL_MASK (0x7U << ADC_VREF_MODE_SEL_SHIFT)
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/**
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* @brief ADC vref mode select
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*/
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typedef enum {
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ADC_VREF_MODE_0 = 0U, /*Vref select inside voltage, input range of 0~1.4V*/
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ADC_VREF_MODE_1 = 1U, /*Vref select inside voltage, input range of 0~2.5V*/
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ADC_VREF_MODE_2 = 2U, /*Vref select outside pin VDDIO, EXT_LDO 3.3V*/
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ADC_VREF_MODE_3 = 6U, /*Vref select outside pin VDDIO, EXT_LDO 3.1V*/
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} ADC_VrefMode;
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#endif /* CONFIG_CHIP_ARCH_VER */
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#define ADC_LDO_EN_BIT HAL_BIT(0)
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/* ADC->CMP_SEL_EN */
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#define ADC_CMP_EN_SHIFT 16
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#define ADC_CMP_EN_MASK (0x1FFU << ADC_CMP_EN_SHIFT)
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#define ADC_SEL_EN_SHIFT 0
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#define ADC_SEL_EN_MASK (0x1FFU << ADC_SEL_EN_SHIFT)
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/*
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* ADC->LOW_CONFIG
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* ADC->HIGH_CONFIG
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* ADC->DATA_CONFIG
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*/
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#define ADC_LOW_IRQ_MASK 0x1FFU
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#define ADC_HIGH_IRQ_MASK 0x1FFU
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#define ADC_DATA_IRQ_MASK 0x1FFU
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/*
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* ADC->FIFO_CTRL
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*/
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#define ADC_FIFO_DATA_DRQ_MASK HAL_BIT(18)
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#define ADC_FIFO_OVERUN_IRQ_MASK HAL_BIT(17)
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#define ADC_FIFO_DATA_IRQ_MASK HAL_BIT(16)
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#define ADC_FIFO_LEVEL_SHIFT 8
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#define ADC_FIFO_LEVEL_MASK (0x3FU << ADC_FIFO_LEVEL_SHIFT)
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#define ADC_FIFO_FLUSH_MASK HAL_BIT(4)
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/*
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* ADC->FIFO_STATUS
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*/
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#define ADC_FIFO_OVERUN_PENDING_MASK HAL_BIT(17)
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#define ADC_FIFO_DATA_PENDING_MASK HAL_BIT(16)
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/* ADC->FIFO_DATA */
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#define ADC_FIFO_DATA_MASK 0xFFFU
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/*
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* ADC->LOW_STATUS
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* ADC->HIGH_STATUS
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* ADC->DATA_STATUS
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*/
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#define ADC_LOW_PENDING_MASK 0x1FFU
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#define ADC_HIGH_PENDING_MASK 0x1FFU
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#define ADC_DATA_PENDING_MASK 0x1FFU
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/* ADC->CMP_DATA */
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#define ADC_HIGH_DATA_SHIFT 16
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#define ADC_HIGH_DATA_MASK (0xFFFU << ADC_HIGH_DATA_SHIFT)
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#define ADC_LOW_DATA_SHIFT 0
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#define ADC_LOW_DATA_MASK (0xFFFU << ADC_LOW_DATA_SHIFT)
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/* ADC->DATA */
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#define ADC_DATA_MASK 0xFFFU
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/******************************************************************************/
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/**
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* @brief ADC work clock selected definition
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*/
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typedef enum {
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ADC_WORKCLK_HFCLK = 0,
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ADC_WORKCLK_LFCLK = 1
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} ADC_WorkClk;
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/**
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* @brief ADC channel initialization parameters
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*/
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typedef struct {
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#if (CONFIG_CHIP_ARCH_VER == 3)
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ADC_WorkClk work_clk; /* ADC word clock select */
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#endif
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uint32_t freq; /* ADC sample frequency */
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uint8_t delay; /* the number of delayed samples in first conversion */
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uint8_t suspend_bypass;
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#if (CONFIG_CHIP_ARCH_VER > 1)
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ADC_VrefMode vref_mode; /* VERF mode select */
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#endif
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ADC_WorkMode mode; /* ADC work mode */
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} ADC_InitParam;
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/**
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* @brief ADC channel selected state definition
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*/
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typedef enum {
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ADC_SELECT_DISABLE = 0,
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ADC_SELECT_ENABLE = 1
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} ADC_Select;
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/**
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* @brief ADC interrupt mode definition
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*/
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typedef enum {
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ADC_IRQ_NONE = 0,
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ADC_IRQ_DATA = 1,
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ADC_IRQ_LOW = 2,
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ADC_IRQ_HIGH = 3,
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ADC_IRQ_LOW_DATA = 4,
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ADC_IRQ_HIGH_DATA = 5,
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ADC_IRQ_LOW_HIGH = 6,
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ADC_IRQ_LOW_HIGH_DATA = 7
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} ADC_IRQMode;
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/**
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* @brief ADC interrupt state definition
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*/
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typedef enum {
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ADC_NO_IRQ = 0,
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ADC_DATA_IRQ = 1,
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ADC_LOW_IRQ = 2,
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ADC_HIGH_IRQ = 3,
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ADC_LOW_DATA_IRQ = 4,
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ADC_HIGH_DATA_IRQ = 5
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} ADC_IRQState;
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/** @brief Type define of ADC interrupt callback function */
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typedef void (*ADC_IRQCallback)(void *arg);
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/**
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* @brief Initialize the ADC according to the specified parameters.
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* @param[in] initParam Pointer to ADC_InitParam structure.
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* @retval HAL_Status, HAL_OK on success.
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*/
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HAL_Status HAL_ADC_Init(ADC_InitParam *initParam);
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/**
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* @brief DeInitialize the ADC
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* @retval HAL_Status, HAL_OK on success
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*/
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HAL_Status HAL_ADC_DeInit(void);
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/**
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* @brief The specified ADC channel convert once in polling mode
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* @param[in] chan The specified ADC channel
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* @param[in] data Pointer to the output data
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* @param[in] msec Timeout value in millisecond of conversion
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* HAL_WAIT_FOREVER for no timeout
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* @retval HAL_Status, HAL_OK on success
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*/
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HAL_Status HAL_ADC_Conv_Polling(ADC_Channel chan, uint32_t *data, uint32_t msec);
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/**
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* @brief Enable interrupt callback function for the specified ADC channel
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* @param[in] chan The specified ADC channel
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* @param[in] cb The interrupt callback function
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* @param[in] arg Argument of the interrupt callback function
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* @retval HAL_Status, HAL_OK on success
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*/
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HAL_Status HAL_ADC_EnableIRQCallback(ADC_Channel chan, ADC_IRQCallback cb, void *arg);
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/**
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* @brief Disable interrupt callback function for the specified ADC channel
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* @param[in] chan The specified ADC channel
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* @retval HAL_Status, HAL_OK on success
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*/
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HAL_Status HAL_ADC_DisableIRQCallback(ADC_Channel chan);
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/**
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* @brief Configure the specified ADC channel for conversion in interrupt mode(CHAN mode)
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* @param[in] chan The specified ADC channel
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* @param[in] select ADC channel selected state
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* @param[in] mode ADC interrupt mode
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* @param[in] lowValue lower limit value in interrupt mode of ADC_IRQ_LOW,
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* ADC_IRQ_LOW_DATA, ADC_IRQ_LOW_HIGH or ADC_IRQ_LOW_HIGH_DATA
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* @param[in] highValue Upper limit value in interrupt mode of ADC_IRQ_HIGH,
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* ADC_IRQ_HIGH_DATA, ADC_IRQ_LOW_HIGH or ADC_IRQ_LOW_HIGH_DATA
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* @retval HAL_Status, HAL_OK on success, HAL_ERROR on fail
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*/
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HAL_Status HAL_ADC_ConfigChannel(ADC_Channel chan, ADC_Select select, ADC_IRQMode mode, uint32_t lowValue, uint32_t highValue);
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/**
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* @brief Configure the specified ADC channel for conversion in interrupt mode(FIFO mode)
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* @param[in] chan The specified ADC channel
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* @param[in] select ADC channel selected state
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* @retval HAL_Status, HAL_OK on success, HAL_ERROR on fail, HAL_INVALID on invalid argument
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* @note When this function is called, the FIFO will be flushed firstly
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*/
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HAL_Status HAL_ADC_FifoConfigChannel(ADC_Channel chan, ADC_Select select);
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/**
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* @brief Start the ADC conversion in interrupt mode
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* @retval HAL_Status, HAL_OK on success
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*/
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HAL_Status HAL_ADC_Start_Conv_IT(void);
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/**
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* @brief Stop the ADC conversion in interrupt mode
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* @retval HAL_Status, HAL_OK on success
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*/
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HAL_Status HAL_ADC_Stop_Conv_IT(void);
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/**
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* @brief Get interrupt mode of the specified ADC channel
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* @param[in] chan The specified ADC channel
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* @retval HAL_Status, HAL_OK on success
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*/
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ADC_IRQState HAL_ADC_GetIRQState(ADC_Channel chan);
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/**
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* @brief Get digital value of the specified ADC channel
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* @param[in] chan The specified ADC channel
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* @return Digital value converted by the specified ADC channel
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*/
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uint32_t HAL_ADC_GetValue(ADC_Channel chan);
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/**
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* @brief Get digital value of the ADC fifo
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* @param[in] NULL
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* @return Digital value converted by the ADC fifo
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* @note before call it, fifo data should be available
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*/
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uint32_t HAL_ADC_GetFifoData(void);
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/**
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* @brief Get data count of ADC fifo
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* @param[in] NULL
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* @return the specified data count of ADC fifo
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*/
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uint8_t HAL_ADC_GetFifoDataCount(void);
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/**
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* @brief modify adc vref voltage
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* @param Mode Mode 0 usage is verf inside soc, and input voltage range of 0~1.4v.
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* @ Mode 1 usage is verf inside soc, and input voltage range of 0~2.5v.
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* @ Mode 2 usage is verf outside pin, and input voltage range of 0~2.5v.
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* @return None
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* @NOTE: Mode 0 and Mode 1 can calculate virtual voltage according to ADC Value But Mode 2 and Mode 3 NOT.
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Mode 2 and Mode 3 adc value will not expand when vddio and channel voltage change at the same time.
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*/
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void HAL_ADC_Set_VrefMode(ADC_VrefMode mode);
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/**
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* @brief Set PM mode to be bypassed
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* @param[in] mode Bit mask of PM mode to be bypassed
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* @retval HAL_Status, HAL_OK on success
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*/
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HAL_Status HAL_ADC_SetBypassPmMode(uint8_t mode);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRIVER_CHIP_HAL_ADC_H_ */
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