316 lines
14 KiB
C
316 lines
14 KiB
C
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/**
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* @file hal_dmic.h
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* @author XRADIO IOT WLAN Team
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*/
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/*
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* Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DRIVER_CHIP_HAL_DMIC_H_
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#define _DRIVER_CHIP_HAL_DMIC_H_
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#include <stdbool.h>
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#include "driver/chip/hal_def.h"
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#include "driver/chip/hal_gpio.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct {
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__IO uint32_t DMIC_EN; /* DMIC enable control register Address offset: 0x0000 */
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__IO uint32_t DMIC_SR; /* DMIC sample rate register Adrress offset: 0x0004 */
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__IO uint32_t DMIC_CTR; /* DMIC control register Address offset: 0x0008 */
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__IO uint32_t RESERVED0;
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__IO uint32_t DMIC_DATA; /* DMIC data register Address offset: 0x0010 */
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__IO uint32_t DMIC_INTC; /* DMIC interrupt control register Address offset: 0x0014 */
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__IO uint32_t DMIC_INTS; /* DMIC interrupt status register Address offset: 0x0018 */
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__IO uint32_t FIFO_CTR; /* DMIC FIFO control register Address offset: 0x001C */
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__I uint32_t FIFO_STA; /* DMIC FIFO status register Address offset: 0x0020 */
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__IO uint32_t CH_NUM; /* DMIC channel numbers register Address offset: 0x0024 */
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__IO uint32_t CH_MAP; /* DMIC channel mapping register Address offset: 0x0028 */
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__IO uint32_t DMIC_CNT; /* DMIC counter register Address offset: 0x002C */
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__IO uint32_t DATA0_DATA1_VOL_CTR; /* DATA0 and DATA1 volume control register Address offset: 0x0030 */
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__IO uint32_t DATA2_DATA3_VOL_CTR; /* High pass filter enable control register Address offset: 0x0034 */
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__IO uint32_t HPF_EN_CTR; /**/
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__IO uint32_t HPF_COEF_REG; /* High pass filter coef register Address offset: 0x003C */
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__IO uint32_t HPF_GAIN_REG; /* High pass filter gain register Address offset: 0x0040 */
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} DMIC_T;
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#define DMIC ((DMIC_T *)DMIC_BASE)
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/*
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* Bits definition for DMIC_ECR register(0x0000)
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*/
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#define DMIC_ECR_DATA0_CHL_EN_BIT HAL_BIT(0)
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#define DMIC_ECR_DATA0_CHR_EN_BIT HAL_BIT(1)
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#define DMIC_ECR_DATA1_CHL_EN_BIT HAL_BIT(2)
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#define DMIC_ECR_DATA1_CHR_EN_BIT HAL_BIT(3)
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#define DMIC_ECR_DATA2_CHL_EN_BIT HAL_BIT(4)
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#define DMIC_ECR_DATA2_CHR_EN_BIT HAL_BIT(5)
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#define DMIC_ECR_DATA3_CHL_EN_BIT HAL_BIT(6)
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#define DMIC_ECR_DATA3_CHR_EN_BIT HAL_BIT(7)
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#define DMIC_ECR_GLOBE_EN HAL_BIT(8)
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/*
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* Bits definition for DMIC_SRR register (0x0004)
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*/
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#define DMIC_SR_SHIFT (0)
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#define DMIC_SR_MASK (0x7U << DMIC_SR_SHIFT)
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/**
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* @brief Dmic sample rate definition
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*/
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typedef enum {
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DMIC_SR48KHZ = (0X0U << DMIC_SR_SHIFT),
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DMIC_SR44KHZ = (0X8U << DMIC_SR_SHIFT),/*44100*/
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DMIC_SR24KHZ = (0X2U << DMIC_SR_SHIFT),
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DMIC_SR22KHZ = (0X9U << DMIC_SR_SHIFT),/*22050*/
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DMIC_SR12KHZ = (0X4U << DMIC_SR_SHIFT),
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DMIC_SR11KHZ = (0XaU << DMIC_SR_SHIFT),/*11025*/
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DMIC_SR32KHZ = (0X1U << DMIC_SR_SHIFT),
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DMIC_SR16KHZ = (0X3U << DMIC_SR_SHIFT),
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DMIC_SR8KHZ = (0X5U << DMIC_SR_SHIFT),
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} DMIC_SampleRate;
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/*
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* Bits definition for DMIC_CTLR register (0X0008)
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*/
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#define DMIC_CTLR_OVERSAMPLE_RATE_SHIFT (0)
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#define DMIC_CTLR_OVERSAMPLE_RATE_MASK (0x1U << DMIC_CTLR_OVERSAMPLE_RATE_SHIFT)
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typedef enum {
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DMIC_CTLR_OVERSAMPLE_RATE64 = (0X1U << DMIC_CTLR_OVERSAMPLE_RATE_SHIFT),
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DMIC_CTLR_OVERSAMPLE_RATE128 = (0X0U << DMIC_CTLR_OVERSAMPLE_RATE_SHIFT),
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} DMIC_OverSampleRate;
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#define DMIC_CTLR_DATA0_SWAP_BIT HAL_BIT(4) /* bit4, data0 left data and right data sweep enable */
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#define DMIC_CTLR_DATA1_SWAP_BIT HAL_BIT(5) /* bit5, data1 left data and right data sweep enable */
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#define DMIC_CTLR_DATA2_SWAP_BIT HAL_BIT(6) /* bit6, data2 left data and right data sweep enable */
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#define DMIC_CTLR_DATA3_SWAP_BIT HAL_BIT(7) /* bit7, data3 left data and right data sweep enable */
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#define DMIC_CTLR_DMICDFEN_BIT HAL_BIT(8) /* bit8, dmic fifo delay function for writing data after globe_en */
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#define DMIC_CTLR_DMICFDT_SHIFT (9)
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#define DMIC_CTLR_DMICFDT_MASK (0x3U << DMIC_CTLR_OVERSAMPLE_RATE_SHIFT)
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typedef enum {
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DMIC_CTLR_DMICFDT_5MS = (0X0U << DMIC_CTLR_DMICFDT_SHIFT),
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DMIC_CTLR_DMICFDT_10MS = (0X1U << DMIC_CTLR_DMICFDT_SHIFT),
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DMIC_CTLR_DMICFDT_200MS = (0X2U << DMIC_CTLR_DMICFDT_SHIFT),
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DMIC_CTLR_DMICFDT_30MS = (0X3U << DMIC_CTLR_DMICFDT_SHIFT),
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} DMIC_CtrlDmicFDT;
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/*
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* Bits definition for DMIC_ICR register (0x14)
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*/
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#define DMIC_ICR_DATA_IRQ_EN_BIT HAL_BIT(0) /* bit0, dmic fifo data available irq enable */
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#define DMIC_ICR_OVERRUN_IRQ_EN_BIT HAL_BIT(1) /* bit1, dmic fifo fifo overrun irq enable */
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#define DMIC_ICR_FIFO_DRQ_EN_BIT HAL_BIT(2) /* bit2, dmic fifo data available drq enable */
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/*
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* Bits definition for DMIC_ISR register (0X18)
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*/
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#define DMIC_ISR_DATA_IRQ_PEND_BIT HAL_BIT(0) /* bit0, dmic fifo data available pending interrupt */
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#define DMIC_ISR_OVERRUN_IRQ_PEND_BIT HAL_BIT(1) /* bit1, dmic fifo fifo overrun pending interrupt */
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/*
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* Bits definition for DMIC_FIFOCR register(0X1C)
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*/
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#define DMIC_FIFOCR_TRG_LEVEL_SHIFT (0)
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#define DMIC_FIFOCR_TRG_LEVEL_MASK (0xFFU << DMIC_FIFOCR_TRG_LEVEL_SHIFT)
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#define DMIC_FIFOCR_TRG_LEVEL(n) ((n) << DMIC_FIFOCR_TRG_LEVEL_SHIFT)
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#define DMIC_FIFOCR_SAMPLE_RES_SHIFT (8)
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#define DMIC_FIFOCR_SAMPLE_RES_MASK (0x1U << DMIC_FIFOCR_SAMPLE_RES_SHIFT)
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/**
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* @brief sampling accuracy
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*/
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typedef enum {
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DMIC_RES16BIT = (0X0U << DMIC_FIFOCR_SAMPLE_RES_SHIFT),
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DMIC_RES24BIT = (0X1U << DMIC_FIFOCR_SAMPLE_RES_SHIFT),
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} DMIC_FifoSampleRes;
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#define DMIC_FIFOCR_MODE_SHIFT (9)
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#define DMIC_FIFOCR_MODE_MASK (0x1U << DMIC_FIFOCR_MODE_SHIFT)
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typedef enum {
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DMIC_FIFOCR_MODE0 = (0X0U << DMIC_FIFOCR_MODE_SHIFT),
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DMIC_FIFOCR_MODE1 = (0X1U << DMIC_FIFOCR_MODE_SHIFT),
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} DMIC_FifoMode;
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#define DMIC_FIFOCR_FIFO_FLUSH_BIT HAL_BIT(31) /* bit31, dmic fifo flush */
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/*
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* Bits definition for DMIC_FIFOSR register (0x20)
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*/
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#define DMIC_FIFOSR_DATA_CNT_SHIFT (0)
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#define DMIC_FIFOSR_DATA_CNT_MASK (0xFFU << DMIC_FIFOSR_DATA_CNT_SHIFT) /* bit0:bit7, FIFO available sample world counter */
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/*
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* Bits definition for DMIC_CNR register
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*/
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#define DMIC_CH_NUM_SHIFT (0)
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#define DMIC_CH_NUM_MASK (0X7U << DMIC_CH_NUM_SHIFT)
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typedef enum {
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DMIC_CH_NUM1 = (0X0U << DMIC_CH_NUM_SHIFT),
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DMIC_CH_NUM2 = (0X1U << DMIC_CH_NUM_SHIFT),
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DMIC_CH_NUM3 = (0X2U << DMIC_CH_NUM_SHIFT),
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DMIC_CH_NUM4 = (0X3U << DMIC_CH_NUM_SHIFT),
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DMIC_CH_NUM5 = (0X4U << DMIC_CH_NUM_SHIFT),
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DMIC_CH_NUM6 = (0X5U << DMIC_CH_NUM_SHIFT),
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DMIC_CH_NUM7 = (0X6U << DMIC_CH_NUM_SHIFT),
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DMIC_CH_NUM8 = (0X7U << DMIC_CH_NUM_SHIFT),
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} DMIC_ChannelNum;
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/*
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* Bits definition for DMIC_CMR register(0x28)
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*/
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#define DMIC_CMR_CH0_MAP_SHIFT (0)
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#define DMIC_CMR_CH0_MAP_MASK(m) (0X7U << 4*m)
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#define DMIC_CMR_CH0_MAP(m) (m << 4*m)
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/*
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* Bits definition for DMIC_VCR0 register (0X0030)
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*/
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#define DMIC_DATA0R_VOL_SHIFT (0)
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#define DMIC_DATA0R_VOL_MASK (0xFFU << DMIC_DATA0R_VOL_SHIFT)
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#define DMIC_DATA0R_VOL(n) (n << DMIC_DATA0R_VOL_SHIFT)
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#define DMIC_DATA0L_VOL_SHIFT (8)
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#define DMIC_DATA0L_VOL_MASK (0xFFU << DMIC_DATA0L_VOL_SHIFT)
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#define DMIC_DATA0L_VOL(n) (n << DMIC_DATA0L_VOL_SHIFT)
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#define DMIC_DATA1R_VOL_SHIFT (16)
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#define DMIC_DATA1R_VOL_MASK (0xFFU << DMIC_DATA1R_VOL_SHIFT)
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#define DMIC_DATA1L_VOL_SHIFT (24)
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#define DMIC_DATA1L_VOL_MASK (0xFFU << DMIC_DATA1L_VOL_SHIFT)
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/*
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* Bits definition for DMIC_VCR1 register (0X0034)
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*/
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#define DMIC_DATA2R_VOL_SHIFT (0)
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#define DMIC_DATA2R_VOL_MASK (0xFFU << DMIC_DATA2R_VOL_SHIFT)
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#define DMIC_DATA2L_VOL_SHIFT (8)
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#define DMIC_DATA2L_VOL_MASK (0xFFU << DMIC_DATA2L_VOL_SHIFT)
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#define DMIC_DATA3R_VOL_SHIFT (16)
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#define DMIC_DATA3R_VOL_MASK (0xFFU << DMIC_DATA3R_VOL_SHIFT)
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#define DMIC_DATA3L_VOL_SHIFT (24)
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#define DMIC_DATA3L_VOL_MASK (0xFFU << DMIC_DATA3L_VOL_SHIFT)
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/*
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* Bits definition for DMIC_HPFECR register (0X0038)
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*/
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#define DMIC_HPF_DATA0_CHL_EN_BIT HAL_BIT(0) /* bit0, data0 left channel enable */
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#define DMIC_HPF_DATA0_CHR_EN_BIT HAL_BIT(1) /* bit1, data0 right channel 1 enable */
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#define DMIC_HPF_DATA1_CHL_EN_BIT HAL_BIT(2) /* bit2, data1 left channel enable */
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#define DMIC_HPF_DATA1_CHR_EN_BIT HAL_BIT(3) /* bit3, data1 right channel 1 enable */
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#define DMIC_HPF_DATA2_CHL_EN_BIT HAL_BIT(4) /* bit4, data2 left channel enable */
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#define DMIC_HPF_DATA2_CHR_EN_BIT HAL_BIT(5) /* bit5, data2 right channel 1 enable */
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#define DMIC_HPF_DATA3_CHL_EN_BIT HAL_BIT(6) /* bit6, data3 left channel enable */
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#define DMIC_HPF_DATA3_CHR_EN_BIT HAL_BIT(7) /* bit7, data3 right channel 1 enable */
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/**
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* @brief Dmic low level hardware init structure definition
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*/
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typedef struct {
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DMIC_CtrlDmicFDT delayTime; /*!< Specifies dmic fdt delay time. */
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DMIC_FifoMode fifoMode; /*!< Specifies dmic fifo mode. */
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uint32_t triggerLevel; /*!< Specifies the threshold for dmic fifo triggers. */
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uint32_t volumeGain; /*!< Specifies the dmic hardware gain. */
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bool hpfEnable; /*!< Specifies whether to enable hpf function. */
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} DMIC_HWParam;
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/**
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* @brief Dmic data format init structure definition
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*/
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typedef struct {
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DMIC_SampleRate sampleRate; /*!< Specifies the sampling rate of the stream. */
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DMIC_FifoSampleRes resolution; /*!< Specifies the sampling accuracy of the stream. */
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uint32_t channels; /*!< Specifies the number of the stream. */
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uint32_t bufSize; /*!< Specifies the buffer size of received data. */
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} DMIC_DataParam;
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/**
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* @brief Dmic module init structure definition
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*/
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typedef struct {
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const DMIC_HWParam *hwParam; /*!< Dmic hardware init structure. */
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} DMIC_Param;
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/**
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* @brief Initializes the DMIC according to the specified parameters
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* in the DMIC_Param.
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* @param param: pointer to a DMIC_Param structure that contains
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* the hw configuration information for DMIC controller
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* @retval HAL status
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*/
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HAL_Status HAL_DMIC_Init(DMIC_Param *param);
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/**
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* @brief DeInitializes the DMIC module
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* @retval
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*/
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void HAL_DMIC_DeInit(void);
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/**
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* @brief Open the DMIC module according to the specified parameters
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* in the DMIC_DataParam.
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* @param param: pointer to a DMIC_DataParam structure that contains
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* the data format information
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* @retval HAL status
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*/
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HAL_Status HAL_DMIC_Open(DMIC_DataParam *param);
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/**
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* @brief Close the DMIC module
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* @note The module is closed at the end of transaction to avoid power consumption
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* @retval none
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*/
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void HAL_DMIC_Close(void);
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HAL_Status HAL_DMIC_Suspend(void);
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HAL_Status HAL_DMIC_Resume(void);
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/**
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* @brief Receive an amount of data with DMA
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* @param buf: pointer to the Receive data buffer.
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* @param Size: length of buf to be Receive:
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* @retval length of receive data
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*/
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int32_t HAL_DMIC_Read_DMA(uint8_t *buf, uint32_t size);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRIVER_CHIP_HAL_DMIC_H_ */
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