284 lines
8.5 KiB
C
284 lines
8.5 KiB
C
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/**
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* @file psram.h
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* @author XRADIO IOT WLAN Team
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*/
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/*
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* Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _PSRAM_H
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#define _PSRAM_H
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#include "driver/chip/hal_def.h"
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#include "driver/chip/hal_xip.h"
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#include "kernel/os/os_semaphore.h"
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#ifdef CONFIG_PSRAM
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#define PSRAM_DBG_CHECK 0
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#define PSRAM_DBG_ON 0
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#define PSRAM_WRN_ON 1
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#define PSRAM_ERR_ON 1
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#define PSRAM_ABORT_ON 1
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#define PSRAM_SYSLOG printf
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#define PSRAM_ABORT() do { } while (0)
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#define PSRAM_LOG(flags, fmt, arg...) \
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do { \
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if (flags) { \
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__sram_rodata static char __fmt[] = fmt; \
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PSRAM_SYSLOG(__fmt, ##arg); \
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} \
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} while (0)
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#define PSRAM_DBG(fmt, arg...) \
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PSRAM_LOG(PSRAM_DBG_ON, "[psram] "fmt, ##arg)
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#define PSRAM_INF(fmt, arg...) \
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PSRAM_LOG(PSRAM_WRN_ON, "[psram] "fmt, ##arg)
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#define PSRAM_WRN(fmt, arg...) \
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PSRAM_LOG(PSRAM_WRN_ON, "[psram WRN] "fmt, ##arg)
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#define PSRAM_ERR(fmt, arg...) \
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do { \
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PSRAM_LOG(PSRAM_ERR_ON, "[psram ERR] "fmt, ##arg); \
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if (PSRAM_ABORT_ON) \
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PSRAM_ABORT(); \
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} while (0)
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#if PSRAM_DBG_ON
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#define PSRAM_DUMP(a, l) print_hex_dump_bytes(a, l)
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#else
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#define PSRAM_DUMP(a, l)
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#endif
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#ifdef CONFIG_PLATFORM_FPGA
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#define PSRAM_FREQ (6000000)
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#else
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#if CONFIG_PSRAM_FREQ_96M
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#define PSRAM_FREQ (96000000)
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#elif CONFIG_PSRAM_FREQ_120M
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#define PSRAM_FREQ (120000000)
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#else
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#error "select a freq for psram!"
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#endif
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#endif
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/*---------PSRAM SPI/QPI Command set------*/
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#if (defined CONFIG_PSRAM_CHIP_SQPI)
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#define SQ_Read 0x03
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#define SQ_Fast_Read 0x0B /* 66MHz, wait 4 cycle every read */
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#define SQ_Fast_Read_Quad 0xEB /* 144/84MHz, wait 6 cycle every read */
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#define SQ_Write 0x02
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#define SQ_Quad_Write 0x38
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#define SQ_Mode_Reg_Read 0xB5
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#define SQ_Mode_Reg_Write 0xB1
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#define SQ_Wrapped_Read 0x8B
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#define SQ_Wrapped_Write 0x82
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#define SQ_ModeResister_Read 0xB5
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#define SQ_ModeResister_Write 0xB1
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#define SQ_Enter_Quad_Mode 0x35
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#define SQ_Exit_Quad_Mode 0xF5
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#define SQ_Reset_Enable 0x66
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#define SQ_Reset 0x99
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#define SQ_Wrap 0xC0
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#define SQ_Read_ID 0x9F
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/*--------PSRAM OPI Command set-----------*/
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#elif ((defined CONFIG_PSRAM_CHIP_OPI32) || (defined CONFIG_PSRAM_CHIP_OPI64))
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#define Sync_Read 0x00
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#define Sync_Write 0x80
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#define Sync_Burst_Read 0x20
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#define Sync_Burst_Write 0xA0
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#define Mode_Reg_Read 0x40
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#define Mode_Reg_Write 0xC0
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#define Global_Reaet 0xFF
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#endif
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/*--------OPI Mode Register Address-------*/
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#define MR0 0x00
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#define MR1 0x01
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#define MR2 0x02
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#define MR3 0x03
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#define MR4 0x04
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#define MR5 0x05
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#define MR6 0x06
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#define MR7 0x07
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/*--------Drive Strength-----------------*/
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#define DRV_STR_50_OHM 0
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#define DRV_STR_100_OHM 1
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#define DRV_STR_200_OHM 2
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/*--------------define by myself----------*/
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#define S_READ 0x00
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#define S_FAST_READ 0x01
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#define S_FAST_READ_QUAD 0x02
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#define S_WRITE 0x03
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#define S_QAUD_WRITE 0x04
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#define Q_FAST_READ 0x05
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#define Q_FAST_READ_QUAD 0x06
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#define Q_WRITE 0x07
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#define O_SYNC_READ 0x08
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#define O_SYNC_WRITE 0x09
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#define O_SYNC_BURST_READ 0x0A
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#define O_SYNC_BURST_WRITE 0x0B
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/*--------SQPI MODE Reset-----------------*/
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#define S_RST 0
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#define Q_RST 1
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#define P_DMA_B1W8 0
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#define P_DMA_B1W16 1
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#define P_DMA_B1W32 2
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#define P_DMA_B4W8 3
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#define P_DMA_B4W16 4
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#define P_DMA_B4W32 5
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#define FLUSH_LEN_HSIZE 32
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#define FLUSH_LEN_CSIZE_128 128
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#define FLUSH_LEN_CSIZE_256 256
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#define FLUSH_LEN_CSIZE_896 896
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#define FLUSH_MODE FLUSH_LEN_CSIZE_128
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#define DCACHE_OPEN
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/* chip information */
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#define PSRAM_CHIP_SQPI 0
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#define PSRAM_CHIP_OPI_APS32 1
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#define PSRAM_CHIP_OPI_APS64 2
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#define PSRAM_CHIP_MAX 3
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/**
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* @brief PSRAM initialization parameters
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*/
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typedef struct {
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uint32_t p_type;
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uint32_t freq; /*!< PSRAM Chip working frequency */
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} PSRAMChip_InitParam;
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struct psram_chip {
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uint8_t id;
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uint8_t type;
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uint8_t ref;
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uint8_t suspend;
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uint8_t cbus_rcmd;
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uint8_t cbus_wcmd;
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uint8_t mf_id;
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uint8_t kgd;
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uint32_t die;
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uint32_t buswidth;
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uint32_t wrap_len;
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uint32_t capacity;
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uint32_t freq;
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char *name;
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#ifdef CONFIG_PSRAM_PM_DATA_CHECK
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uint16_t pm_checksum;
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#endif
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struct psram_ctrl *ctrl;
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};
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#define PSRAM_DATA_WRITE_BYTE (1 << 0)
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#define PSRAM_DATA_WRITE_SHORT (1 << 1)
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#define PSRAM_DATA_WRITE_WORD (1 << 2)
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#define PSRAM_DATA_WRITE_MASK (0x07 << 0)
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#define PSRAM_DATA_READ_BYTE (1 << 4)
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#define PSRAM_DATA_READ_SHORT (1 << 5)
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#define PSRAM_DATA_READ_WORD (1 << 6)
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#define PSRAM_DATA_READ_MASK (0x07 << 4)
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struct psram_data {
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uint32_t blksz; /* data block size */
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uint32_t blocks; /* number of blocks */
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uint32_t flags;
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uint32_t busconfig;
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uint8_t *buff;
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};
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#define PSRAM_ADDR_PRESENT (1 << 0)
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struct psram_command {
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uint32_t opcode;
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uint32_t addr;
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uint8_t *resp;
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uint32_t flags; /* expected response type */
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uint32_t dummy;
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uint32_t busconfig;
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};
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struct psram_request {
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struct psram_command cmd;
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struct psram_data data;
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};
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struct psram_ctrl;
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extern uint8_t __PSRAM_BASE[];
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extern uint8_t __PSRAM_END[];
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extern uint8_t __PSRAM_LENGTH[];
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extern uint8_t __psram_start__[];
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extern uint8_t __psram_end__[];
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extern uint8_t __psram_data_start__[];
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extern uint8_t __psram_data_end__[];
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extern uint8_t __psram_bss_start__[];
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extern uint8_t __psram_bss_end__[];
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int32_t psram_init(struct psram_chip *chip, struct psram_ctrl *ctrl, PSRAMChip_InitParam *param);
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int32_t psram_deinit(struct psram_chip *chip);
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/**
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* @brief Open psram controller SBUS.
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* @note At the same time, it will disable XIP and suspend schedule.
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* @param None
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* @retval HAL_Status: The status of driver.
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*/
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struct psram_chip *psram_open(uint32_t id);
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/**
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* @brief Close psram controller SBUS.
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* @param None
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* @retval HAL_Status: The status of driver.
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*/
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HAL_Status psram_close(struct psram_chip *chip);
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void psram_info_dump(struct psram_chip *chip);
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#endif /* CONFIG_PSRAM */
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#define RANGEOF_PSRAM(addr, len) \
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((((uint32_t)addr) >= (PSRAM_START_ADDR)) && ((((uint32_t)addr)+(len)) <= (PSRAM_END_ADDR)))
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#endif /* _PSRAM_H */
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