添加内核启动阶段播放声音的驱动
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485e855b5e
commit
2daf93c952
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@ -1457,6 +1457,26 @@
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};
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&codec_has {
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/* external-avcc; */
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/* avcc-supply = <®_aldo1>; */
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avcc-vol = <1800000>; /* uv */
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lineout-vol = <31>;
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mic1gain = <31>;
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mic2gain = <31>;
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adcdelaytime = <0>;
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dma_tx_fifo = <0x02030000>;
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/* lineout-single; */
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/* mic1-single; */
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/* mic2-single; */
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pa-pin-max = <1>; /* set pa */
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pa-pin-0 = <&pio PD 21 1 1 1 0>;
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pa-pin-level-0 = <1>;
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pa-pin-msleep-0 = <0>;
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tx-hub-en;
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rx-sync-en;
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status = "disabled";
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};
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/* audio dirver module -> audio codec */
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&codec {
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@ -1127,6 +1127,7 @@ CONFIG_SUNXI_SYS_INFO=y
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CONFIG_DUMP_REG=y
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CONFIG_DUMP_REG_MISC=y
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# CONFIG_SUNXI_TIMER_TEST is not set
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# CONFIG_HAS_INTERNALCODEC is not set
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# CONFIG_MEM_OPERATION is not set
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# CONFIG_SUNXI_TRANSFORM is not set
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# CONFIG_SUNXI_DI is not set
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@ -1254,6 +1254,7 @@ CONFIG_SUNXI_SYS_INFO=y
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CONFIG_DUMP_REG=y
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CONFIG_DUMP_REG_MISC=y
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# CONFIG_SUNXI_TIMER_TEST is not set
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# CONFIG_HAS_INTERNALCODEC is not set
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CONFIG_MEM_OPERATION=y
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# CONFIG_SUNXI_TRANSFORM is not set
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# CONFIG_SUNXI_DI is not set
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@ -1170,6 +1170,15 @@
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gpr_cur_pos = <6>;
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};
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codec_has:codec_has@0x02030000 {
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#sound-dai-cells = <0>;
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compatible = "has,has-snd-codec";
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reg = <0x0 0x02030000 0x0 0x34C>;
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clocks = <&clk_pll_audio>,
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<&clk_codec_dac>,
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<&clk_codec_adc>;
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status = "disabled";
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};
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/* audio dirver module -> audio codec */
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codec:codec@0x02030000 {
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#sound-dai-cells = <0>;
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@ -596,6 +596,7 @@ source "drivers/char/sunxi-scr/Kconfig"
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source "drivers/char/sunxi-sysinfo/Kconfig"
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source "drivers/char/dump_reg/Kconfig"
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source "drivers/char/timer_test/Kconfig"
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source "drivers/char/hichs-has/Kconfig"
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source "drivers/char/mem_operation/Kconfig"
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source "drivers/char/sunxi_tr/Kconfig"
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source "drivers/char/sunxi-di/Kconfig"
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@ -64,6 +64,7 @@ obj-$(CONFIG_POWERNV_OP_PANEL) += powernv-op-panel.o
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obj-$(CONFIG_ARCH_SUNXI) += sunxi-sysinfo/
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obj-$(CONFIG_SUNXI_TIMER_TEST) += timer_test/
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obj-$(CONFIG_HAS_INTERNALCODEC) += hichs-has/
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obj-$(CONFIG_MEM_OPERATION) += mem_operation/
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obj-$(CONFIG_DUMP_REG) += dump_reg/
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obj-$(CONFIG_SUNXI_TRANSFORM) += sunxi_tr/
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@ -0,0 +1,12 @@
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#
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# Touchscreen driver configuration
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#
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config HAS_INTERNALCODEC
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tristate "play pcm file from Specific partition to internalcodec(DAC) during start up"
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# depends on INPUT && I2C
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default N
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help
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Say Y here if you need to plat sound during start up.
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If unsure, say N.
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@ -0,0 +1,5 @@
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obj-$(CONFIG_HAS_INTERNALCODEC) += has_boot_doorbell.o
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has_boot_doorbell-objs := snd_has_play_sound.o
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,460 @@
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/* sound\soc\sunxi\snd_sun8iw21_codec.h
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* (C) Copyright 2021-2025
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Dby <dby@allwinnertech.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef __SND_HAS_SUN8IW21_CODEC_H
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#define __SND_HAS_SUN8IW21_CODEC_H
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#define SUNXI_DAC_DPC 0x00
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#define SUNXI_DAC_VOL_CTRL 0x04
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#define SUNXI_DAC_FIFOC 0x10
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#define SUNXI_DAC_FIFOS 0x14
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#define SUNXI_DAC_TXDATA 0X20
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#define SUNXI_DAC_CNT 0x24
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#define SUNXI_DAC_DG 0x28
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#define SUNXI_ADC_FIFOC 0x30
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#define SUNXI_ADC_VOL_CTRL 0x34
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#define SUNXI_ADC_FIFOS 0x38
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#define SUNXI_ADC_RXDATA 0x40
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#define SUNXI_ADC_CNT 0x44
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#define SUNXI_ADC_DG 0x4C
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#define SUNXI_ADC_DIG_CTRL 0x50
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#define SUNXI_VRA1SPEEDUP_DOWN_CTRL 0x54
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#define SUNXI_DAC_DAP_CTL 0xF0
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#define SUNXI_ADC_DAP_CTL 0xF8
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#define SUNXI_DAC_DRC_HHPFC 0x100
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#define SUNXI_DAC_DRC_LHPFC 0x104
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#define SUNXI_DAC_DRC_CTRL 0x108
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#define SUNXI_DAC_DRC_LPFHAT 0x10C
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#define SUNXI_DAC_DRC_LPFLAT 0x110
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#define SUNXI_DAC_DRC_RPFHAT 0x114
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#define SUNXI_DAC_DRC_RPFLAT 0x118
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#define SUNXI_DAC_DRC_LPFHRT 0x11C
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#define SUNXI_DAC_DRC_LPFLRT 0x120
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#define SUNXI_DAC_DRC_RPFHRT 0x124
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#define SUNXI_DAC_DRC_RPFLRT 0x128
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#define SUNXI_DAC_DRC_LRMSHAT 0x12C
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#define SUNXI_DAC_DRC_LRMSLAT 0x130
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#define SUNXI_DAC_DRC_RRMSHAT 0x134
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#define SUNXI_DAC_DRC_RRMSLAT 0x138
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#define SUNXI_DAC_DRC_HCT 0x13C
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#define SUNXI_DAC_DRC_LCT 0x140
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#define SUNXI_DAC_DRC_HKC 0x144
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#define SUNXI_DAC_DRC_LKC 0x148
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#define SUNXI_DAC_DRC_HOPC 0x14C
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#define SUNXI_DAC_DRC_LOPC 0x150
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#define SUNXI_DAC_DRC_HLT 0x154
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#define SUNXI_DAC_DRC_LLT 0x158
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#define SUNXI_DAC_DRC_HKI 0x15C
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#define SUNXI_DAC_DRC_LKI 0x160
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#define SUNXI_DAC_DRC_HOPL 0x164
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#define SUNXI_DAC_DRC_LOPL 0x168
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#define SUNXI_DAC_DRC_HET 0x16C
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#define SUNXI_DAC_DRC_LET 0x170
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#define SUNXI_DAC_DRC_HKE 0x174
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#define SUNXI_DAC_DRC_LKE 0x178
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#define SUNXI_DAC_DRC_HOPE 0x17C
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#define SUNXI_DAC_DRC_LOPE 0x180
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#define SUNXI_DAC_DRC_HKN 0x184
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#define SUNXI_DAC_DRC_LKN 0x188
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#define SUNXI_DAC_DRC_SFHAT 0x18C
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#define SUNXI_DAC_DRC_SFLAT 0x190
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#define SUNXI_DAC_DRC_SFHRT 0x194
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#define SUNXI_DAC_DRC_SFLRT 0x198
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#define SUNXI_DAC_DRC_MXGHS 0x19C
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#define SUNXI_DAC_DRC_MXGLS 0x1A0
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#define SUNXI_DAC_DRC_MNGHS 0x1A4
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#define SUNXI_DAC_DRC_MNGLS 0x1A8
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#define SUNXI_DAC_DRC_EPSHC 0x1AC
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#define SUNXI_DAC_DRC_EPSLC 0x1B0
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#define SUNXI_DAC_DRC_OPT 0x1B4
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#define SUNXI_DAC_DRC_HPFHGAIN 0x1B8
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#define SUNXI_DAC_DRC_HPFLGAIN 0x1BC
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#define SUNXI_ADC_DRC_HHPFC 0x200
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#define SUNXI_ADC_DRC_LHPFC 0x204
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#define SUNXI_ADC_DRC_CTRL 0x208
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#define SUNXI_ADC_DRC_LPFHAT 0x20C
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#define SUNXI_ADC_DRC_LPFLAT 0x210
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#define SUNXI_ADC_DRC_RPFHAT 0x214
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#define SUNXI_ADC_DRC_RPFLAT 0x218
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#define SUNXI_ADC_DRC_LPFHRT 0x21C
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#define SUNXI_ADC_DRC_LPFLRT 0x220
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#define SUNXI_ADC_DRC_RPFHRT 0x224
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#define SUNXI_ADC_DRC_RPFLRT 0x228
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#define SUNXI_ADC_DRC_LRMSHAT 0x22C
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#define SUNXI_ADC_DRC_LRMSLAT 0x230
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#define SUNXI_ADC_DRC_HCT 0x23C
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#define SUNXI_ADC_DRC_LCT 0x240
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#define SUNXI_ADC_DRC_HKC 0x244
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#define SUNXI_ADC_DRC_LKC 0x248
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#define SUNXI_ADC_DRC_HOPC 0x24C
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#define SUNXI_ADC_DRC_LOPC 0x250
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#define SUNXI_ADC_DRC_HLT 0x254
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#define SUNXI_ADC_DRC_LLT 0x258
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#define SUNXI_ADC_DRC_HKI 0x25C
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#define SUNXI_ADC_DRC_LKI 0x260
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#define SUNXI_ADC_DRC_HOPL 0x264
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#define SUNXI_ADC_DRC_LOPL 0x268
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#define SUNXI_ADC_DRC_HET 0x26C
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#define SUNXI_ADC_DRC_LET 0x270
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#define SUNXI_ADC_DRC_HKE 0x274
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#define SUNXI_ADC_DRC_LKE 0x278
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#define SUNXI_ADC_DRC_HOPE 0x27C
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#define SUNXI_ADC_DRC_LOPE 0x280
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#define SUNXI_ADC_DRC_HKN 0x284
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#define SUNXI_ADC_DRC_LKN 0x288
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#define SUNXI_ADC_DRC_SFHAT 0x28C
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#define SUNXI_ADC_DRC_SFLAT 0x290
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#define SUNXI_ADC_DRC_SFHRT 0x294
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#define SUNXI_ADC_DRC_SFLRT 0x298
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#define SUNXI_ADC_DRC_MXGHS 0x29C
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#define SUNXI_ADC_DRC_MXGLS 0x2A0
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#define SUNXI_ADC_DRC_MNGHS 0x2A4
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#define SUNXI_ADC_DRC_MNGLS 0x2A8
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#define SUNXI_ADC_DRC_EPSHC 0x2AC
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#define SUNXI_ADC_DRC_EPSLC 0x2B0
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#define SUNXI_ADC_DRC_OPT 0x2B4
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#define SUNXI_ADC_DRC_HPFHGAIN 0x2B8
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#define SUNXI_ADC_DRC_HPFLGAIN 0x2BC
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#define SUNXI_AC_VERSION 0x2C0
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/* Analog register */
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#define SUNXI_ADC1_REG 0x300
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#define SUNXI_ADC2_REG 0x304
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#define SUNXI_DAC_REG 0x310
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#define SUNXI_MICBIAS_REG 0x318
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#define SUNXI_RAMP_REG 0x31C /* only set bit[1] at init */
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#define SUNXI_BIAS_REG 0x320
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#define SUNXI_POWER_REG 0x348
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#define SUNXI_ADC_CUR_REG 0x34C
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#define SUNXI_CODEC_REG_MAX SUNXI_ADC_CUR_REG
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/* SUNXI_DAC_DPC:0x00 */
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#define EN_DAC 31
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#define MODQU 25
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#define DWA_EN 24
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#define HPF_EN 18
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#define DVOL 12
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#define DAC_HUB_EN 0
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/* SUNXI_DAC_VOL_CTRL:0x04 */
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#define DAC_VOL_SEL 16
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#define DAC_VOL_L 8
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#define DAC_VOL_R 0
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/* SUNXI_DAC_FIFOC:0x10 */
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#define DAC_FS 29
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#define FIR_VER 28
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#define SEND_LASAT 26
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#define FIFO_MODE 24
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#define DAC_DRQ_CLR_CNT 21
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#define TX_TRIG_LEVEL 8
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#define DAC_MONO_EN 6
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#define TX_SAMPLE_BITS 5
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#define DAC_DRQ_EN 4
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#define DAC_IRQ_EN 3
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#define FIFO_UNDERRUN_IRQ_EN 2
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#define FIFO_OVERRUN_IRQ_EN 1
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#define FIFO_FLUSH 0
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/* SUNXI_DAC_FIFOS:0x14 */
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#define TX_EMPTY 23
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#define DAC_TXE_CNT 8
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#define DAC_TXE_INT 3
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#define DAC_TXU_INT 2
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#define DAC_TXO_INT 1
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/* SUNXI_DAC_DG:0x28 */
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#define DAC_MODU_SEL 11
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#define DAC_PATTERN_SEL 9
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#define DAC_CODEC_CLK_SEL 8
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#define DAC_SWP 6
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#define ADDA_LOOP_MODE 0
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/* SUNXI_ADC_FIFOC:0x30 */
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#define ADC_FS 29
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#define EN_AD 28
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#define ADCFDT 26
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#define ADCDFEN 25
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#define RX_FIFO_MODE 24
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#define RX_SYNC_EN_START 21
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#define RX_SYNC_EN 20
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#define RX_SAMPLE_BITS 16
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#define RX_FIFO_TRG_LEVEL 4
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#define ADC_DRQ_EN 3
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#define ADC_IRQ_EN 2
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#define ADC_OVERRUN_IRQ_EN 1
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#define ADC_FIFO_FLUSH 0
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/* SUNXI_ADC_VOL_CTRL:0x34 */
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#define ADC2_VOL 8
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#define ADC1_VOL 0
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/* SUNXI_ADC_FIFOS:0x38 */
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#define RXA 23
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#define ADC_RXA_CNT 8
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#define ADC_RXA_INT 3
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#define ADC_RXO_INT 1
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/* SUNXI_ADC_DG:0x4C */
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#define AD_SWP1 24
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/* SUNXI_ADC_DIG_CTRL:0x50 */
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#define ADC1_2_VOL_EN 16
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#define ADC2_CHANNEL_EN 1
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#define ADC1_CHANNEL_EN 0
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#define ADC_CHANNEL_EN 0
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/* SUNXI_VRA1SPEEDUP_DOWN_CTRL:0x54 */
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#define VRA1SPEEDUP_DOWN_STATE 4
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#define VRA1SPEEDUP_DOWN_CTRL 1
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#define VRA1SPEEDUP_DOWN_RST_CTRL 0
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/* SUNXI_DAC_DAP_CTL:0xf0 */
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#define DDAP_EN 31
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#define DDAP_DRC_EN 29
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#define DDAP_HPF_EN 28
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/* SUNXI_ADC_DAP_CTL:0xf8 */
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#define ADC_DAP0_EN 31
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#define ADC_DRC0_EN 29
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#define ADC_HPF0_EN 28
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#define ADC_DAP1_EN 27
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#define ADC_DRC1_EN 25
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#define ADC_HPF1_EN 24
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/* SUNXI_DAC_DRC_HHPFC: 0x100*/
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#define DAC_HHPF_CONF 0
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/* SUNXI_DAC_DRC_LHPFC: 0x104*/
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#define DAC_LHPF_CONF 0
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/* SUNXI_DAC_DRC_CTRL: 0x108*/
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#define DAC_DRC_DELAY_OUT_STATE 15
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#define DAC_DRC_SIGNAL_DELAY 8
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#define DAC_DRC_DELAY_BUF_EN 7
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#define DAC_DRC_GAIN_MAX_EN 6
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#define DAC_DRC_GAIN_MIN_EN 5
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#define DAC_DRC_NOISE_DET_EN 4
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#define DAC_DRC_SIGNAL_SEL 3
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#define DAC_DRC_DELAY_EN 2
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#define DAC_DRC_LT_EN 1
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#define DAC_DRC_ET_EN 0
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/* SUNXI_ADC_DRC_HHPFC: 0x200*/
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#define ADC_HHPF_CONF 0
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/* SUNXI_ADC_DRC_LHPFC: 0x204*/
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#define ADC_LHPF_CONF 0
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/* SUNXI_ADC_DRC_CTRL: 0x208*/
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#define ADC_DRC_DELAY_OUT_STATE 15
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#define ADC_DRC_SIGNAL_DELAY 8
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#define ADC_DRC_DELAY_BUF_EN 7
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#define ADC_DRC_GAIN_MAX_EN 6
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#define ADC_DRC_GAIN_MIN_EN 5
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#define ADC_DRC_NOISE_DET_EN 4
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#define ADC_DRC_SIGNAL_SEL 3
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#define ADC_DRC_DELAY_EN 2
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#define ADC_DRC_LT_EN 1
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#define ADC_DRC_ER_EN 0
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/* SUNXI_DAC_DRC_HHPFC: 0x100*/
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#define DAC_HHPF_CONF 0
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/* SUNXI_DAC_DRC_LHPFC: 0x104*/
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#define DAC_LHPF_CONF 0
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/* SUNXI_ADC_DRC_HHPFC: 0x200*/
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#define ADC_HHPF_CONF 0
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/* SUNXI_ADC_DRC_LHPFC: 0x204*/
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#define ADC_LHPF_CONF 0
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/* SUNXI_ADC1_REG : 0x300 */
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#define ADC1_EN 31
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#define MIC1_PGA_EN 30
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#define ADC1_DITHER_CTRL 29
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#define MIC1_SIN_EN 28
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#define FMINLEN 27
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#define FMINLG 26
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#define ADC1_DSM_DITHER_LVL 24
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#define LINEINLEN 23
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#define LINEINLG 22
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#define ADC1_IOPBUFFER 20
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#define ADC1_PGA_CTRL_RCM 18
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#define ADC1_PGA_IN_VCM_CTRL 16
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#define ADC1_2_CURRENT_SEL 14
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#define ADC1_SINGLE_NOISE_CTL 13
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#define ADC1_PGA_GAIN_CTRL 8
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#define ADC1_IOPAAF 6
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#define ADC1_IOPSDM1 4
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||||
#define ADC1_IOPSDM2 2
|
||||
#define ADC1_IOPMIC 0
|
||||
|
||||
/* SUNXI_ADC2_REG : 0x304 */
|
||||
#define ADC2_EN 31
|
||||
#define MIC2_PGA_EN 30
|
||||
#define ADC2_DITHER_CTRL 29
|
||||
#define MIC2_SIN_EN 28
|
||||
#define FMINREN 27
|
||||
#define FMINRG 26
|
||||
#define ADC2_DSM_DITHER_LVL 24
|
||||
#define LINEINREN 23
|
||||
#define LINEINRG 22
|
||||
#define ADC2_IOPBUFFER 20
|
||||
#define ADC2_PGA_CTRL_RCM 18
|
||||
#define ADC2_PGA_IN_VCM_CTRL 16
|
||||
#define ADC2_SINGLE_NOISE_CTL 13
|
||||
#define ADC2_PGA_GAIN_CTRL 8
|
||||
#define ADC2_IOPAAF 6
|
||||
#define ADC2_IOPSDM1 4
|
||||
#define ADC2_IOPSDM2 2
|
||||
#define ADC2_IOPMIC 0
|
||||
|
||||
/* SUNXI_DAC_REG : 0x310 */
|
||||
#define P_CURRENT_TEST_SELECT 24
|
||||
#define N_CURRENT_TEST_SELECT 22
|
||||
#define VRA2_IOPVRS 20
|
||||
#define ILINEOUTAMPS 18
|
||||
#define IOPDACS 16
|
||||
#define DACLEN 15
|
||||
#define LINEOUTLEN 13
|
||||
#define DACLMUTE 12
|
||||
#define VRA2_OPVR_OI_CTRL 7
|
||||
#define LINEOUTLDIFFEN 6
|
||||
#define LINEOUT_VOL 0
|
||||
|
||||
/* SUNXI_MICBIAS_REG : 0x318 */
|
||||
#define MMICBIASEN 7
|
||||
#define MBIASSEL 5
|
||||
#define MMICBIAS_CHOP_EN 4
|
||||
#define MMICBIAS_CHOP_CLK_SEL 2
|
||||
|
||||
/* SUNXI_RAMP_REG : 0x31C */
|
||||
#define RMC_EN 1
|
||||
|
||||
/* SUNXI_BIAS_REG : 0x320 */
|
||||
#define AC_BIASDATA 0
|
||||
|
||||
/* SUNXI_POWER_REG :0x348 */
|
||||
#define ALDO_EN 31
|
||||
#define VAR1SPEEDUP_DOWN_FURTHER_CTRL 29
|
||||
#define BG_BUFFER_DISABLE 15
|
||||
#define ALDO_OUTPUT_VOLTAGE 12
|
||||
#define BG_ROUGH_TRIM 8
|
||||
#define BG_FINE_TRIM 0
|
||||
|
||||
/* SUNXI_ADC_CUR_REG :0x34C */
|
||||
#define ADC2_IOPMIC2 12
|
||||
#define ADC2_OP_MIC1_CUR 10
|
||||
#define ADC2_OP_MIC2_CUR 8
|
||||
#define ADC1_IOPMIC2 4
|
||||
#define ADC1_OP_MIC1_CUR 2
|
||||
#define ADC1_OP_MIC2_CUR 0
|
||||
|
||||
struct sunxi_has_clk {
|
||||
struct clk *pllaudio;
|
||||
struct clk *dacclk;
|
||||
struct clk *adcclk;
|
||||
};
|
||||
|
||||
struct sunxi_regulator {
|
||||
bool external_avcc;
|
||||
unsigned int avcc_vol;
|
||||
struct regulator *avcc;
|
||||
};
|
||||
|
||||
struct sunxi_has_dts {
|
||||
unsigned int lineout_vol;
|
||||
unsigned int mic1gain;
|
||||
unsigned int mic2gain;
|
||||
unsigned int adc_dtime;
|
||||
bool lineout_single; /* true: single mode; false: differ mode */
|
||||
bool mic1_single;
|
||||
bool mic2_single;
|
||||
|
||||
/* tx_hub */
|
||||
bool tx_hub_en;
|
||||
|
||||
/* components func -> rx sync */
|
||||
bool rx_sync_en; /* read from dts */
|
||||
bool rx_sync_ctl;
|
||||
int rx_sync_id;
|
||||
// rx_sync_domain_t rx_sync_domain;
|
||||
};
|
||||
|
||||
struct sunxi_dap {
|
||||
unsigned int dap_enable;
|
||||
struct mutex mutex;
|
||||
};
|
||||
|
||||
// struct sunxi_codec_runtime {
|
||||
// /* input: micin and linein have common parts, need manage */
|
||||
// unsigned int mic1gain;
|
||||
// unsigned int mic2gain;
|
||||
// bool mic1_single;
|
||||
// bool mic2_single;
|
||||
|
||||
// unsigned int lineinlgain;
|
||||
// unsigned int lineinrgain;
|
||||
|
||||
// bool mic1_run;
|
||||
// bool mic2_run;
|
||||
// bool linein_run;
|
||||
|
||||
// struct mutex input_mutex;
|
||||
|
||||
// /* output: only lineout, unneed manage. */
|
||||
// };
|
||||
|
||||
// enum SUNXI_kCONTROL_SHIFT {
|
||||
// KCONTROL_SHIFT_MIC1_GAIN = 0,
|
||||
// KCONTROL_SHIFT_MIC2_GAIN,
|
||||
// KCONTROL_SHIFT_LINEINL_GAIN,
|
||||
// KCONTROL_SHIFT_LINEINR_GAIN,
|
||||
// };
|
||||
|
||||
// enum SUNXI_WIDGET_SHIFT {
|
||||
// WIDGET_SHIFT_ADC1 = 0,
|
||||
// WIDGET_SHIFT_ADC2,
|
||||
// WIDGET_SHIFT_MIC1_INPUT_SELECT,
|
||||
// WIDGET_SHIFT_MIC2_INPUT_SELECT,
|
||||
// WIDGET_SHIFT_MIC1_GAIN,
|
||||
// WIDGET_SHIFT_MIC2_GAIN,
|
||||
// WIDGET_SHIFT_LINEINL_GAIN,
|
||||
// WIDGET_SHIFT_LINEINR_GAIN,
|
||||
// };
|
||||
|
||||
// struct sunxi_codec {
|
||||
// struct platform_device *pdev;
|
||||
|
||||
// struct sunxi_has_mem mem;
|
||||
// struct sunxi_clk clk;
|
||||
// struct sunxi_regulator rglt;
|
||||
// // struct sunxi_dts dts;
|
||||
// struct sunxi_dap dac_dap;
|
||||
// struct sunxi_dap adc_dap;
|
||||
|
||||
// unsigned int pa_pin_max;
|
||||
// struct pa_config *pa_config;
|
||||
|
||||
// struct sunxi_codec_runtime runtime;
|
||||
// };
|
||||
|
||||
#endif /* __SND_HAS_SUN8IW21_CODEC_H */
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/* sound\soc\sunxi\snd_sunxi_common.h
|
||||
* (C) Copyright 2021-2025
|
||||
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
|
||||
* Dby <dby@allwinnertech.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __SND_HAS_SUNXI_COMMON_H
|
||||
#define __SND_HAS_SUNXI_COMMON_H
|
||||
|
||||
/* for regmap */
|
||||
struct sunxi_has_mem {
|
||||
char *dev_name;
|
||||
struct resource *res;
|
||||
struct regmap_config *regmap_config;
|
||||
|
||||
void __iomem *membase;
|
||||
struct resource *memregion;
|
||||
struct regmap *regmap;
|
||||
};
|
||||
|
||||
// int snd_sunxi_mem_init(struct platform_device *pdev, struct sunxi_mem *mem);
|
||||
// void snd_sunxi_mem_exit(struct platform_device *pdev, struct sunxi_mem *mem);
|
||||
|
||||
// /* for reg debug */
|
||||
// #define REG_LABEL(constant) {#constant, constant, 0}
|
||||
// #define REG_LABEL_END {NULL, 0, 0}
|
||||
|
||||
struct reg_label {
|
||||
const char *name;
|
||||
const unsigned int address;
|
||||
unsigned int value;
|
||||
};
|
||||
|
||||
// int snd_sunxi_save_reg(struct regmap *regmap, struct reg_label *reg_labels);
|
||||
// int snd_sunxi_echo_reg(struct regmap *regmap, struct reg_label *reg_labels);
|
||||
|
||||
/* for pa config */
|
||||
struct has_pa_config {
|
||||
u32 pin;
|
||||
u32 msleep;
|
||||
bool used;
|
||||
bool level;
|
||||
};
|
||||
|
||||
// struct pa_config *snd_sunxi_pa_pin_init(struct platform_device *pdev, u32 *pa_pin_max);
|
||||
// void snd_sunxi_pa_pin_exit(struct platform_device *pdev, struct pa_config *pa_cfg, u32 pa_pin_max);
|
||||
// int snd_sunxi_pa_pin_enable(struct pa_config *pa_cfg, u32 pa_pin_max);
|
||||
// int snd_sunxi_pa_pin_disable(struct pa_config *pa_cfg, u32 pa_pin_max);
|
||||
|
||||
#endif /* __SND_HAS_SUNXI_COMMON_H */
|
||||
Loading…
Reference in New Issue