添加boot0获取唤醒源

This commit is contained in:
2025-02-24 17:04:54 +08:00
parent b10824bc07
commit 47d6d64341
5 changed files with 152 additions and 1 deletions

View File

@@ -22,8 +22,87 @@
static serial_hw_t *serial_ctrl_base;
#ifdef CFG_GET_WKSRC
static serial_hw_t *serial_ctrl_M0_base;
#define M0_UART_BAUD 9600
void sunxi_serial_M0_init(int uart_port, void *gpio_cfg, int gpio_max)
{
u32 uart_clk;
void __iomem *uart0_base = sunxi_get_iobase(SUNXI_UART0_BASE);
#ifdef FPGA_PLATFORM
normal_gpio_set_t fpga_uart_gpio[2] = {
{2, 9, 3, 1, 1, 0, {0} }, /* PB9: 3--RX */
{2, 8, 3, 1, 1, 0, {0} }, /* PB8: 3--TX */
};
#endif
sunxi_clock_init_uart(uart_port);
/* gpio */
#ifdef FPGA_PLATFORM
boot_set_gpio(fpga_uart_gpio, gpio_max, 1);
#else
boot_set_gpio(gpio_cfg, gpio_max, 1);
#endif
/* uart init */
serial_ctrl_M0_base = (serial_hw_t *)(uart0_base + uart_port * CCM_UART_ADDR_OFFSET);
serial_ctrl_M0_base->mcr = 0x3;
uart_clk = (24000000 + 8 * M0_UART_BAUD)/(16 * M0_UART_BAUD);
serial_ctrl_M0_base->lcr |= 0x80;
serial_ctrl_M0_base->dlh = uart_clk>>8;
serial_ctrl_M0_base->dll = uart_clk&0xff;
serial_ctrl_M0_base->lcr &= ~0x80;
serial_ctrl_M0_base->lcr = ((PARITY&0x03)<<3) | ((STOP&0x01)<<2) | (DLEN&0x03);
serial_ctrl_M0_base->fcr = 0x7;
return;
}
int has_sunxi_serial_M0_send(unsigned char *buff, size_t len)
{
u32 start= 0;
int i;
for (i = 0; i < len; i++)
{
start = get_sys_ticks();
while ((serial_ctrl_M0_base->lsr & (1 << 6)) == 0)
{
if (get_sys_ticks() - start > 30)
{
pr_emerg("can't send cmd\n");
return -1;
}
}
serial_ctrl_M0_base->thr = buff[i];
}
return i;
}
int has_sunxi_serial_M0_get(unsigned char *buff, size_t len)
{
u32 start= 0;
int i;
for (i = 0; i < len; i++)
{
start = get_sys_ticks();
while ((serial_ctrl_M0_base->lsr & 1) == 0)
{
if (get_sys_ticks() - start > 30)
{
pr_emerg("can't get wksrc\n");
return -1;
}
}
buff[i] = serial_ctrl_M0_base->rbr;
}
return i;
}
#endif
void sunxi_serial_init(int uart_port, void *gpio_cfg, int gpio_max)
{
u32 uart_clk;