添加boot0获取唤醒源

lichee/brandy-2.0/spl/board/sun8iw21p1/commonfastboot_sl100_front.mk

@@ -28,5 +28,8 @@ CFG_RISCV_E907=y
 CFG_SUNXI_ELF=y
 CFG_MELISELF_LOAD_ADDR=0x43080000
 
+#get wakeup source from M0
+CFG_GET_WKSRC=y
+CFG_WKSRC_ADDR=0x4307F000
 #E907 interrupt table info update
 #CFG_UPDATA_IRQ_TAB=y

lichee/brandy-2.0/spl/drivers/serial.c

@@ -22,8 +22,87 @@
 
 
 static serial_hw_t *serial_ctrl_base;
+#ifdef CFG_GET_WKSRC
+static serial_hw_t *serial_ctrl_M0_base;
 
 
+#define M0_UART_BAUD 9600
+
+void sunxi_serial_M0_init(int uart_port, void *gpio_cfg, int gpio_max)
+{
+	u32 uart_clk;
+	void __iomem *uart0_base = sunxi_get_iobase(SUNXI_UART0_BASE);
+
+#ifdef FPGA_PLATFORM
+	normal_gpio_set_t fpga_uart_gpio[2] = {
+	    {2, 9, 3, 1, 1, 0, {0} }, /* PB9: 3--RX */
+	    {2, 8, 3, 1, 1, 0, {0} }, /* PB8: 3--TX */
+	};
+#endif
+
+	sunxi_clock_init_uart(uart_port);
+	/* gpio */
+#ifdef FPGA_PLATFORM
+	boot_set_gpio(fpga_uart_gpio, gpio_max, 1);
+#else
+	boot_set_gpio(gpio_cfg, gpio_max, 1);
+#endif
+	/* uart init */
+	serial_ctrl_M0_base = (serial_hw_t *)(uart0_base + uart_port * CCM_UART_ADDR_OFFSET);
+
+	serial_ctrl_M0_base->mcr = 0x3;
+	uart_clk = (24000000 + 8 * M0_UART_BAUD)/(16 * M0_UART_BAUD);
+	serial_ctrl_M0_base->lcr |= 0x80;
+	serial_ctrl_M0_base->dlh = uart_clk>>8;
+	serial_ctrl_M0_base->dll = uart_clk&0xff;
+	serial_ctrl_M0_base->lcr &= ~0x80;
+	serial_ctrl_M0_base->lcr = ((PARITY&0x03)<<3) | ((STOP&0x01)<<2) | (DLEN&0x03);
+	serial_ctrl_M0_base->fcr = 0x7;
+
+	return;
+}
+
+int has_sunxi_serial_M0_send(unsigned char *buff, size_t len)
+{
+	u32 start= 0;
+	int i;
+	for (i = 0; i < len; i++)
+	{
+		start = get_sys_ticks();
+		while ((serial_ctrl_M0_base->lsr & (1 << 6)) == 0)
+		{
+			if (get_sys_ticks() - start > 30)
+			{
+				pr_emerg("can't send cmd\n");
+				return -1;
+			}
+		}
+		serial_ctrl_M0_base->thr = buff[i];
+	}
+	return i;
+}
+
+int has_sunxi_serial_M0_get(unsigned char *buff, size_t len)
+{
+	u32 start= 0;
+	int i;
+	for (i = 0; i < len; i++)
+	{
+		start = get_sys_ticks();
+		while ((serial_ctrl_M0_base->lsr & 1) == 0)
+		{
+			if (get_sys_ticks() - start > 30)
+			{
+				pr_emerg("can't get wksrc\n");
+				return -1;
+			}
+		}
+		buff[i] = serial_ctrl_M0_base->rbr;
+	}
+	return i;
+}
+#endif
+
 void sunxi_serial_init(int uart_port, void *gpio_cfg, int gpio_max)
 {
 	u32 uart_clk;

lichee/brandy-2.0/spl/include/arch/gpio_new.h

@@ -3,6 +3,10 @@
 
 #include <arch/gpio.h>
 
+#ifdef CFG_SET_BACKLIGHT
+#define CFG_SET_GPIO_NEW 1
+#endif
+
 #define OUPUT_HIGH_LEVEL (1)
 #define OUPUT_LOW_LEVEL	 (0)
 #define PORT_NO_USE	 (0xFF)

lichee/brandy-2.0/spl/include/arch/uart.h

@@ -40,6 +40,11 @@ typedef struct serial_hw
 /* Data Length: 0 - 5bits; 1 - 6bits; 2 - 7bits; 3 - 8bit */
 #define   DLEN         3 
 
+#ifdef CFG_GET_WKSRC
+void sunxi_serial_M0_init(int uart_port, void *gpio_cfg, int gpio_max);
+int has_sunxi_serial_M0_send(unsigned char *buff, size_t len);
+int has_sunxi_serial_M0_get(unsigned char *buff, size_t len);
+#endif
 
 void sunxi_serial_init(int uart_port, void *gpio_cfg, int gpio_max);
 void sunxi_serial_putc (char c);

lichee/brandy-2.0/spl/nboot/main/boot0_main.c

@@ -13,6 +13,9 @@
 #include <arch/dram.h>
 #include <arch/rtc.h>
 #include <arch/gpio.h>
+#ifdef CFG_SET_BACKLIGHT
+#include <arch/gpio_new.h>
+#endif
 #include <board_helper.h>
 #include <config.h>
 #include <boot_param.h>
@@ -41,8 +44,19 @@ void main(void)
 				rtos_base = 0, opensbi_base = 0, cpus_rtos_base = 0;
 	u16 pmu_type = 0, key_input = 0; /* TODO: set real value */
 
+#ifdef CFG_SET_BACKLIGHT
+	normal_gpio_set_t gpio_bl;
+#endif
+#ifdef CFG_GET_WKSRC
+	normal_gpio_cfg M0_uart_gpio[2];
+	/* has_get_wksrc[10] = 0; 默认唤醒源是0 */
+	u8 has_get_wksrc[11] = {0xaa, 0x55, 0xaa, 0x55, 0x0e, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00}; // has get wake up source, len is 11
+#ifdef CFG_WKSRC_ADDR
+	u8 *buff;
+#endif
+#endif
 	sunxi_board_init_early();
-	sunxi_serial_init(BT0_head.prvt_head.uart_port, (void *)BT0_head.prvt_head.uart_ctrl, 6);
+	sunxi_serial_init(BT0_head.prvt_head.uart_port, (void *)BT0_head.prvt_head.uart_ctrl, 2);
 	print_commit_log();
 
 	status = sunxi_board_init();
@@ -60,10 +74,46 @@ void main(void)
 #endif
 	}
 
+#ifdef CFG_SET_BACKLIGHT
+	/* gpio back light */
+	gpio_bl.port = SUNXI_GPIO_D; /*使用PD口*/
+	gpio_bl.port_num = 20; /*端口为20口*/
+	gpio_bl.mul_sel = SUNXI_GPIO_OUTPUT; /*配置为输出模式*/
+	gpio_bl.pull = SUNXI_GPIO_PULL_DISABLE; /*不配置默认上下拉*/
+	gpio_bl.drv_level  = SUNXI_GPIO_DRV_LEVEL1; /*输出等级为1级*/
+	gpio_bl.data = 1; /*默认输出high电平*/
+	// gpio_bl.data = 0; /*默认输出low电平*/
+
+	if (boot_set_gpio_new(&gpio_bl, 1, 1) < 0)
+	{
+		pr_emerg("boot_set_gpio error\n");
+	}
+#endif
+#ifdef CFG_GET_WKSRC
+	/* init uart for M0 */
+	M0_uart_gpio[0] = BT0_head.prvt_head.uart_ctrl[0];
+	M0_uart_gpio[0].port = SUNXI_GPIO_D + 1; // ZZP:using API without _new needs to +1, please ref macro:PIO_REG_CFG
+	M0_uart_gpio[0].port_num = 18;
+	M0_uart_gpio[0].mul_sel = 7; // Multiplex funciton
+	M0_uart_gpio[1] = BT0_head.prvt_head.uart_ctrl[1];
+	M0_uart_gpio[1].port =  SUNXI_GPIO_D + 1;
+	M0_uart_gpio[1].port_num = 19;
+	M0_uart_gpio[1].mul_sel = 7;
+	sunxi_serial_M0_init(2, (void *)M0_uart_gpio, 2); // UART2 
+	if (has_sunxi_serial_M0_send(has_get_wksrc, sizeof(has_get_wksrc)) == sizeof(has_get_wksrc))
+	{
+		if (has_sunxi_serial_M0_get(has_get_wksrc, sizeof(has_get_wksrc)) != sizeof(has_get_wksrc))
+		{
+			has_get_wksrc[10] = 0; // 默认唤醒源是0
+		}
+	}
+	// pr_emerg("wksrc:%d\n", has_get_wksrc[10]);
+#else
 	if (BT0_head.prvt_head.enable_jtag) {
 		printf("enable_jtag\n");
 		boot_set_gpio((normal_gpio_cfg *)BT0_head.prvt_head.jtag_gpio, 5, 1);
 	}
+#endif
 
 	char uart_input_value = get_uart_input(); /* Prevent DRAM jamming */
 	if (uart_input_value == '2') {
@@ -88,6 +138,7 @@ void main(void)
 	handler_super_standby();
 #endif
 
+#ifndef CFG_GET_WKSRC
 	uart_input_value = get_uart_input();
 	if (uart_input_value == '2') {
 		sunxi_set_printf_debug_mode(3, 0);
@@ -100,6 +151,7 @@ void main(void)
 		printf("detected user input q\n");
 		sunxi_set_printf_debug_mode(0, 1);
 	}
+#endif
 
 	mmu_enable(dram_size);
 	malloc_init(CONFIG_HEAP_BASE, CONFIG_HEAP_SIZE);
@@ -123,6 +175,14 @@ void main(void)
 	update_uboot_info(uboot_base, optee_base, monitor_base, rtos_base, dram_size,
 			pmu_type, uart_input_value, key_input);
 
+#ifdef CFG_GET_WKSRC
+#ifdef CFG_WKSRC_ADDR
+	/* must operate after dram init */
+	buff = (u8 *)CFG_WKSRC_ADDR;
+	buff[0] = has_get_wksrc[10];
+#endif
+#endif
+
 #if CFG_BOOT0_LOAD_KERNEL
 	exist_uboot_jmp_cardproduct(uboot_base);
 	void load_and_run_kernel(u32 optee_base, u32 opensbi_base, u32 monitor_base);