/* SPDX-License-Identifier: GPL-2.0*/
#ifndef __NAND_LIB_CFG_H__
#define __NAND_LIB_CFG_H__

#include "../../aw_nand_type.h"


/*
 * define in nand_boot.h
 *#define NAND_BOOT0_PAGE_CNT_PER_COPY 64
 *#define NAND_BOOT0_PAGE_CNT_PER_COPY_2 128
 *#define NAND_BOOT0_PAGE_CNT_PER_COPY_4 256 //A50 boot0 size >= 128K
 */

/*boot0 size refer to brom, need consistent with brom configuration*/
#if defined(CONFIG_ARCH_SUN8IW18) || defined(CONFIG_ARCH_SUN50IW11)
#define NAND_BOOT0_PAGE_CNT_PER_COPY	NAND_BOOT0_PAGE_CNT_PER_COPY_4
#else
#define NAND_BOOT0_PAGE_CNT_PER_COPY	NAND_BOOT0_PAGE_CNT_PER_COPY_2
#endif


struct nand_cfg {
	unsigned int phy_interface_cfg;

	unsigned int phy_support_two_plane;
	unsigned int phy_nand_support_vertical_interleave;
	unsigned int phy_support_dual_channel;

	unsigned int phy_wait_rb_before;
	unsigned int phy_wait_rb_mode;
	unsigned int phy_wait_dma_mode;
};

extern struct nand_cfg *g_phy_cfg;

#define PHY_ONLY_TOG_AND_SDR 1

#define PHY_WAIT_RB_BEFORE 1
#define PHY_WAIT_RB_INTERRUPT 1
#if defined(CONFIG_ARCH_SUN8IW18)
#define PHY_WAIT_DMA_INTERRUPT 0 //((wait_dma_int == 1) ? 1 : 0)
#else
#define PHY_WAIT_DMA_INTERRUPT 1 //((wait_dma_int == 1) ? 1 : 0)
#endif

#define SUPPORT_UPDATE_EXTERNAL_ACCESS_FREQ (1)

#define SUPPORT_CHANGE_ONFI_TIMING_MODE (1)

#define SUPPORT_SCAN_EDO_FOR_SDR_NAND (0)
#define GOOD_DDR_EDO_DELAY_CHAIN_TH (7)

#define MAX_SECTORS_PER_PAGE_FOR_TWO_PLANE (32)

/****************************************************************************
*Single channel needs to be affixed to the same kind of flashdddd
*Dual channel needs to be affixed to  the same number and type of flash
*
*Single channel
*1.support two-plane
*2.support vertical_interleave
*3.if superpage>32k two-plane not supported
*4.vertical_interleave chip pairing with different rb in the channel
*
*Dual channel
*1.support two-plane
*2.support dual_channel
*3.support vertical_interleave
*4.if superpage>32k two-plane not supported
*5.dual_channel chip pairing with same chip number between the channel
86.vertical_interleave chip pairing with different rb in the channel
*****************************************************************************/
#define PHY_SUPPORT_TWO_PLANE 1
#define PHY_SUPPORT_VERTICAL_INTERLEAVE 1
#define PHY_SUPPORT_DUAL_CHANNEL 1

//#define  NAND_VERSION                 0x0223
//#define  NAND_DRV_DATE                  0x20150312

#define SUPPORT_UPDATE_EXTERNAL_ACCESS_FREQ (1)

#define SUPPORT_CHANGE_ONFI_TIMING_MODE (1)

#define SUPPORT_SCAN_EDO_FOR_SDR_NAND (0)
#define GOOD_DDR_EDO_DELAY_CHAIN_TH (7)

#define MAX_SECTORS_PER_PAGE_FOR_TWO_PLANE (32)

int nand_cfg_interface(void);
int nand_wait_rb_before(void);
int nand_wait_rb_mode(void);
int nand_wait_dma_mode(void);
int nand_support_two_plane(void);
int nand_support_vertical_interleave(void);
int nand_support_dual_channel(void);

#endif /*NAND_LIB_CFG_H*/