/*
 * Allwinner Technology CO., Ltd. sun50iw10p1 platform
 *
 * modify base on juno.dts
 */

/memreserve/ 0x48000000 0x01000000; /* atf */
/memreserve/ 0x48100000 0x00100000; /* arisc dram space */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/display/lcd_command.h>
#include "sun50iw10p1-clk.dtsi"
#include "sun50iw10p1-pinctrl.dtsi"
#include <dt-bindings/thermal/thermal.h>
/ {
	model = "sun50iw10";
	compatible = "arm,sun50iw10p1";
	interrupt-parent = <&wakeupgen>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		serial6 = &uart6;
		serial7 = &uart7;
		ir0 = &s_cir0;
		ir1 = &ir1;
		twi0 = &twi0;
		twi1 = &twi1;
		twi2 = &twi2;
		twi3 = &twi3;
		twi4 = &twi4;
		twi5 = &twi5;
		twi6 = &twi6;
		twi7 = &twi7;
		spi0 = &spi0;
		spi1 = &spi1;
		spi2 = &spi2;
		ledc = &ledc;
		pcie = &pcie;
		gmac0 = &gmac0;
		gmac1 = &gmac1;

		global_timer0  = &soc_timer0;
		mmc0 = &sdc0;
		mmc2 = &sdc2;
		nand0 =&nand0;
		disp = &disp;
		eink = &eink;
		tps65185 = &tps65185;
		tps65185_slave = &tps65185_slave;
		lcd0 = &lcd0;
		lcd1 = &lcd1;
		pwm = &pwm;
		pwm0 = &pwm0;
		pwm1 = &pwm1;
		pwm2 = &pwm2;
		pwm3 = &pwm3;
		pwm4 = &pwm4;
		pwm5 = &pwm5;
		pwm6 = &pwm6;
		pwm7 = &pwm7;
		pwm8 = &pwm8;
		pwm9 = &pwm9;
		pwm10 = &pwm10;
		pwm11 = &pwm11;
		pwm12 = &pwm12;
		pwm13 = &pwm13;
		pwm14 = &pwm14;
		pwm15 = &pwm15;
		ac200 = &ac200;
		boot_disp = &boot_disp;
	};

	chosen {
		bootargs = "earlyprintk=sunxi-uart,0x05000000 loglevel=8 initcall_debug=0 console=ttyS0 init=/init";
		linux,initrd-start = <0x0 0x0>;
		linux,initrd-end = <0x0 0x0>;
	};

	firmware {
		android {
			compatible = "android,firmware";
			name = "android";
			boot_devices = "soc/sdc0,soc/sdc2,soc";
			vbmeta {
				compatible = "android,vbmeta";
				parts = "vbmeta,vbmeta_system,vbmeta_vendor,boot,super,recovery";
			};
		};
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "psci";
			clocks = <&clk_pll_cpu>;
			clock-latency = <2000000>;
			clock-frequency = <1320000000>;
			dynamic-power-coefficient = <190>;
			operating-points-v2 = <&cpu_opp_l_table>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			#cooling-cells = <2>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x1>;
			enable-method = "psci";
			clocks = <&clk_pll_cpu>;
			clock-frequency = <1320000000>;
			operating-points-v2 = <&cpu_opp_l_table>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			#cooling-cells = <2>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x2>;
			enable-method = "psci";
			clocks = <&clk_pll_cpu>;
			clock-frequency = <1320000000>;
			operating-points-v2 = <&cpu_opp_l_table>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			#cooling-cells = <2>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x3>;
			enable-method = "psci";
			clocks = <&clk_pll_cpu>;
			clock-frequency = <1320000000>;
			operating-points-v2 = <&cpu_opp_l_table>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			#cooling-cells = <2>;
		};

		idle-states {
			entry-method = "arm,psci";

			CPU_SLEEP_0: cpu-sleep-0 {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010000>;
				entry-latency-us = <46>;
				exit-latency-us = <59>;
				min-residency-us = <3570>;
				local-timer-stop;
			};

			CLUSTER_SLEEP_0: cluster-sleep-0 {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x1010000>;
				entry-latency-us = <47>;
				exit-latency-us = <74>;
				min-residency-us = <5000>;
				local-timer-stop;
			};
		};
	};

	cpu_opp_l_table: opp_l_table {
		compatible = "allwinner,sun50i-operating-points";
		nvmem-cells = <&speedbin_efuse>, <&cpubin_efuse>;
		nvmem-cell-names = "speed", "bin";
		opp-shared;

		opp@408000000 {
			opp-hz = /bits/ 64 <408000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <900000>;
			opp-microvolt-a1 = <900000>;
			opp-microvolt-a2 = <900000>;
			opp-microvolt-a3 = <937500 937500 940000>;
			opp-microvolt-a4 = <937500 937500 940000>;
			opp-microvolt-a5 = <920000 920000 925000>;
			opp-microvolt-a6 = <920000 920000 925000>;
			opp-microvolt-b0 = <900000>;
			opp-microvolt-b1 = <900000>;
			opp-microvolt-b2 = <937500 937500 940000>;
			opp-microvolt-b3 = <920000 920000 925000>;
			opp-microvolt-c0 = <900000>;
		};

		opp@600000000 {
			opp-hz = /bits/ 64 <600000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <900000>;
			opp-microvolt-a1 = <900000>;
			opp-microvolt-a2 = <900000>;
			opp-microvolt-a3 = <937500 937500 940000>;
			opp-microvolt-a4 = <937500 937500 940000>;
			opp-microvolt-a5 = <920000 920000 925000>;
			opp-microvolt-a6 = <920000 920000 925000>;
			opp-microvolt-b0 = <900000>;
			opp-microvolt-b1 = <900000>;
			opp-microvolt-b2 = <937500 937500 940000>;
			opp-microvolt-b3 = <920000 920000 925000>;
			opp-microvolt-c0 = <900000>;
		};

		opp@816000000 {
			opp-hz = /bits/ 64 <816000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <937500 937500 940000>;
			opp-microvolt-a1 = <900000>;
			opp-microvolt-a2 = <900000>;
			opp-microvolt-a3 = <937500 937500 940000>;
			opp-microvolt-a4 = <937500 937500 940000>;
			opp-microvolt-a5 = <920000 920000 925000>;
			opp-microvolt-a6 = <920000 920000 925000>;
			opp-microvolt-b0 = <900000>;
			opp-microvolt-b1 = <900000>;
			opp-microvolt-b2 = <937500 937500 940000>;
			opp-microvolt-b3 = <920000 920000 925000>;
			opp-microvolt-c0 = <900000>;
		};

		opp@1008000000 {
			opp-hz = /bits/ 64 <1008000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <1020000 1020000 1025000>;
			opp-microvolt-a1 = <975000 975000 980000>;
			opp-microvolt-a2 = <950000>;
			opp-microvolt-a3 = <1020000 1020000 1025000>;
			opp-microvolt-a4 = <960000 960000 962500>;
			opp-microvolt-a5 = <937500 937500 940000>;
			opp-microvolt-a6 = <937500 937500 940000>;
			opp-microvolt-b0 = <975000 975000 980000>;
			opp-microvolt-b1 = <950000>;
			opp-microvolt-b2 = <960000 960000 962500>;
			opp-microvolt-b3 = <937500 937500 940000>;
			opp-microvolt-c0 = <900000>;
		};

		opp@1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <1100000>;
			opp-microvolt-a1 = <1020000 1020000 1025000>;
			opp-microvolt-a2 = <1000000>;
			opp-microvolt-a3 = <1100000>;
			opp-microvolt-a4 = <975000 975000 980000>;
			opp-microvolt-a5 = <960000 960000 962500>;
			opp-microvolt-a6 = <960000 960000 962500>;
			opp-microvolt-b0 = <1020000 1020000 1025000>;
			opp-microvolt-b1 = <1000000>;
			opp-microvolt-b2 = <975000 975000 980000>;
			opp-microvolt-b3 = <960000 960000 962500>;
			opp-microvolt-c0 = <937500 937500 940000>;
		};

		opp@1320000000 {
			opp-hz = /bits/ 64 <1320000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <1160000 1160000 1162500>;
			opp-microvolt-a1 = <1060000 1060000 1062500>;
			opp-microvolt-a2 = <1025000 1025000 1030000>;
			opp-microvolt-a3 = <1160000 1160000 1162500>;
			opp-microvolt-a4 = <1020000 1020000 1025000>;
			opp-microvolt-a5 = <1000000>;
			opp-microvolt-a6 = <1000000>;
			opp-microvolt-b0 = <1060000 1060000 1062500>;
			opp-microvolt-b1 = <1025000 1025000 1030000>;
			opp-microvolt-b2 = <1020000 1020000 1025000>;
			opp-microvolt-b3 = <1000000>;
		};

		opp@1416000000 {
			opp-hz = /bits/ 64 <1416000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-b0 = <1100000>;
			opp-microvolt-b1 = <1070000 1070000 1075000>;
			opp-microvolt-b2 = <1060000 1060000 1062500>;
			opp-microvolt-b3 = <1037500 1037500 1040000>;
			opp-microvolt-c0 = <1020000 1020000 1025000>;
		};

		opp@1464000000 {
			opp-hz = /bits/ 64 <1464000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-a0 = <1180000 1180000 1187500>;
			opp-microvolt-a1 = <1180000 1180000 1187500>;
			opp-microvolt-a2 = <1125000 1125000 1130000>;
			opp-microvolt-a3 = <1180000 1180000 1187500>;
			opp-microvolt-a4 = <1100000>;
			opp-microvolt-a5 = <1075000 1075000 1080000>;
			opp-microvolt-a6 = <1075000 1075000 1080000>;
		};

		opp@1512000000 {
			opp-hz = /bits/ 64 <1512000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-b0 = <1180000 1180000 1187500>;
			opp-microvolt-b1 = <1130000 1130000 1140000>;
			opp-microvolt-b2 = <1100000>;
			opp-microvolt-b3 = <1075000 1075000 1080000>;
		};

		opp@1608000000 {
			opp-hz = /bits/ 64 <1608000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-c0 = <1100000>;
		};

		opp@1800000000 {
			opp-hz = /bits/ 64 <1800000000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
			opp-microvolt-c0 = <1180000 1180000 1187500>;
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	n_brom {
		compatible = "allwinner,n-brom";
		reg = <0x0 0x0 0x0 0xa000>;
	};

	s_brom {
		compatible = "allwinner,s-brom";
		reg = <0x0 0x0 0x0 0x10000>;
	};

	sram_ctrl {
		device_type = "sram_ctrl";
		compatible = "allwinner,sram_ctrl";
		reg = <0x0 0x03000000 0x0 0x100>;
	};

	sram_a1 {
		compatible = "allwinner,sram_a1";
		reg = <0x0 0x00020000 0x0 0x8000>;
	};

	sram_a2 {
		compatible = "allwinner,sram_a2";
		reg = <0x0 0x00100000 0x0 0x14000>;
	};

	prcm {
		compatible = "allwinner,prcm";
		reg = <0x0 0x01f01400 0x0 0x400>;
	};

	s_cpuscfg {
		compatible = "allwinner,s_cpuscfg";
		reg = <0x0 0x01f01c00 0x0 0x400>;
	};

	ion {
		compatible = "allwinner,sunxi-ion";
		/*types is list here:
			ION_HEAP_TYPE_SYSTEM = 0,
			ION_HEAP_TYPE_SYSTEM_CONTIG = 1,
			ION_HEAP_TYPE_CARVEOUT = 2,
			ION_HEAP_TYPE_CHUNK = 3,
			ION_HEAP_TYPE_DMA = 4,
			ION_HEAP_TYPE_SECURE = 6,
		**/
		heap_sys_user@0{
			compatible = "allwinner,sys_user";
			heap-name  = "sys_user";
			heap-id    = <0x0>;
			heap-base  = <0x0>;
			heap-size  = <0x0>;
			heap-type  = "ion_system";
		};
		heap_cma@0{
			compatible = "allwinner,cma";
			heap-name  = "cma";
			heap-id    = <0x4>;
			heap-base  = <0x0>;
			heap-size  = <0x0>;
			heap-type  = "ion_cma";
		};
		heap_secure@0{
			compatible = "allwinner,secure";
			heap-name  = "secure";
			heap-id    = <0x6>;
			heap-base  = <0x0>;
			heap-size  = <0x0>;
			heap-type  = "ion_secure";
		};
	};

	dram: dram {
		compatible = "allwinner,dram";
		clocks = <&clk_pll_ddr>;
		clock-names = "pll_ddr";
		dram_clk        = <672>;
		dram_type       = <3>;
		dram_zq         = <0x003F3FDD>;
		dram_odt_en     = <1>;
		dram_para1      = <0x10f41000>;
		dram_para2      = <0x00001200>;
		dram_mr0        = <0x1A50>;
		dram_mr1        = <0x40>;
		dram_mr2        = <0x10>;
		dram_mr3        = <0>;
		dram_tpr0       = <0x04E214EA>;
		dram_tpr1       = <0x004214AD>;
		dram_tpr2       = <0x10A75030>;
		dram_tpr3       = <0>;
		dram_tpr4       = <0>;
		dram_tpr5       = <0>;
		dram_tpr6       = <0>;
		dram_tpr7       = <0>;
		dram_tpr8       = <0>;
		dram_tpr9       = <0>;
		dram_tpr10      = <0>;
		dram_tpr11      = <0>;
		dram_tpr12      = <168>;
		dram_tpr13      = <0x823>;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x00000000 0x40000000 0x00000000 0x20000000>;
	};

	gic: interrupt-controller@03020000 {
		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		device_type = "gic";
		interrupt-controller;
		reg = <0x0 0x03021000 0 0x1000>, /* GIC Dist */
		      <0x0 0x03022000 0 0x2000>, /* GIC CPU */
		      <0x0 0x03024000 0 0x2000>, /* GIC VCPU Control */
		      <0x0 0x03026000 0 0x2000>; /* GIC VCPU */
		interrupts = <GIC_PPI 9 0xf04>; /* GIC Maintenence IRQ */
		interrupt-parent = <&gic>;
	};

	wakeupgen: interrupt-controller@0 {
		compatible = "allwinner,sunxi-wakeupgen";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
	};

	nmi_intc: intc-nmi@07010320 {
		compatible = "allwinner,sun8i-nmi";
		interrupt-parent = <&gic>;
		#interrupt-cells = <2>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0x0 0x07010320 0 0xc>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	};

	sid: sunxi-sid@03006000 {
		compatible = "allwinner,sunxi-sid";
		device_type = "sid";
		reg = <0x0 0x03006000 0 0x1000>;
	};

	sunxi-sid-ng@03006000 {
		compatible = "allwinner,sun50iw10p1-sid";
		reg = <0x0 0x03006000 0 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		speedbin_efuse: speed@00 {
			reg = <0x0 2>;
		};

		ths_calib: calib@14 {
			reg = <0x14 8>;
		};

		cpubin_efuse: calib@1c {
			reg = <0x1c 2>;
		};
	};

	chipid: sunxi-chipid@03006200 {
		compatible = "allwinner,sunxi-chipid";
		device_type = "chipid";
		reg = <0x0 0x03006200 0 0x0200>;
	};

	timer_arch {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			   <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			   <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			   <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <24000000>;
		interrupt-parent = <&gic>;
		arm,no-tick-in-suspend;
	};

	pd_gpu: gpu-power-domain@07001000 {
		   compatible = "allwinner,gpu-pd", "syscon";
		   reg = <0x0 0x07001000 0x0 0x40>;
		   interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
		   interrupt-names = "ppu-irq";
		   clocks = <&clk_ppu>;
		   clock-names = "ppu";
		   #power-domain-cells = <0>;
	};

	pd_gpu: gpu-power-domain@07001000 {
		   compatible = "allwinner,gpu-pd", "syscon";
		   reg = <0x0 0x07001000 0x0 0x40>;
		   interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
		   interrupt-names = "ppu-irq";
		   clocks = <&clk_ppu>;
		   clock-names = "ppu";
		   #power-domain-cells = <0>;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
	};

	dramfreq {
		compatible = "allwinner,sunxi-dramfreq";
		reg = <0x0 0x04002000 0x0 0x1000>,
		      <0x0 0x04003000 0x0 0x3000>,
		      <0x0 0x03001000 0x0 0x1000>;
		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk_pll_ddr>;
		status = "okay";
	};

	uboot: uboot {
	};

	mmu_aw: iommu@030f0000 {
		compatible = "allwinner,sunxi-iommu";
		reg = <0x0 0x030f0000 0x0 0x1000>;
		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "iommu-irq";
		clocks = <&clk_iommu>;
		clock-names = "iommu";
		/* clock-frequency = <24000000>; */
		#iommu-cells = <2>;
		status = "okay";
	};

	soc: soc@03000000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		device_type = "soc";

		auto_print {
			device_type = "auto_print";
			status = "okay";
		};

		dma0:dma-controller@03002000 {
			compatible = "allwinner,sun50i-dma";
			reg = <0x0 0x03002000 0x0 0x1000>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_dma>;
			#dma-cells = <1>;
		};

		nsi0:nsi-controller@03100000 {
			compatible = "allwinner,sun50i-nsi";
			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x0 0x03100000 0x0 0x10000>;
			clocks = <&clk_pll_ddr>, <&clk_mbus>;
			clock-frequency = <448000000>;
			#nsi-cells = <1>;
			status = "okay";
			cpu{
				mode = <0>; /*dont't set cpu mode*/
				pri = <0>;
				select = <0>;
			};
			gpu{
				mode = <0>;
				pri = <3>;
				select = <1>;
			};
			sd1{
				mode = <1>;
				pri = <2>;
				select = <0>;
			};
			mstg{
				mode = <0>;
				pri = <1>;
				select = <0>;
			};
			ce{
				mode = <1>;
				pri = <0>;
				select = <1>;
			};
		};

		mbus0:mbus-controller@047fa000 {
			compatible = "allwinner,sun50i-mbus";
			reg = <0x0 0x047fa000 0x0 0x1000>;
			#mbus-cells = <1>;
		};

		arisc {
			compatible = "allwinner,sunxi-arisc";
			#address-cells = <2>;
			#size-cells = <2>;
			clocks = <&clk_losc>, <&clk_iosc>, <&clk_hosc>, <&clk_pll_periph0>;
			clock-names = "losc", "iosc", "hosc", "pll_periph0";
			powchk_used = <0x0>;
			power_reg = <0x02309621>;
			system_power = <50>;
		};

		arisc_space {
			compatible = "allwinner,arisc_space";
			/* num    dst        offset     size                              */
			space1 = <0x48040000 0x00000000 0x00014000>; /* srama2 code space */
			space2 = <0x48100000 0x00018000 0x00004000>; /* dram code space   */
			space3 = <0x48104000 0x00000000 0x00001000>; /* para space        */
			space4 = <0x48105000 0x00000000 0x00001000>; /* msgpool space     */
		};

		standby_space {
			compatible = "allwinner,sun50iw10-usbstandby";
			/* num    dst        offset     size						*/
			space1 = <0x40020000 0x00000000 0x00000800>; /* super standby para space        */
		};

		msgbox: msgbox@03003000 {
			compatible = "allwinner,msgbox";
			clocks = <&clk_msgbox>;
			clock-names = "clk_msgbox";
			reg = <0x0 0x03003000 0x0 0x1000>;
			interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
			status = "okay";
		};

		s_cir0: s_cir@07040000 {
			compatible = "allwinner,s_cir";
			reg = <0x0 0x07040000 0x0 0x400>;
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&s_cir0_pins_a>;
			clocks = <&clk_hosc>,<&clk_cpurcir>;
			status = "okay";
		};

		ir1: ir@0x05071000 {
			compatible = "allwinner,ir_tx";
			reg = <0x0 0x05071000 0x0 0x400>;
			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&ir0_pins_a>,<&ir0_pins_b>;
			clocks = <&clk_hosc>,<&clk_irtx>;
			status = "okay";
		};

		soc_timer0: timer@03009000 {
			compatible = "allwinner,sun4i-a10-timer";
			device_type = "soc_timer";
			reg = <0x0 0x03009000 0x0 0x400>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_hosc>;
		};

		rtc: rtc@07000000 {
			compatible = "allwinner,sunxi-rtc";
			device_type = "rtc";
			wakeup-source;
			auto_switch;
			reg = <0x0 0x07000000 0x0 0x200>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			gpr_offset = <0x100>;
			gpr_len	   = <8>;
			gpr_cur_pos = <6>;
		};

		wdt: watchdog@030090a0 {
			compatible = "allwinner,sun50i-wdt";
			reg = <0x0 0x030090a0 0x0 0x20>;
			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
		};

		ve: ve@01c0e000 {
			compatible = "allwinner,sunxi-cedar-ve";
			reg = <0x0 0x01c0e000 0x0 0x1000>,
			      <0x0 0x03000000 0x0 0x10>,
			      <0x0 0x03001000 0x0 0x1000>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_pll_ve>,	<&clk_ve>;
			iommus = <&mmu_aw 2 1>;
		};

		vp9: vp9@01c00000 {
			compatible = "allwinner,sunxi-google-vp9";
			reg = <0x0 0x01c00000 0x0 0x1000>,
			      <0x0 0x03000000 0x0 0x10>,
			      <0x0 0x03001000 0x0 0x1000>;
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_pll_ve>;
			#clocks = <&clk_pll_periph0x2>;
		};

		uart0: uart@05000000 {
			compatible = "allwinner,sun50i-uart";
			device_type = "uart0";
			reg = <0x0 0x05000000 0x0 0x400>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart0>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart0_pins_a>;
			pinctrl-1 = <&uart0_pins_b>;
			uart0_port = <0>;
			uart0_type = <2>;
			status = "okay";
		};

		uart1: uart@05000400 {
			compatible = "allwinner,sun50i-uart";
			device_type = "uart1";
			reg = <0x0 0x05000400 0x0 0x400>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart1>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart1_pins_a>;
			pinctrl-1 = <&uart1_pins_b>;
			uart1_port = <1>;
			uart1_type = <4>;
			status = "disabled";
		};

		uart2: uart@05000800 {
			compatible = "allwinner,sun50i-uart";
			device_type = "uart2";
			reg = <0x0 0x05000800 0x0 0x400>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart2>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart2_pins_a>;
			pinctrl-1 = <&uart2_pins_b>;
			uart2_port = <2>;
			uart2_type = <4>;
			status = "disabled";
		};

		uart3: uart@05000c00 {
			compatible = "allwinner,sun50i-uart";
			device_type = "uart3";
			reg = <0x0 0x05000c00 0x0 0x400>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart3>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart3_pins_a>;
			pinctrl-1 = <&uart3_pins_b>;
			uart3_port = <3>;
			uart3_type = <4>;
			status = "disabled";
		};

		uart4: uart@05001000 {
			compatible = "allwinner,sun50i-uart";
			device_type = "uart4";
			reg = <0x0 0x05001000 0x0 0x400>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart4>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart4_pins_a>;
			pinctrl-1 = <&uart4_pins_b>;
			uart4_port = <4>;
			uart4_type = <4>;
			status = "disabled";
		};

		uart5: uart@05001400 {
			compatible = "allwinner,sun50i-uart";
			device_type = "uart5";
			reg = <0x0 0x05001400 0x0 0x400>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart5>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart5_pins_a>;
			pinctrl-1 = <&uart5_pins_b>;
			uart5_port = <5>;
			uart5_type = <4>;
			status = "disabled";
		};

		uart6: uart@05001800 {
			compatible = "allwinner,sun50i-uart";
			device_type = "uart6";
			reg = <0x0 0x05001800 0x0 0x400>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart6>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&uart6_pins_a>;
			pinctrl-1 = <&uart6_pins_b>;
			uart6_port = <6>;
			uart6_type = <4>;
			status = "disabled";
		};

		uart7: uart@07080000 {
			compatible = "allwinner,sun50i-uart";
			device_type = "uart7";
			reg = <0x0 0x07080000 0x0 0x400>;
			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_suart>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&s_uart0_pins_a>;
			pinctrl-1 = <&s_uart0_pins_b>;
			uart7_port = <7>;
			uart7_type = <2>;
			status = "disabled";
		};

		ir0: ir@0x05071000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,ir_tx";
			device_type = "ir0";
			reg = <0x0 0x05071000 0x0 0x400>;
			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_hosc>, <&clk_irtx>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&ir0_pins_a>;
			pinctrl-1 = <&ir0_pins_b>;
			status = "okay";
		};

		twi6: s_twi@0x07081400 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun50i-twi";
			reg = <0x0 0x07081400 0x0 0x200>;
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_stwi0>;
			clock-frequency = <200000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&s_twi0_pins_a>;
			pinctrl-1 = <&s_twi0_pins_b>;
			status = "disabled";
		};

		twi0: twi@0x05002000{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun50i-twi";
			device_type = "twi0";
			reg = <0x0 0x05002000 0x0 0x400>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_twi0>;
			clock-frequency = <400000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&twi0_pins_a>;
			pinctrl-1 = <&twi0_pins_b>;
			status = "disabled";
		};

		twi1: twi@0x05002400{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun50i-twi";
			device_type = "twi1";
			reg = <0x0 0x05002400 0x0 0x400>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_twi1>;
			clock-frequency = <200000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&twi1_pins_a>;
			pinctrl-1 = <&twi1_pins_b>;
			status = "disabled";
		};

		twi2: twi@0x05002800{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun50i-twi";
			device_type = "twi2";
			reg = <0x0 0x05002800 0x0 0x400>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_twi2>;
			clock-frequency = <100000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&twi2_pins_a>;
			pinctrl-1 = <&twi2_pins_b>;
			status = "disabled";
		};

		twi3: twi@0x05002c00{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun50i-twi";
			device_type = "twi3";
			reg = <0x0 0x05002c00 0x0 0x400>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_twi3>;
			clock-frequency = <100000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&twi3_pins_a>;
			pinctrl-1 = <&twi3_pins_b>;
			status = "disabled";
		};

		twi4: twi@0x05003000{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun50i-twi";
			device_type = "twi4";
			reg = <0x0 0x05003000 0x0 0x400>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_twi4>;
			clock-frequency = <100000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&twi4_pins_a>;
			pinctrl-1 = <&twi4_pins_b>;
			status = "disabled";
		};

		twi5: twi@0x05003400{
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun50i-twi";
			device_type = "twi5";
			reg = <0x0 0x05003400 0x0 0x400>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_twi5>;
			clock-frequency = <100000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&twi5_pins_a>;
			pinctrl-1 = <&twi5_pins_b>;
			status = "disabled";
		};

		twi7: s_twi@0x07081800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun50i-twi";
			reg = <0x0 0x07081800 0x0 0x200>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_stwi1>;
			clock-frequency = <200000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&s_twi1_pins_a>;
			pinctrl-1 = <&s_twi1_pins_b>;
			status = "disabled";
		};

		usbc0:usbc0@0 {
			device_type = "usbc0";
			compatible = "allwinner,sunxi-otg-manager";
			usb_port_type = <2>;
			usb_detect_type = <1>;
			usb_id_gpio;
			usb_det_vbus_gpio;
			usb_regulator_io = "nocare";
			usb_wakeup_suspend = <0>;
			usb_luns = <3>;
			usb_serial_unique = <0>;
			usb_serial_number = "20080411";
			rndis_wceis = <1>;
			status = "okay";
		};

		udc:udc-controller@0x05100000 {
			compatible = "allwinner,sunxi-udc";
			reg = <0x0 0x05100000 0x0 0x1000>, /*udc base*/
			      <0x0 0x00000000 0x0 0x100>, /*sram base*/
			      <0x0 0x05200000 0x0 0x1000>; /*usb1 base, for common circuit*/
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_usbphy0>, <&clk_usbotg>, <&clk_usbehci1>, <&clk_usbphy1>;
			status = "okay";
		};

		ehci0:ehci0-controller@0x05101000 {
			compatible = "allwinner,sunxi-ehci0";
			reg = <0x0 0x05101000 0x0 0xFFF>, /*hci0 base*/
			      <0x0 0x00000000 0x0 0x100>, /*sram base*/
			      <0x0 0x05100000 0x0 0x1000>, /*otg base*/
			      <0x0 0x07010250 0x0 0x10>,   /*prcm base, for usb standby*/
			      <0x0 0x05200000 0x0 0x1000>; /*usb1 base, for common circuit*/
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_usbphy0>, <&clk_usbehci0>, <&clk_usbehci1>, <&clk_usbphy1>;
			hci_ctrl_no = <0>;
			status = "okay";
		};

		ohci0:ohci0-controller@0x05101400 {
			compatible = "allwinner,sunxi-ohci0";
			reg = <0x0 0x05101000 0x0 0xFFF>, /*hci0 base*/
			      <0x0 0x00000000 0x0 0x100>, /*sram base*/
			      <0x0 0x05100000 0x0 0x1000>, /*otg base*/
			      <0x0 0x07010250 0x0 0x10>,   /*prcm base, for usb standby*/
			      <0x0 0x05200000 0x0 0x1000>; /*usb1 base, for common circuit*/
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_usbphy0>, <&clk_usbohci0>, <&clk_usbohci1>, <&clk_usbphy1>;
			hci_ctrl_no = <0>;
			status = "okay";
		};

		usbc1:usbc1@0 {
			device_type = "usbc1";
			usb_regulator_io = "nocare";
			usb_wakeup_suspend = <0>;
			status = "okay";
		};

		ehci1:ehci1-controller@0x05200000 {
			compatible = "allwinner,sunxi-ehci1";
			reg = <0x0 0x05200000 0x0 0xFFF>, /*hci0 base*/
			      <0x0 0x00000000 0x0 0x100>, /*sram base*/
			      <0x0 0x05100000 0x0 0x1000>, /*otg base*/
			      <0x0 0x07010250 0x0 0x10>;   /*prcm base, for usb standby*/
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_usbphy1>, <&clk_usbehci1>;
			hci_ctrl_no = <1>;
			status = "okay";
		};

		ohci1:ohci1-controller@0x05200400 {
			compatible = "allwinner,sunxi-ohci1";
			reg = <0x0 0x05200000 0x0 0xFFF>, /*hci0 base*/
			      <0x0 0x00000000 0x0 0x100>, /*sram base*/
			      <0x0 0x05100000 0x0 0x1000>, /*otg base*/
			      <0x0 0x07010250 0x0 0x10>;   /*prcm base, for usb standby*/
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_usbphy1>, <&clk_usbohci1>, <&clk_usbohci1_12m>, <&clk_osc48md4>, <&clk_hosc>, <&clk_losc>;
			hci_ctrl_no = <1>;
			status = "okay";
		};

		codec:codec@0x05096000 {
			compatible = "allwinner,sunxi-internal-codec";
			reg = <0x0 0x05096000 0x0 0x32c>;
			clocks = <&clk_pll_audiox4>,<&clk_codec_dac_1x>,<&clk_codec_adc_1x>,<&clk_pll_com>,<&clk_pll_comdiv5>;
			device_type = "codec";
			status = "disabled";
		};

		cpudai:cpudai-controller@0x050906000 {
			compatible = "allwinner,sunxi-internal-cpudai";
			reg = <0x0 0x05096000 0x0 0x32c>;
			status = "disabled";
		};

		sndcodec:sound@0 {
			compatible = "allwinner,sunxi-codec-machine";
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
			sunxi,cpudai-controller = <&cpudai>;
			sunxi,audio-codec = <&codec>;
			hp_detect_case = <0x00>;
			device_type = "sndcodec";
			status = "disabled";
		};

		spdif:spdif-controller@0x05094000{
			compatible = "allwinner,sunxi-spdif";
			reg = <0x0 0x05094000 0x0 0x40>;
			clocks = <&clk_pll_audio>,<&clk_pll_audiox4>,<&clk_spdif>;
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&spdif_pins_a>;
			pinctrl-1 = <&spdif_pins_b>;
			device_type = "spdif";
			status = "disabled";
		};

		sndspdif:sound@1{
			compatible = "allwinner,sunxi-spdif-machine";
			sunxi,spdif-controller = <&spdif>;
			device_type = "sndspdif";
			status = "disabled";
		};

		dmic:dmic-controller@0x05095000{
			compatible = "allwinner,sunxi-dmic";
			reg = <0x0 0x05095000 0x0 0x50>;
			clocks = <&clk_pll_audio>,<&clk_pll_audiox4>,<&clk_dmic>;
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&dmic_pins_a>;
			pinctrl-1 = <&dmic_pins_b>;
			device_type = "dmic";
			status = "disabled";
		};

		snddmic:sound@2{
			compatible = "allwinner,sunxi-dmic-machine";
			sunxi,dmic-controller = <&dmic>;
			device_type = "snddmic";
			status = "disabled";
		};


		daudio0:daudio@0x05090000 {
			compatible = "allwinner,sunxi-daudio";
			reg = <0x0 0x05090000 0x0 0x7c>;
			clocks = <&clk_pll_audio>,<&clk_pll_audiox4>,<&clk_i2s0>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&daudio0_pins_a>;
			pinctrl-1 = <&daudio0_pins_b>;
			device_type = "daudio0";
			tdm_num = <0x00>;
			status = "disabled";
		};

		snddaudio0:sound@3{
			compatible = "allwinner,sunxi-daudio0-machine";
			sunxi,daudio-controller = <&daudio0>;
			device_type = "snddaudio0";
			status = "disabled";
		};

		daudio1:daudio@0x05091000 {
			compatible = "allwinner,sunxi-daudio";
			reg = <0x0 0x05091000 0x0 0x7c>;
			clocks = <&clk_pll_audio>,<&clk_pll_audiox4>,<&clk_i2s1>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&daudio1_pins_a>;
			pinctrl-1 = <&daudio1_pins_b>;
			device_type = "daudio1";
			tdm_num = <0x01>;
			status = "disabled";
		};

		snddaudio1:sound@4{
			compatible = "allwinner,sunxi-daudio1-machine";
			sunxi,daudio-controller = <&daudio1>;
			device_type = "snddaudio1";
			status = "disabled";
		};

		daudio2:daudio@0x05092000 {
			compatible = "allwinner,sunxi-daudio";
			reg = <0x0 0x05092000 0x0 0x7c>;
			clocks = <&clk_pll_audio>,<&clk_pll_audiox4>,<&clk_i2s2>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&daudio2_pins_a>;
			pinctrl-1 = <&daudio2_pins_b>;
			device_type = "daudio2";
			tdm_num = <0x02>;
			status = "disabled";
		};

		snddaudio2:sound@5{
			compatible = "allwinner,sunxi-daudio2-machine";
			sunxi,daudio-controller = <&daudio2>;
			device_type = "snddaudio2";
			status = "disabled";
		};

		daudio3:daudio@0x05093000 {
			compatible = "allwinner,sunxi-daudio";
			reg = <0x0 0x05093000 0x0 0x7c>;
			clocks = <&clk_pll_audio>,<&clk_pll_audiox4>,<&clk_i2s3>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&daudio3_pins_a>;
			pinctrl-1 = <&daudio3_pins_b>;
			device_type = "daudio3";
			tdm_num = <0x03>;
			status = "disabled";
		};

		snddaudio3:sound@6{
			compatible = "allwinner,sunxi-daudio3-machine";
			sunxi,daudio-controller = <&daudio3>;
			device_type = "snddaudio3";
			status = "disabled";
		};

		spi0: spi@05010000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun50i-spi";
			device_type = "spi0";
			reg = <0x0 0x05010000 0x0 0x1000>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_pll_periph0>, <&clk_spi0>;
			clock-frequency = <100000000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi0_pins_a &spi0_pins_b>;
			pinctrl-1 = <&spi0_pins_c>;
			spi0_cs_number = <1>;
			spi0_cs_bitmap = <1>;
			status = "disabled";
			spi-nand {
				compatible="spi-nand";
				spi-max-frequency = <100000000>;
				reg=<0>;
				spi-rx-bus-width = <0x01>;
				spi-tx-bus-width = <0x01>;
				status = "disabled";
			};
		};

		spi1: spi@05011000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun50i-spi";
			device_type = "spi1";
			reg = <0x0 0x05011000 0x0 0x1000>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_pll_periph0>, <&clk_spi1>;
			clock-frequency = <100000000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi1_pins_a &spi1_pins_b>;
			pinctrl-1 = <&spi1_pins_c>;
			spi1_cs_number = <1>;
			spi1_cs_bitmap = <1>;
			status = "disabled";
		};

		spi2: spi@05012000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sun50i-spi";
			device_type = "spi2";
			reg = <0x0 0x05012000 0x0 0x1000>;
			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_pll_periph0>, <&clk_spi2>;
			clock-frequency = <100000000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi2_pins_a &spi2_pins_b>;
			pinctrl-1 = <&spi2_pins_c>;
			spi2_cs_number = <1>;
			spi2_cs_bitmap = <1>;
			status = "disabled";
		};

		ledc: ledc@0x05018000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "allwinner,sunxi-leds";
			reg = <0x0 0x05018000 0x0 0x100>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "ledcirq";
			clocks = <&clk_ledc>, <&clk_cpuapb>;
			clock-names = "clk_ledc", "clk_cpuapb";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&ledc_pins_a>;
			pinctrl-1 = <&ledc_pins_b>;
			led_count         = <34>;
			output_mode       = "GRB";
			reset_ns          = <84>;
			t1h_ns            = <800>;
			t1l_ns            = <450>;
			t0h_ns            = <400>;
			t0l_ns            = <850>;
			wait_time0_ns     = <84>;
			wait_time1_ns     = <84>;
			wait_data_time_ns = <600000>;
			status		  = "disabled";
		};

		pcie: pcie@0x05400000 {
			#address-cells = <3>;
			#size-cells = <2>;
			compatible = "allwinner,sun50i-pcie";
			reg = <0 0x05400000 0 0x2000>,
			      <0 0x05410000 0 0x10000>;
			reg-names = "dbi", "config";
			device_type = "pci";
			ranges = <0x00000800 0 0x05410000 0 0x05410000 0 0x00010000 /* configuration space */
				  0x81000000 0 0          0 0x05e00000 0 0x00010000 /* downstream I/O */
				  0x82000000 0 0x05500000 0 0x05500000 0 0x00800000>; /* non-prefetchable memory */
			num-lanes = <1>;
			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			/*clocks = <&clk_pcieref>,
				<&clk_pciemaxi>,
				<&clk_pcieaux>,
				<&clk_pcie_bus>,
				<&clk_pcie_power>,
				<&clk_pcie_rst>;*/
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
			status = "okay";
		};

		sdc2: sdmmc@04022000 {
			compatible = "allwinner,sunxi-mmc-v4p6x";
			device_type = "sdc2";
			reg = <0x0 0x04022000 0x0 0x1000>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_hosc>,
				 <&clk_pll_periph1x2>,
				 <&clk_sdmmc2_mod>,
				 <&clk_sdmmc2_bus>,
				 <&clk_sdmmc2_rst>;
			clock-names = "osc24m","pll_periph","mmc","ahb","rst";
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&sdc2_pins_a &sdc2_pins_c>;
			pinctrl-1 = <&sdc2_pins_b>;
			bus-width = <8>;
			cap-mmc-highspeed;
			cap-cmd23;
			mmc-cache-ctrl;
			non-removable;
			/*max-frequency = <200000000>;*/
			max-frequency = <50000000>;
			cap-erase;
			mmc-high-capacity-erase-size;
			no-sdio;
			no-sd;
			/*-- speed mode --*/
			/*sm0: DS26_SDR12*/
			/*sm1: HSSDR52_SDR25*/
			/*sm2: HSDDR52_DDR50*/
			/*sm3: HS200_SDR104*/
			/*sm4: HS400*/
			/*-- frequency point --*/
			/*f0: CLK_400K*/
			/*f1: CLK_25M*/
			/*f2: CLK_50M*/
			/*f3: CLK_100M*/
			/*f4: CLK_150M*/
			/*f5: CLK_200M*/

			sdc_tm4_sm0_freq0 = <0>;
			sdc_tm4_sm0_freq1 = <0>;
			sdc_tm4_sm1_freq0 = <0x00000000>;
			sdc_tm4_sm1_freq1 = <0>;
			sdc_tm4_sm2_freq0 = <0x00000000>;
			sdc_tm4_sm2_freq1 = <0>;
			sdc_tm4_sm3_freq0 = <0x05000000>;
			sdc_tm4_sm3_freq1 = <0x00000005>;
			sdc_tm4_sm4_freq0 = <0x00050000>;
			sdc_tm4_sm4_freq1 = <0x00000004>;

			/*vmmc-supply = <&reg_3p3v>;*/
			/*vqmc-supply = <&reg_3p3v>;*/
			/*vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
			/*sunxi-power-save-mode;*/
			status = "okay";
		};

		sdc0: sdmmc@04020000 {
			compatible = "allwinner,sunxi-mmc-v5p3x";
			device_type = "sdc0";
			reg = <0x0 0x04020000 0x0 0x1000>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_hosc>,
				 <&clk_pll_periph1x2>,
				 <&clk_sdmmc0_mod>,
				 <&clk_sdmmc0_bus>,
				 <&clk_sdmmc0_rst>;
			clock-names = "osc24m","pll_periph","mmc","ahb","rst";
			pinctrl-names = "default","sleep","uart_jtag";
			pinctrl-0 = <&sdc0_pins_a>;
			pinctrl-1 = <&sdc0_pins_b>;
			pinctrl-2 = <&sdc0_pins_c>;
			max-frequency = <50000000>;
			bus-width = <4>;
			/*non-removable;*/
			/*broken-cd;*/
			/*cd-inverted*/
			/*cd-gpios = <&pio PF 6 0 1 2 0>;*/
			/* vmmc-supply = <&reg_3p3v>;*/
			/* vqmc-supply = <&reg_3p3v>;*/
			/* vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
			cap-sd-highspeed;
			cap-wait-while-busy;
			no-sdio;
			no-mmc;
			/*sd-uhs-sdr50;*/
			/*sd-uhs-ddr50;*/
			/*cap-sdio-irq;*/
			/*keep-power-in-suspend;*/
			/*ignore-pm-notify;*/
			/*sunxi-power-save-mode;*/
			/*sunxi-dly-400k = <1 0 0 0>; */
			/*sunxi-dly-26M  = <1 0 0 0>;*/
			/*sunxi-dly-52M  = <1 0 0 0>;*/
			/*sunxi-dly-52M-ddr4  = <1 0 0 0>;*/
			/*sunxi-dly-52M-ddr8  = <1 0 0 0>;*/
			/*sunxi-dly-104M  = <1 0 0 0>;*/
			/*sunxi-dly-208M  = <1 0 0 0>;*/
			/*sunxi-dly-104M-ddr  = <1 0 0 0>;*/
			/*sunxi-dly-208M-ddr  = <1 0 0 0>;*/

			status = "okay";
		};

		sdc1: sdmmc@04021000 {
			compatible = "allwinner,sunxi-mmc-v5p3x";
			device_type = "sdc1";
			reg = <0x0 0x04021000 0x0 0x1000>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_hosc>,
				 <&clk_pll_periph1x2>,
				 <&clk_sdmmc1_mod>,
				 <&clk_sdmmc1_bus>,
				 <&clk_sdmmc1_rst>;
			clock-names = "osc24m","pll_periph","mmc","ahb","rst";
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&sdc1_pins_a>;
			pinctrl-1 = <&sdc1_pins_b>;
			max-frequency = <50000000>;
			bus-width = <4>;
			/*broken-cd;*/
			/*cd-inverted*/
			/*cd-gpios = <&pio PG 6 6 1 2 0>;*/
			/* vmmc-supply = <&reg_3p3v>;*/
			/* vqmc-supply = <&reg_3p3v>;*/
			/* vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
			cap-sd-highspeed;
			no-mmc;
			/*sd-uhs-sdr50;*/
			/*sd-uhs-ddr50;*/
			/*sd-uhs-sdr104;*/
			/*cap-sdio-irq;*/
			keep-power-in-suspend;
			/*ignore-pm-notify;*/
			/*sunxi-power-save-mode;*/
			/*sunxi-dly-400k = <1 0 0 0 0>; */
			/*sunxi-dly-26M  = <1 0 0 0 0>;*/
			/*sunxi-dly-52M  = <1 0 0 0 0>;*/
			sunxi-dly-52M-ddr4  = <1 0 0 0 2>;
			/*sunxi-dly-52M-ddr8  = <1 0 0 0 0>;*/
			sunxi-dly-104M  = <1 0 0 0 1>;
			/*sunxi-dly-208M  = <1 1 0 0 0>;*/
			sunxi-dly-208M  = <1 0 0 0 1>;
			/*sunxi-dly-104M-ddr  = <1 0 0 0 0>;*/
			/*sunxi-dly-208M-ddr  = <1 0 0 0 0>;*/

			/*status = "okay";*/
			status = "disabled";
		};

		sdc3: sdmmc@04023000 {
			compatible = "allwinner,sunxi-mmc-v5p3x";
			device_type = "sdc3";
			reg = <0x0 0x04023000 0x0 0x1000>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			/*the system has not configured sdmmc3 clk*/
			/*clocks = <&clk_hosc>,*/
			/*	 <&clk_pll_periph1x2>,*/
			/*	 <&clk_sdmmc3_mod>,*/
			/*	 <&clk_sdmmc3_bus>,*/
			/*	 <&clk_sdmmc3_rst>;*/
			/*clock-names = "osc24m","pll_periph","mmc","ahb","rst";*/
			pinctrl-names = "default","sleep";
			pinctrl-0 = <&sdc3_pins_a>;
			pinctrl-1 = <&sdc3_pins_b>;
			max-frequency = <50000000>;
			bus-width = <4>;
			cap-sd-highspeed;
			no-sdio;
			no-mmc;
			/*broken-cd;*/
			/*cd-inverted*/
			/*cd-gpios = <&pio PG 6 6 1 2 0>;*/
			/* vmmc-supply = <&reg_3p3v>;*/
			/* vqmc-supply = <&reg_3p3v>;*/
			/* vdmc-supply = <&reg_3p3v>;*/
			/*vmmc = "vcc-card";*/
			/*vqmc = "";*/
			/*vdmc = "";*/
			/*sd-uhs-sdr50;*/
			/*sd-uhs-ddr50;*/
			/*sd-uhs-sdr104;*/
			/*cap-sdio-irq;*/
			/*keep-power-in-suspend;*/
			/*ignore-pm-notify;*/
			/*sunxi-power-save-mode;*/
			/*sunxi-dly-400k = <1 0 0 0 0>; */
			/*sunxi-dly-26M  = <1 0 0 0 0>;*/
			/*sunxi-dly-52M  = <1 0 0 0 0>;*/
			/*sunxi-dly-52M-ddr8  = <1 0 0 0 0>;*/
			/*sunxi-dly-208M  = <1 1 0 0 0>;*/
			/*sunxi-dly-104M-ddr  = <1 0 0 0 0>;*/
			/*sunxi-dly-208M-ddr  = <1 0 0 0 0>;*/

			status = "disabled";
			/*status = "okay";*/
		};

		disp1: disp1@1 {
			compatible = "allwinner,sunxi-disp";
			iommus = <&mmu_aw 1 1>;
		};

		disp: disp@06000000 {
			compatible = "allwinner,sunxi-disp";
			reg = <0x0 0x06000000 0x0 0x3fffff>,/*de0*/
			      <0x0 0x06800000 0x0 0x3fffff>,/*de1*/
			      <0x0 0x06510000 0x0 0xfff>,/*tcon-top0*/
			      <0x0 0x06d10000 0x0 0xfff>,/*tcon-top1*/
			      <0x0 0x06511000 0x0 0xfff>,/*tcon-lcd0*/
			      <0x0 0x06d11000 0x0 0xfff>,/*tcon-lcd1*/
			      <0x0 0x06504000 0x0 0x1fff>;/*dsi0*/
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_de0>,
				 <&clk_de1>,
				 <&clk_display_top>,
				 <&clk_dpss_top0>,
				 <&clk_dpss_top1>,
				 <&clk_tcon_lcd0>,
				 <&clk_tcon_lcd1>,
				 <&clk_lvds>,
				 <&clk_lvds1>,
				 <&clk_mipi_host>;
			boot_disp = <0>;
			boot_disp1 = <0>;
			boot_disp2 = <0>;
			fb_base = <0>;
			iommus = <&mmu_aw 0 0>;
			status = "okay";
		};

		eink: eink@06400000 {
			compatible = "allwinner,sunxi-eink";
			pinctrl-names = "active","sleep";
			reg = <0x0 0x06400000 0x0 0x01ffff>,/* eink */
			      <0x0 0x06000000 0x0 0x3fffff>;/* de */
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, /* eink */
				     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; /* de */
			clocks = <&clk_de0>,
				 <&clk_ee>,
				 <&clk_panel>;
			iommus = <&mmu_aw 6 1>;
			status = "okay";
		};

		tps65185: tps65185@68 {
			compatible = "allwinner, tps65185";
			pinctrl-names = "active","sleep";
			status = "okay";
		};

		tps65185_slave: tps65185_slave@68{
			compatible = "allwinner, tps65185_slave";
			pinctrl-names = "active","sleep";
			status = "okay";
		};

		lcd0: lcd0@01c0c000 {
			compatible = "allwinner,sunxi-lcd0";
			pinctrl-names = "active","sleep";

			status = "okay";
		};

		lcd1: lcd1@01c0c001 {
			compatible = "allwinner,sunxi-lcd1";
			pinctrl-names = "active","sleep";

			status = "okay";
		};

		g2d: g2d@06480000 {
			compatible = "allwinner,sunxi-g2d";
			reg = <0x0 0x06480000 0x0 0x3ffff>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_g2d>;
			iommus = <&mmu_aw 5 1>;
			status = "okay";
		};

		pwm: pwm@0300a000 {
			compatible = "allwinner,sunxi-pwm";
			reg = <0x0 0x0300a000 0x0 0x3ff>;
			clocks = <&clk_pwm>;
			pwm-number = <16>;
			pwm-base = <0x0>;
			pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>,
				<&pwm5>, <&pwm6>, <&pwm7>, <&pwm8>, <&pwm9>,
				<&pwm10>, <&pwm11>, <&pwm12>, <&pwm13>,
				<&pwm14>, <&pwm15>;
		};

		s_pwm: pwm@07020c00 {
			compatible = "allwinner,sunxi-pwm";
			reg = <0x0 0x07020c00 0x0 0x3ff>;
			clocks = <&clk_spwm>;
			pwm-number = <1>;
			pwm-base = <16>;
			pwms = <&s_pwm0>;
		};

		pwm0: pwm0@0300a000 {
			compatible = "allwinner,sunxi-pwm0";
			pinctrl-names = "active", "sleep";
			reg_base = <0x0300a000>;
		};

		pwm1: pwm1@0300a000 {
			compatible = "allwinner,sunxi-pwm1";
			pinctrl-names = "active", "sleep";
			reg_base = <0x0300a000>;
		};

		pwm2: pwm2@0300a000 {
			compatible = "allwinner,sunxi-pwm2";
			pinctrl-names = "active", "sleep";
			reg_base = <0x0300a000>;
		};

		pwm3: pwm3@0300a000 {
			compatible = "allwinner,sunxi-pwm3";
			pinctrl-names = "active", "sleep";
			reg_base = <0x0300a000>;
		};

		pwm4: pwm4@0300a000 {
			compatible = "allwinner,sunxi-pwm4";
			pinctrl-names = "active", "sleep";
			reg_base = <0x0300a000>;
		};

		pwm5: pwm5@0300a000 {
			compatible = "allwinner,sunxi-pwm5";
			pinctrl-names = "active", "sleep";
			reg_base = <0x0300a000>;
		};

		pwm6: pwm6@0300a000 {
			compatible = "allwinner,sunxi-pwm6";
			pinctrl-names = "active", "sleep";
			reg_base = <0x0300a000>;
		};

		pwm7: pwm7@0300a000 {
			compatible = "allwinner,sunxi-pwm7";
			pinctrl-names = "active", "sleep";
			reg_base = <0x0300a000>;
		};

		pwm8: pwm8@0300a000 {
			compatible = "allwinner,sunxi-pwm8";
			pinctrl-names = "active", "sleep";
			reg_base = <0x0300a000>;
		};

		pwm9: pwm9@0300a000 {
			compatible = "allwinner,sunxi-pwm9";
			pinctrl-names = "active", "sleep";
			reg_base = <0x0300a000>;
		};

		pwm10: pwm10@0300a000 {
			compatible = "allwinner,sunxi-pwm10";
			pinctrl-names = "active", "sleep";
			reg_base = <0x0300a000>;
		};

		pwm11: pwm11@0300a000 {
			compatible = "allwinner,sunxi-pwm11";
			pinctrl-names = "active", "sleep";
			reg_base = <0x0300a000>;
		};

		pwm12: pwm12@0300a000 {
			compatible = "allwinner,sunxi-pwm12";
			pinctrl-names = "active", "sleep";
			reg_base = <0x0300a000>;
		};

		pwm13: pwm13@0300a000 {
			compatible = "allwinner,sunxi-pwm13";
			pinctrl-names = "active", "sleep";
			reg_base = <0x0300a000>;
		};

		pwm14: pwm14@0300a000 {
			compatible = "allwinner,sunxi-pwm14";
			pinctrl-names = "active", "sleep";
			reg_base = <0x0300a000>;
		};

		pwm15: pwm15@0300a000 {
			compatible = "allwinner,sunxi-pwm15";
			pinctrl-names = "active", "sleep";
			reg_base = <0x0300a000>;
		};

		s_pwm0: s_pwm0@07020c00 {
			compatible = "allwinner,sunxi-pwm16";
			pinctrl-names = "active", "sleep";
			reg_base = <0x07020c00>;
		};

		boot_disp: boot_disp {
			compatible = "allwinner,boot_disp";
		};

		ac200: ac200 {
			compatible = "allwinner,sunxi-ac200";
			clocks = <&clk_tcon_lcd0>;
			pinctrl-names = "active","sleep", "ccir_clk_active",
			"ccir_clk_sleep";
			pinctrl-2 = <&ccir_clk_pin_a>;
			pinctrl-3 = <&ccir_clk_pin_b>;
			status = "okay";
		};

		vind0:vind@0 {
			compatible = "allwinner,sunxi-vin-media", "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			device_id = <0>;
			vind0_clk = <336000000>;
			vind0_isp = <327000000>;
			reg = <0x0 0x02000800 0x0 0x200>,
				<0x0 0x02000000 0x0 0x800>,
				<0x0 0x0200A000 0x0 0x100>;
			clocks = <&clk_csi_top>, <&clk_pll_video2x2>,
				 <&clk_csi_master0>, <&clk_hosc>, <&clk_pll_video2x2>,
				 <&clk_csi_master1>, <&clk_hosc>, <&clk_pll_video2x2>,
				 <&clk_csi_isp>, <&clk_pll_video3x2>;
			pinctrl-names = "mclk0-default","mclk0-sleep","mclk1-default","mclk1-sleep";
			pinctrl-0 = <&csi_mclk0_pins_a>;
			pinctrl-1 = <&csi_mclk0_pins_b>;
			pinctrl-2 = <&csi_mclk1_pins_a>;
			pinctrl-3 = <&csi_mclk1_pins_b>;
			status = "okay";

			csi0:csi@0 {
				device_type = "csi0";
				compatible = "allwinner,sunxi-csi";
				reg = <0x0 0x02001000 0x0 0x1000>;
				interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
				device_id = <0>;
				iommus = <&mmu_aw 3 1>;
				status = "okay";
			};
			csi1:csi@1 {
				device_type = "csi1";
				compatible = "allwinner,sunxi-csi";
				reg = <0x0 0x02002000 0x0 0x1000>;
				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
				device_id = <1>;
				iommus = <&mmu_aw 3 1>;
				status = "okay";
			};
			mipi0:mipi@0 {
				compatible = "allwinner,sunxi-mipi";
				reg = <0x0 0x0200A100 0x0 0x100>,
					<0x0 0x0200B000 0x0 0x400>;
				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
				device_id = <0>;
				status = "okay";
			};
			mipi1:mipi@1 {
				compatible = "allwinner,sunxi-mipi";
				reg = <0x0 0x0200A200 0x0 0x100>,
					<0x0 0x0200B400 0x0 0x400>;
				device_id = <1>;
				status = "okay";
			};
			tdm0:tdm@0 {
				compatible = "allwinner,sunxi-tdm";
				reg = <0x0 0x02108000 0x0 0x180>;
				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
				device_id = <0>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			isp0:isp@0 {
				compatible = "allwinner,sunxi-isp";
				reg = <0x0 0x02100000 0x0 0x2000>;
				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
				device_id = <0>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			isp1:isp@1 {
				compatible = "allwinner,sunxi-isp";
				reg = <0x0 0x02102000 0x0 0x2000>;
				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
				device_id = <1>;
				iommus = <&mmu_aw 4 1>;
				status = "okay";
			};
			scaler0:scaler@0 {
				compatible = "allwinner,sunxi-scaler";
				reg = <0x0 0x02110000 0x0 0x400>;
				device_id = <0>;
				iommus = <&mmu_aw 3 1>;
				status = "okay";
			};
			scaler1:scaler@1 {
				compatible = "allwinner,sunxi-scaler";
				reg = <0x0 0x02110400 0x0 0x400>;
				device_id = <1>;
				iommus = <&mmu_aw 3 1>;
				status = "okay";
			};
			scaler2:scaler@2 {
				compatible = "allwinner,sunxi-scaler";
				reg = <0x0 0x02110800 0x0 0x400>;
				device_id = <2>;
				iommus = <&mmu_aw 3 1>;
				status = "okay";
			};
			scaler3:scaler@3 {
				compatible = "allwinner,sunxi-scaler";
				reg = <0x0 0x02110C00 0x0 0x400>;
				device_id = <3>;
				iommus = <&mmu_aw 3 1>;
				status = "okay";
			};
			actuator0:actuator@0 {
				device_type = "actuator0";
				compatible = "allwinner,sunxi-actuator";
				actuator0_name = "ad5820_act";
				actuator0_slave = <0x18>;
				actuator0_af_pwdn = <>;
				actuator0_afvdd = "afvcc-csi";
				actuator0_afvdd_vol = <2800000>;
				status = "disabled";
			};
			flash0:flash@0 {
				device_type = "flash0";
				compatible = "allwinner,sunxi-flash";
				flash0_type = <2>;
				flash0_en = <>;
				flash0_mode = <>;
				flash0_flvdd = "";
				flash0_flvdd_vol = <>;
				device_id = <0>;
				status = "disabled";
			};
			sensor0:sensor@0 {
				device_type = "sensor0";
				compatible = "allwinner,sunxi-sensor";
				sensor0_mname = "ov5640";
				sensor0_twi_cci_id = <2>;
				sensor0_twi_addr = <0x78>;
				sensor0_mclk_id = <0>;
				sensor0_pos = "rear";
				sensor0_isp_used = <0>;
				sensor0_fmt = <0>;
				sensor0_stby_mode = <0>;
				sensor0_vflip = <0>;
				sensor0_hflip = <0>;
				sensor0_iovdd-supply = <>;
				sensor0_iovdd_vol = <2800000>;
				sensor0_avdd-supply = <>;
				sensor0_avdd_vol = <2800000>;
				sensor0_dvdd-supply = <>;
				sensor0_dvdd_vol = <1500000>;
				sensor0_power_en = <>;
				sensor0_reset = <&pio PE 14 1 0 1 0>;
				sensor0_pwdn = <&pio PE 16 1 0 1 0>;
				sensor0_sm_vs = <>;
				flash_handle = <&flash0>;
				act_handle = <&actuator0>;
				device_id = <0>;
				status	= "okay";
			};
			sensor1:sensor@1 {
				device_type = "sensor1";
				compatible = "allwinner,sunxi-sensor";
				sensor1_mname = "ov5647";
				sensor1_twi_cci_id = <3>;
				sensor1_twi_addr = <0x6c>;
				sensor1_mclk_id = <1>;
				sensor1_pos = "front";
				sensor1_isp_used = <0>;
				sensor1_fmt = <0>;
				sensor1_stby_mode = <0>;
				sensor1_vflip = <0>;
				sensor1_hflip = <0>;
				sensor1_iovdd-supply = <>;
				sensor1_iovdd_vol = <2800000>;
				sensor1_avdd-supply = <>;
				sensor1_avdd_vol = <2800000>;
				sensor1_dvdd-supply = <>;
				sensor1_dvdd_vol = <1500000>;
				sensor1_power_en = <>;
				sensor1_reset = <&pio PE 14 1 0 1 0>;
				sensor1_pwdn = <&pio PE 15 1 0 1 0>;
				sensor1_sm_vs = <>;
				flash_handle = <>;
				act_handle = <>;
				device_id = <1>;
				status	= "okay";
			};
			vinc0:vinc@0 {
				device_type = "vinc0";
				compatible = "allwinner,sunxi-vin-core";
				reg = <0x0 0x02009000 0x0 0x200>;
				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
				vinc0_csi_sel = <1>;
				vinc0_mipi_sel = <0xff>;
				vinc0_isp_sel = <1>;
				vinc0_tdm_rx_sel = <0xff>;
				vinc0_rear_sensor_sel = <0>;
				vinc0_front_sensor_sel = <0>;
				vinc0_sensor_list = <0>;
				device_id = <0>;
				iommus = <&mmu_aw 3 1>;
				status = "okay";
			};
			vinc1:vinc@1 {
				device_type = "vinc1";
				compatible = "allwinner,sunxi-vin-core";
				reg = <0x0 0x02009200 0x0 0x200>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
				vinc1_csi_sel = <1>;
				vinc1_mipi_sel = <0xff>;
				vinc1_isp_sel = <1>;
				vinc1_tdm_rx_sel = <0xff>;
				vinc1_rear_sensor_sel = <0>;
				vinc1_front_sensor_sel = <0>;
				vinc1_sensor_list = <0>;
				device_id = <1>;
				iommus = <&mmu_aw 3 1>;
				status = "okay";
			};
			vinc2:vinc@2 {
				device_type = "vinc2";
				compatible = "allwinner,sunxi-vin-core";
				reg = <0x0 0x02009400 0x0 0x200>;
				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
				vinc2_csi_sel = <3>;
				vinc2_mipi_sel = <0xff>;
				vinc2_isp_sel = <1>;
				vinc2_tdm_rx_sel = <0xff>;
				vinc2_rear_sensor_sel = <0>;
				vinc2_front_sensor_sel = <1>;
				vinc2_sensor_list = <0>;
				device_id = <2>;
				iommus = <&mmu_aw 3 1>;
				status = "disabled";
			};
			vinc3:vinc@3 {
				device_type = "vinc3";
				compatible = "allwinner,sunxi-vin-core";
				reg = <0x0 0x02009600 0x0 0x200>;
				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
				vinc3_csi_sel = <3>;
				vinc3_mipi_sel = <0xff>;
				vinc3_isp_sel = <1>;
				vinc3_tdm_rx_sel = <0xff>;
				vinc3_rear_sensor_sel = <0>;
				vinc3_front_sensor_sel = <1>;
				vinc3_sensor_list = <0>;
				device_id = <3>;
				iommus = <&mmu_aw 3 1>;
				status = "disabled";
			};
		};

		Vdevice: vdevice@0 {
			compatible = "allwinner,sun50i-vdevice";
			device_type = "Vdevice";
			pinctrl-names = "default";
			interrupt-parent = <&pio>;
			interrupts = < PB 0 IRQ_TYPE_LEVEL_HIGH>;       /* bank offset type */
			pinctrl-0 = <&vdevice_pins_a>;
			test-gpios = <&pio PB 0 1 2 2 1>;  /* PA 0 0=in/1=out drive pull level */
			suspend-gpios = <&r_pio PL 4 1 2 2 1>;  /* PA 0 0=in/1=out drive pull level */
			wakeup-source;
			status = "okay";
		};

		emce: emce@01905000 {
			compatible = "allwinner,sunxi-emce";
			device_name = "emce";
			reg = <0x0 0x01905000 0 0x100>;
			clock-frequency = <300000000>; /*300MHZ*/
			/*clocks = <&clk_emce>, <&clk_pll_periph0x2>;*/
		};

		cryptoengine: ce@1904000 {
			compatible = "allwinner,sunxi-ce";
			device_name = "ce";
			reg = <0x0 0x01904000 0x0 0xa0>, /* non-secure space */
			      <0x0 0x01904800 0x0 0xa0>; /* secure space */
			interrupts = <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>, /* non-secure space */
				   <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; /* secure space */
			clock-frequency = <400000000>; /* 400MHz */
			clocks = <&clk_ce>, <&clk_pll_periph0x2>;
		};

		nand0:nand0@04011000 {
			compatible = "allwinner,sun50iw10-nand";
			device_type = "nand0";
			reg = <0x0 0x04011000 0x0 0x1000>;/* nand0 */
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_pll_periph0x2>,<&clk_nand0>,<&clk_nand1>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&nand0_pins_a &nand0_pins_b>;
			pinctrl-1 = <&nand0_pins_c>;
			nand0_regulator1 = "vcc-nand";
			nand0_regulator2 = "none";
			nand0_cache_level = <0x55aaaa55>;
			nand0_flush_cache_num = <0x55aaaa55>;
			nand0_capacity_level = <0x55aaaa55>;
			nand0_id_number_ctl = <0x55aaaa55>;
			nand0_print_level = <0x55aaaa55>;
			nand0_p0 = <0x55aaaa55>;
			nand0_p1 = <0x55aaaa55>;
			nand0_p2 = <0x55aaaa55>;
			nand0_p3 = <0x55aaaa55>;
			chip_code = "sun50iw10";
			status = "okay";
		};

		ths: thermal_sensor{
			compatible = "allwinner,sun50iw10p1-ths";
			reg = <0x0 0x05070400 0x0 0x400>;
			clocks = <&clk_ths>;
			clock-names = "bus";
			nvmem-cells = <&ths_calib>;
			nvmem-cell-names = "calibration";
			#thermal-sensor-cells = <1>;
		};

		thermal-zones {
			cpu_thermal_zone {
				polling-delay-passive = <500>;
				polling-delay = <1000>;
				thermal-sensors = <&ths 0>;
				sustainable-power = <800>;
				k_po = <24>;
				k_pu = <48>;
				k_i = <0>;

				cpu_trips: trips {
					cpu_threshold: trip-point@0 {
						temperature = <70000>;
						type = "passive";
						hysteresis = <0>;
					};
					cpu_target: trip-point@1 {
						temperature = <80000>;
						type = "passive";
						hysteresis = <0>;
					};
					cpu_crit: cpu_crit@0 {
						temperature = <110000>;
						type = "critical";
						hysteresis = <0>;
					};
				};

				cooling-maps {
					map0 {
						trip = <&cpu_target>;
						cooling-device = <&cpu0
						THERMAL_NO_LIMIT
						THERMAL_NO_LIMIT>;
						contribution = <1024>;
					};
				/*	map1{
						trip = <&cpu_target>;
						cooling-device = <&gpu
						THERMAL_NO_LIMIT
						THERMAL_NO_LIMIT>;
						contribution = <1024>;
					};	*/
				};
			};
			gpu_thermal_zone{
				polling-delay-passive = <500>;
				polling-delay = <1000>;
				thermal-sensors = <&ths 1>;
				sustainable-power = <1100>;
			};
			ddr_thermal_zone{
				polling-delay-passive = <0>;
				polling-delay = <0>;
				thermal-sensors = <&ths 2>;
			};
		};

		gpadc:gpadc{
			compatible = "allwinner,sunxi-gpadc";
			reg = <0x0 0x05070000 0x0 0x400>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_NONE>;
			clocks = <&clk_gpadc>;
			status = "disabled";
		};

		keyboard0:keyboard{
			compatible = "allwinner,keyboard_1350mv";
			reg = <0x0 0x05070800 0x0 0x400>;
			interrupts = <GIC_SPI 22 IRQ_TYPE_NONE>;
			clocks = <&clk_lradc>;
			status = "okay";
			key_cnt = <5>;
			key0 = <210 115>;
			key1 = <410 114>;
			key2 = <590 139>;
			key3 = <750 28>;
			key4 = <880 102>;
		};

		gmac0: eth@05020000 {
			compatible = "allwinner,sunxi-gmac";
			reg = <0x0 0x05020000 0x0 0x10000>,
			      <0x0 0x03000030 0x0 0x4>;
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gmacirq";
			clocks = <&clk_gmac0>, <&clk_gmac0_25m>;
			clock-names = "gmac", "ephy";
			device_type = "gmac0";
			pinctrl-0 = <&gmac_pins_a>;
			pinctrl-1 = <&gmac_pins_b>;
			pinctrl-names = "default", "sleep";
			phy-mode;
			tx-delay = <7>;
			rx-delay = <31>;
			phy-rst;
			gmac-power0;
			gmac-power1;
			gmac-power2;
			status = "disable";
		};

		gmac1: eth@05030000 {
			compatible = "allwinner,sunxi-gmac";
			reg = <0x0 0x05030000 0x0 0x10000>,
			      <0x0 0x03000034 0x0 0x4>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gmacirq";
			clocks = <&clk_gmac1>, <&clk_gmac1_25m>;
			clock-names = "gmac", "ephy";
			device_type = "gmac1";
			pinctrl-0 = <&gmac1_pins_a>;
			pinctrl-1 = <&gmac1_pins_b>;
			pinctrl-names = "default", "sleep";
			phy-mode;
			tx-delay = <7>;
			rx-delay = <31>;
			phy-rst;
			gmac-power0;
			gmac-power1;
			gmac-power2;
			status = "disable";
		};
	};

	gpu: gpu@0x01800000 {
		device_type = "gpu";
		compatible = "img,gpu";
		reg = <0x0 0x01800000 0x0 0x80000>;
		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "IRQGPU";
		clocks = <&clk_pll_gpu>, <&clk_gpu>;
		clock-names = "clk_parent", "clk_mali";
		power-domains = <&pd_gpu>;
	};
};