/*
 * (C) Copyright 2018
 * wangwei <wangwei@allwinnertech.com>
 */

#include <common.h>
#include <private_boot0.h>
#include <private_uboot.h>
#include <private_toc.h>
#include <private_tee.h>
#include <arch/clock.h>
#include <arch/uart.h>
#include <arch/dram.h>
#include <arch/rtc.h>
#include <arch/gpio.h>
#ifdef CFG_SET_BACKLIGHT
#include <arch/gpio_new.h>
#endif
#include <board_helper.h>
#include <config.h>
#include <boot_param.h>

__u8 uboot_backup;

static void update_uboot_info(phys_addr_t uboot_base, phys_addr_t optee_base,
		phys_addr_t monitor_base, phys_addr_t rtos_base, u32 dram_size,
		u16 pmu_type, u16 uart_input, u16 key_input);
static int boot0_clear_env(void);
__maybe_unused int load_kernel_from_spinor(u32 *);
__maybe_unused void startup_kernel(u32, u32);

static void print_commit_log(void)
{
	printf("HELLO! BOOT0 is starting!\n");
	printf("BOOT0 commit : %s\n", BT0_head.hash);
	sunxi_set_printf_debug_mode(BT0_head.prvt_head.debug_mode, 0);
}

void main(void)
{
	int dram_size;
	int status;
	phys_addr_t  uboot_base = 0, optee_base = 0, monitor_base = 0, \
				rtos_base = 0, opensbi_base = 0, cpus_rtos_base = 0;
	u16 pmu_type = 0, key_input = 0; /* TODO: set real value */

#ifdef CFG_SET_BACKLIGHT
	normal_gpio_set_t gpio_bl;
#endif
#ifdef CFG_GET_WKSRC
	normal_gpio_cfg M0_uart_gpio[2];
	/* has_get_wksrc[10] = 0; 默认唤醒源是0 */
	u8 has_get_wksrc[11] = {0xaa, 0x55, 0xaa, 0x55, 0x0e, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00}; // has get wake up source, len is 11
#ifdef CFG_WKSRC_ADDR
	u8 *buff;
#endif
#endif
	sunxi_board_init_early();
	sunxi_serial_init(BT0_head.prvt_head.uart_port, (void *)BT0_head.prvt_head.uart_ctrl, 2);
	print_commit_log();

	status = sunxi_board_init();
	if (status)
		goto _BOOT_ERROR;

	if (rtc_probe_fel_flag()) {
		rtc_clear_fel_flag();
		goto _BOOT_ERROR;
#ifdef CFG_SUNXI_PHY_KEY
#ifdef CFG_LRADC_KEY
	} else if (check_update_key(&key_input)) {
		goto _BOOT_ERROR;
#endif
#endif
	}

#ifdef CFG_SET_BACKLIGHT
	/* gpio back light */
	gpio_bl.port = SUNXI_GPIO_D; /*使用PD口*/
	gpio_bl.port_num = 20; /*端口为20口*/
	gpio_bl.mul_sel = SUNXI_GPIO_OUTPUT; /*配置为输出模式*/
	gpio_bl.pull = SUNXI_GPIO_PULL_DISABLE; /*不配置默认上下拉*/
	gpio_bl.drv_level  = SUNXI_GPIO_DRV_LEVEL1; /*输出等级为1级*/
	gpio_bl.data = 1; /*默认输出high电平*/
	// gpio_bl.data = 0; /*默认输出low电平*/

	if (boot_set_gpio_new(&gpio_bl, 1, 1) < 0)
	{
		pr_emerg("boot_set_gpio error\n");
	}
#endif
#ifdef CFG_GET_WKSRC
	/* init uart for M0 */
	M0_uart_gpio[0] = BT0_head.prvt_head.uart_ctrl[0];
	M0_uart_gpio[0].port = SUNXI_GPIO_D + 1; // ZZP:using API without _new needs to +1, please ref macro:PIO_REG_CFG
	M0_uart_gpio[0].port_num = 18;
	M0_uart_gpio[0].mul_sel = 7; // Multiplex funciton
	M0_uart_gpio[1] = BT0_head.prvt_head.uart_ctrl[1];
	M0_uart_gpio[1].port =  SUNXI_GPIO_D + 1;
	M0_uart_gpio[1].port_num = 19;
	M0_uart_gpio[1].mul_sel = 7;
	sunxi_serial_M0_init(2, (void *)M0_uart_gpio, 2); // UART2 
	if (has_sunxi_serial_M0_send(has_get_wksrc, sizeof(has_get_wksrc)) == sizeof(has_get_wksrc))
	{
		if (has_sunxi_serial_M0_get(has_get_wksrc, sizeof(has_get_wksrc)) != sizeof(has_get_wksrc))
		{
			has_get_wksrc[10] = 0; // 默认唤醒源是0
		}
	}
	// pr_emerg("wksrc:%d\n", has_get_wksrc[10]);
#else
	if (BT0_head.prvt_head.enable_jtag) {
		printf("enable_jtag\n");
		boot_set_gpio((normal_gpio_cfg *)BT0_head.prvt_head.jtag_gpio, 5, 1);
	}
#endif

	char uart_input_value = get_uart_input(); /* Prevent DRAM jamming */
	if (uart_input_value == '2') {
		printf("detected_f user input 2\n");
		goto _BOOT_ERROR;
	}
	sunxi_bootparam_load();
#ifdef FPGA_PLATFORM
	dram_size = sunxi_fpga_dram_init((void *)sunxi_bootparam_get_dram_buf());
#else
	dram_size = init_DRAM(0, (void *)sunxi_bootparam_get_dram_buf());
#endif
	if (!dram_size) {
		printf("init dram fail\n");
		goto _BOOT_ERROR;
	} else {
		if (BT0_head.dram_size > 0)
			dram_size = BT0_head.dram_size;
		printf("dram size =%d\n", dram_size);
	}
#ifdef CFG_SUNXI_STANDBY_WORKAROUND
	handler_super_standby();
#endif

#ifndef CFG_GET_WKSRC
	uart_input_value = get_uart_input();
	if (uart_input_value == '2') {
		sunxi_set_printf_debug_mode(3, 0);
		printf("detected_r user input 2\n");
		goto _BOOT_ERROR;
	} else if (uart_input_value == 'd') {
		sunxi_set_printf_debug_mode(8, 1);
		printf("detected user input d\n");
	} else if (uart_input_value == 'q') {
		printf("detected user input q\n");
		sunxi_set_printf_debug_mode(0, 1);
	}
#endif

	mmu_enable(dram_size);
	malloc_init(CONFIG_HEAP_BASE, CONFIG_HEAP_SIZE);
	status = sunxi_board_late_init();
	if (status)
		goto _BOOT_ERROR;

	status = load_package();
	if (status == 0)
		load_image(&uboot_base, &optee_base, &monitor_base, &rtos_base, &opensbi_base, &cpus_rtos_base);
	else
		goto _BOOT_ERROR;
#if defined(CFG_RISCV_E907) || defined(CFG_RISCV_E906) || defined(CFG_RISCV_C906)
#ifdef CFG_SUNXI_FDT
	extern void boot_riscv(phys_addr_t base, unsigned long fdt_addr);
	if (cpus_rtos_base != 0)
		boot_riscv(cpus_rtos_base, (unsigned long)working_fdt);
#endif
#endif

	update_uboot_info(uboot_base, optee_base, monitor_base, rtos_base, dram_size,
			pmu_type, uart_input_value, key_input);

#ifdef CFG_GET_WKSRC
#ifdef CFG_WKSRC_ADDR
	/* must operate after dram init */
	buff = (u8 *)CFG_WKSRC_ADDR;
	buff[0] = has_get_wksrc[10];
#endif
#endif

#if CFG_BOOT0_LOAD_KERNEL
	exist_uboot_jmp_cardproduct(uboot_base);
	void load_and_run_kernel(u32 optee_base, u32 opensbi_base, u32 monitor_base);
	load_and_run_kernel(optee_base, opensbi_base, monitor_base);
	//already jump to kernel, should never return, if so, go FEL
	goto _BOOT_ERROR;
#endif

	mmu_disable();
	printf("Jump to second Boot.\n");
	if (opensbi_base) {
			boot0_jmp_opensbi(opensbi_base, uboot_base);
	} else if (monitor_base) {
		struct spare_monitor_head *monitor_head =
			(struct spare_monitor_head *)((phys_addr_t)monitor_base);
		monitor_head->secureos_base = optee_base;
		monitor_head->nboot_base = uboot_base;
		boot0_jmp_monitor(monitor_base);
	} else if (optee_base)
		boot0_jmp_optee(optee_base, uboot_base);
	else if (rtos_base) {
		printf("jump to rtos\n");
		boot0_jmp(rtos_base);
	}
	else
		boot0_jmp(uboot_base);

	while(1);
_BOOT_ERROR:
	boot0_clear_env();
	boot0_jmp(FEL_BASE);

}

static void update_uboot_info(phys_addr_t uboot_base, phys_addr_t optee_base,
		phys_addr_t monitor_base, phys_addr_t rtos_base, u32 dram_size,
		u16 pmu_type, u16 uart_input, u16 key_input)
{
	if (rtos_base)
		return;

	uboot_head_t  *header = (uboot_head_t *) uboot_base;
	struct sbrom_toc1_head_info *toc1_head = (struct sbrom_toc1_head_info *)CONFIG_BOOTPKG_BASE;

	if (uboot_base) {

#ifdef CFG_SUNXI_BOOT_PARAM
		sunxi_bootparam_format_and_transfer(
			(void *)(uboot_base + SUNXI_BOOTPARAM_OFFSET));
#endif

		header->boot_data.boot_package_size = toc1_head->valid_len;
		header->boot_data.dram_scan_size = dram_size;
		memcpy((void *)header->boot_data.dram_para,
			(void *)sunxi_bootparam_get_dram_buf(), 32 * sizeof(int));

		if (monitor_base)
			header->boot_data.monitor_exist = 1;

		if (optee_base) {
			struct spare_optee_head *tee_head =
				(struct spare_optee_head *)optee_base;
			header->boot_data.secureos_exist = 1;
			tee_head->dram_size		 = dram_size;
			tee_head->drm_size = BT0_head.secure_dram_mbytes;
			tee_head->uart_port = BT0_head.prvt_head.uart_port;
		}

#ifndef CONFIG_RISCV
		header->boot_data.func_mask |= get_uboot_func_mask(UBOOT_FUNC_MASK_ALL);
#endif
		update_flash_para(uboot_base);

		header->boot_data.uart_port = BT0_head.prvt_head.uart_port;
		memcpy((void *)header->boot_data.uart_gpio, BT0_head.prvt_head.uart_ctrl, 2*sizeof(normal_gpio_cfg));
		header->boot_data.pmu_type = pmu_type;
		header->boot_data.uart_input = uart_input;
		header->boot_data.key_input = key_input;
		header->boot_data.debug_mode = sunxi_get_debug_mode_for_uboot();
		if (get_card_work_mode() != NOUSE_CARDMODE)
			header->boot_data.work_mode = get_card_work_mode();
		header->boot_data.uboot_backup = uboot_backup;
	}
}

static int boot0_clear_env(void)
{
	sunxi_board_exit();
	sunxi_board_clock_reset();
	mmu_disable();
	mdelay(10);

	return 0;
}