/* * Allwinner Technology CO., Ltd. sun8iw19p1 platform * * modify base on juno.dts */ /* kernel used */ /memreserve/ 0x41980000 0x00018000; /* optee:0x41980000~0x41998000,size=96k */ #include #include #include "sun8iw19p1-clk.dtsi" #include "sun8iw19p1-pinctrl.dtsi" #include / { model = "sun8iw19"; compatible = "allwinner,sun8iw19p1"; interrupt-parent = <&wakeupgen>; #address-cells = <2>; #size-cells = <2>; aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; serial3 = &uart3; twi0 = &twi0; twi1 = &twi1; twi2 = &twi2; twi3 = &twi3; twi4 = &twi4; spi0 = &spi0; spi1 = &spi1; spi2 = &spi2; gmac0 = &gmac0; global_timer0 = &soc_timer0; mmc0 = &sdc0; mmc2 = &sdc2; /*nand0 =&nand0;*/ disp = &disp; lcd0 = &lcd0; /*hdmi = &hdmi;*/ pwm = &pwm; pwm0 = &pwm0; pwm1 = &pwm1; pwm2 = &pwm2; pwm3 = &pwm3; pwm4 = &pwm4; pwm5 = &pwm5; pwm6 = &pwm6; pwm7 = &pwm7; pwm8 = &pwm8; pwm9 = &pwm9; /*tv0 = &tv0; vdpo0 = &vdpo0;*/ boot_disp = &boot_disp; }; chosen { bootargs = "earlyprintk=sunxi-uart,0x05000000 loglevel=8 initcall_debug=0 console=ttyS0 init=/init"; linux,initrd-start = <0x0 0x0>; linux,initrd-end = <0x0 0x0>; }; cpus { enable-method = "allwinner,sun8iw19p1"; #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x0>; enable-method = "psci"; clocks = <&clk_pll_cpu>; clock-frequency = <1008000000>; clock-latency = <2000000>; /* if divide bin <&cpu_opp_l_table0 &cpu_opp_l_table1> */ operating-points-v2 = <&cpu_opp_l_table0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>; cooling-min-level = <5>; cooling-max-level = <0>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <150>; }; idle-states { entry-method = "arm,psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x0010000>; entry-latency-us = <45>; exit-latency-us = <90>; min-residency-us = <3000>; local-timer-stop; }; CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x1010000>; entry-latency-us = <55>; exit-latency-us = <570>; min-residency-us = <17000>; local-timer-stop; }; SYS_SLEEP_0: sys-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x2010000>; entry-latency-us = <0xffffffff>; exit-latency-us = <0xffffffff>; min-residency-us = <0xffffffff>; local-timer-stop; }; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; n_brom { compatible = "allwinner,n-brom"; reg = <0x0 0x0 0x0 0xc000>; }; s_brom { compatible = "allwinner,s-brom"; reg = <0x0 0x0 0x0 0x10000>; }; sram_ctrl { device_type = "sram_ctrl"; compatible = "allwinner,sram_ctrl"; reg = <0x0 0x03000000 0x0 0x100>; }; sram_a1 { compatible = "allwinner,sram_a1"; reg = <0x0 0x00010000 0x0 0x10000>; }; sram_a2 { compatible = "allwinner,sram_a2"; reg = <0x0 0x00040000 0x0 0x14000>; }; prcm { compatible = "allwinner,prcm"; reg = <0x0 0x01f01400 0x0 0x400>; }; cpuscfg { compatible = "allwinner,cpuscfg"; reg = <0x0 0x01f01c00 0x0 0x400>; }; ion { compatible = "allwinner,sunxi-ion"; /* *types list here: ION_HEAP_TYPE_SYSTEM = 0, ION_HEAP_TYPE_SYSTEM_CONTIG = 1, ION_HEAP_TYPE_CARVEOUT = 2, ION_HEAP_TYPE_CHUNK = 3, ION_HEAP_TYPE_DMA = 4, ION_HEAP_TYPE_SECURE = 6, **/ heap_sys_user@0{ compatible = "allwinner,sys_user"; heap-name = "sys_user"; heap-id = <0x0>; heap-base = <0x0>; heap-size = <0x0>; heap-type = "ion_system"; }; heap_sys_contig@0{ compatible = "allwinner,sys_contig"; heap-name = "sys_contig"; heap-id = <0x1>; heap-base = <0x0>; heap-size = <0x0>; heap-type = "ion_contig"; }; /*heap_carveout@0{ compatible = "allwinner,carveout"; heap-name = "carveout"; heap-id = <0x2>; heap-base = <0x0>; heap-size = <0x0>; heap-type = "ion_carveout"; };*/ heap_cma@0{ compatible = "allwinner,cma"; heap-name = "cma"; heap-id = <0x4>; heap-base = <0x0>; heap-size = <0x0>; heap-type = "ion_cma"; }; }; dram: dram { compatible = "allwinner,dram"; device_type = "dram"; clocks = <&clk_pll_ddr0>; clock-names = "pll_ddr0"; }; memory@40000000 { device_type = "memory"; reg = <0x00000000 0x40000000 0x00000000 0x20000000>; }; gic: interrupt-controller@03020000 { compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <0>; device_type = "gic"; interrupt-controller; reg = <0x0 0x03021000 0 0x1000>, /* GIC Dist */ <0x0 0x03022000 0 0x2000>, /* GIC CPU */ <0x0 0x03024000 0 0x2000>, /* GIC VCPU Control */ <0x0 0x03026000 0 0x2000>; /* GIC VCPU */ interrupts = ; /* GIC Maintenence IRQ */ interrupt-parent = <&gic>; }; nmi_intc: intc-nmi@07010320 { compatible = "allwinner,sun8i-nmi"; interrupt-parent = <&gic>; #interrupt-cells = <2>; #address-cells = <0>; interrupt-controller; reg = <0x0 0x07010320 0 0xc>; pad-control-v1 = <0x07000208>; interrupts = ; }; wakeupgen: interrupt-controller@0 { compatible = "allwinner,sunxi-wakeupgen"; interrupt-controller; #interrupt-cells = <3>; interrupt-parent = <&gic>; }; sid: sunxi-sid@03006000 { compatible = "allwinner,sunxi-sid"; device_type = "sid"; reg = <0x0 0x03006000 0 0x200>; }; chipid: sunxi-chipid@03006200 { compatible = "allwinner,sunxi-chipid"; device_type = "chipid"; reg = <0x0 0x03006200 0 0xC0>; }; timer { compatible = "arm,armv7-timer"; interrupts = , /* Secure Phys IRQ */ , /* Non-secure Phys IRQ */ , /* Virt IRQ */ ; /* Hyp IRQ */ clock-frequency = <24000000>; arm,cpu-registers-not-fw-configured; interrupt-parent = <&gic>; }; pmu { compatible = "arm,cortex-a7-pmu"; interrupts = ; }; dramfreq { compatible = "allwinner,sunxi-dramfreq"; reg = <0x0 0x01c62000 0x0 0x1000>, <0x0 0x01c63000 0x0 0x1000>, <0x0 0x01c20000 0x0 0x800>; interrupts = ; /* clocks = <&clk_pll_ddr>, <&clk_pll_periph0>, <&clk_ahb1>; */ status = "okay"; }; uboot: uboot { }; mmu_aw: iommu@030f0000 { compatible = "allwinner,sunxi-iommu"; reg = <0x0 0x030f0000 0x0 0x1000>; interrupts = ; interrupt-names = "iommu-irq"; clocks = <&clk_iommu>; clock-names = "iommu"; /*clock-frequency = <24000000>; */ #iommu-cells = <2>; status = "okay"; }; mbus0:mbus-controller@047FA000 { compatible = "allwinner,sun8i-mbus"; reg = <0x0 0x04002000 0x0 0x1000>; #mbus-cells = <1>; }; ac200: ac200 { compatible = "allwinner,sunxi-ac200"; /* clocks = <&clk_tcon0>; */ pinctrl-names = "active","sleep"; status = "okay"; }; ramoops@0x48106000 { compatible = "ramoops"; reg = <0x0 0x48106000 0x0 0x60000>; record-size = <0x00020000>; console-size = <0x00020000>; pmsg-size = <0x00020000>; }; cpucfg@09010000 { compatible = "allwinner,sunxi-cpucfg"; reg = <0x0 0x09010000 0x0 0xc8>; }; soc: soc@03000000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; device_type = "soc"; dma0:dma-controller@03002000 { compatible = "allwinner,sun8i-dma"; reg = <0x0 0x03002000 0x0 0x1000>; interrupts = ; clocks = <&clk_dma>; #dma-cells = <1>; }; soc_timer0: timer@03009000 { compatible = "allwinner,sun4i-a10-timer"; device_type = "soc_timer"; reg = <0x0 0x03009000 0x0 0x90>; interrupts = ; /* On FPGA, timer can only use the losc. * On IC, timer should use the hosc. */ clocks = <&clk_hosc>, <&clk_losc>; }; rtc: rtc@07000000 { compatible = "allwinner,sun8i-rtc", "allwinner,sunxi-rtc"; device_type = "rtc"; reg = <0x0 0x07000000 0x0 0x400>; interrupts = ; auto_switch; wakeup-source; gpr_offset = <0x100>; gpr_len = <8>; }; wdt: watchdog@030090a0 { compatible = "allwinner,sun50i-wdt"; reg = <0x0 0x030090a0 0x0 0x20>; interrupts = ; }; ve@01c0e000 { compatible = "allwinner,sunxi-cedar-ve"; reg = <0x0 0x01c0e000 0x0 0x1000>, <0x0 0x03000000 0x0 0x10>, <0x0 0x03001000 0x0 0x800>, <0x0 0x07010000 0x0 0x300>; interrupts = ; clocks = <&clk_pll_uni>, <&clk_ve>; iommus = <&mmu_aw 3 1>; }; ise: ise@01c10000 { compatible = "allwinner,sunxi-ise"; reg = <0x0 0x01c10000 0x0 0x1000>, <0x0 0x03001000 0x0 0x800>; interrupts = ; /*clocks = <&clk_pll_ise>, <&clk_ise>;*/ }; eise: eise@0x02300000 { compatible = "allwinner,sunxi-eise"; reg = <0x0 0x02300000 0x0 0x1000>, <0x0 0x03001000 0x0 0x800>; interrupts = ; clocks = <&clk_pll_uni>, <&clk_eise>; iommus = <&mmu_aw 1 1>; }; uart0: uart@05000000 { compatible = "allwinner,sun8i-uart"; device_type = "uart0"; reg = <0x0 0x05000000 0x0 0x400>; interrupts = ; clocks = <&clk_uart0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart0_pins_a>; pinctrl-1 = <&uart0_pins_b>; uart0_port = <0>; uart0_type = <2>; status = "okay"; }; uart1: uart@05000400 { compatible = "allwinner,sun8i-uart"; device_type = "uart1"; reg = <0x0 0x05000400 0x0 0x400>; interrupts = ; clocks = <&clk_uart1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart1_pins_a>; pinctrl-1 = <&uart1_pins_b>; uart1_port = <1>; uart1_type = <4>; status = "disabled"; }; uart2: uart@05000800 { compatible = "allwinner,sun8i-uart"; device_type = "uart2"; reg = <0x0 0x05000800 0x0 0x400>; interrupts = ; clocks = <&clk_uart2>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart2_pins_a>; pinctrl-1 = <&uart2_pins_b>; uart2_port = <2>; uart2_type = <4>; status = "disabled"; }; uart3: uart@05000c00 { compatible = "allwinner,sun8i-uart"; device_type = "uart3"; reg = <0x0 0x05000c00 0x0 0x400>; interrupts = ; clocks = <&clk_uart3>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart3_pins_a>; pinctrl-1 = <&uart3_pins_b>; uart3_port = <3>; uart3_type = <4>; status = "disabled"; }; s_owc0: s_owc@07040400 { compatible = "allwinner,sunxi-owc"; device_type = "s_owc0"; reg = <0x0 0x07040400 0x0 0x30>; interrupts = ; clocks = <&clk_hosc>,<&clk_cpurowc>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&owc0_pins_a>; pinctrl-1 = <&owc0_pins_b>; status = "disabled"; }; twi0: twi@0x05002000{ #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun8i-twi"; device_type = "twi0"; reg = <0x0 0x05002000 0x0 0x400>; interrupts = ; clocks = <&clk_twi0>; clock-frequency = <400000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&twi0_pins_a>; pinctrl-1 = <&twi0_pins_b>; twi_drv_used = <1>; status = "disable"; }; twi1: twi@0x05002400{ #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun8i-twi"; device_type = "twi1"; reg = <0x0 0x05002400 0x0 0x400>; interrupts = ; clocks = <&clk_twi1>; clock-frequency = <200000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&twi1_pins_a>; pinctrl-1 = <&twi1_pins_b>; twi_drv_used = <1>; status = "disable"; }; twi2: twi@0x05002800{ #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun8i-twi"; device_type = "twi2"; reg = <0x0 0x05002800 0x0 0x400>; interrupts = ; clocks = <&clk_twi2>; clock-frequency = <200000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&twi2_pins_a>; pinctrl-1 = <&twi2_pins_b>; twi_drv_used = <1>; status = "disable"; }; twi3: twi@0x05002c00{ #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun8i-twi"; device_type = "twi3"; reg = <0x0 0x05002c00 0x0 0x400>; interrupts = ; clocks = <&clk_twi3>; clock-frequency = <200000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&twi3_pins_a>; pinctrl-1 = <&twi3_pins_b>; twi_drv_used = <1>; status = "disable"; }; twi4: twi@0x07081400{ #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun8i-twi"; device_type = "twi4"; reg = <0x0 0x07081400 0x0 0x400>; interrupts = ; clocks = <&clk_stwi>; clock-frequency = <200000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&s_twi0_pins_a>; pinctrl-1 = <&s_twi0_pins_b>; status = "disabled"; }; usbc0:usbc0@0 { device_type = "usbc0"; compatible = "allwinner,sunxi-otg-manager"; usb_port_type = <2>; usb_detect_type = <1>; usb_id_gpio; usb_det_vbus_gpio; usb_drv_vbus_gpio; usb_host_init_state = <0>; usb_regulator_io = "nocare"; usb_wakeup_suspend = <0>; usb_luns = <3>; usb_serial_unique = <0>; usb_serial_number = "20080411"; rndis_wceis = <1>; status = "okay"; }; udc:udc-controller@0x05100000 { compatible = "allwinner,sunxi-udc"; reg = <0x0 0x05100000 0x0 0x1000>, /*udc base*/ <0x0 0x00000000 0x0 0x100>; /*sram base*/ interrupts = ; clocks = <&clk_usbphy0>, <&clk_usbotg>; status = "okay"; }; ehci0:ehci0-controller@0x05101000 { compatible = "allwinner,sunxi-ehci0"; reg = <0x0 0x05101000 0x0 0xFFF>, /*hci0 base*/ <0x0 0x00000000 0x0 0x100>, /*sram base*/ <0x0 0x05100000 0x0 0x1000>; /*otg base*/ interrupts = ; clocks = <&clk_usbphy0>, <&clk_usbehci0>; hci_ctrl_no = <0>; status = "okay"; }; ohci0:ohci0-controller@0x05101400 { compatible = "allwinner,sunxi-ohci0"; reg = <0x0 0x05101000 0x0 0xFFF>, /*hci0 base*/ <0x0 0x00000000 0x0 0x100>, /*sram base*/ <0x0 0x05100000 0x0 0x1000>; /*otg base*/ interrupts = ; clocks = <&clk_usbphy0>, <&clk_usbohci0>, <&clk_usbohci0_12m>, <&clk_osc48md4>, <&clk_hosc>, <&clk_losc>; hci_ctrl_no = <0>; status = "okay"; }; daudio0:daudio@0x05090000 { compatible = "allwinner,sunxi-daudio"; reg = <0x0 0x05090000 0x0 0x7c>; clocks = <&clk_pll_audio>,<&clk_i2s0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&daudio0_pins_a>; pinctrl-1 = <&daudio0_pins_b>; device_type = "daudio0"; tdm_num = <0x00>; status = "disabled"; /* pcm platform runtime hwparams config */ rate_max = <0x2ee00>; /* max rate: 192000 */ channels_max = <0x08>; /* max chennels: 8 */ buffer_bytes_max = <0x20000>; /* max buffer size: 1024 * 128 */ period_bytes_max = <0x10000>; /* max period size: 1024 * 64 */ periods_max = <0x08>; /* max count of periods: 8 */ fifo_size = <0x80>; /* fifo size in bytes: 128 */ }; daudio1:daudio@0x05091000 { compatible = "allwinner,sunxi-daudio"; reg = <0x0 0x05091000 0x0 0x7c>; clocks = <&clk_pll_audio>,<&clk_i2s1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&daudio1_pins_a>; pinctrl-1 = <&daudio1_pins_b>; device_type = "daudio1"; tdm_num = <0x01>; status = "disabled"; /* pcm platform runtime hwparams config */ rate_max = <0x2ee00>; /* 192000 */ channels_max = <0x08>; /* 8 */ buffer_bytes_max = <0x20000>; /* 1024 * 128 */ period_bytes_max = <0x10000>; /* 1024 * 64 */ periods_max = <0x08>; /* 8 */ fifo_size = <0x80>; /* 128 */ }; codec:codec@0x05096000 { compatible = "allwinner,sunxi-internal-codec"; reg = <0x0 0x05096000 0x0 0x320>; clocks = <&clk_pll_audio>,<&clk_codec_1x>; device_type = "codec"; status = "disabled"; /* pcm platform runtime hwparams config */ rate_max = <0x2ee00>; /* 192000 */ channels_max = <0x08>; /* 8 */ buffer_bytes_max = <0x20000>; /* 1024 * 128 */ period_bytes_max = <0x10000>; /* 1024 * 64 */ periods_max = <0x08>; /* 8 */ fifo_size = <0x80>; /* 128 */ }; sndcodec:sound@0 { compatible = "allwinner,sunxi-codec-machine"; interrupts = ; sunxi,audio-codec = <&codec>; device_type = "sndcodec"; status = "disabled"; }; snddaudio0:sound@1{ compatible = "allwinner,sunxi-daudio0-machine"; sunxi,daudio-controller = <&daudio0>; device_type = "snddaudio0"; status = "disabled"; }; snddaudio1:sound@2{ compatible = "allwinner,sunxi-daudio1-machine"; sunxi,daudio-controller = <&daudio1>; device_type = "snddaudio1"; status = "disabled"; }; spi0: spi@05010000 { #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun8i-spi"; device_type = "spi0"; reg = <0x0 0x05010000 0x0 0x1000>; interrupts = ; clocks = <&clk_pll_periph0>, <&clk_spi0>; clock-frequency = <300000000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi0_pins_a &spi0_pins_b>; pinctrl-1 = <&spi0_pins_c>; spi0_cs_number = <2>; spi0_cs_bitmap = <3>; status = "disabled"; }; spi1: spi@05011000 { #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun8i-spi"; device_type = "spi1"; reg = <0x0 0x05011000 0x0 0x1000>; interrupts = ; clocks = <&clk_pll_periph0>, <&clk_spi1>; clock-frequency = <200000000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi1_pins_a &spi1_pins_b>; pinctrl-1 = <&spi1_pins_c>; spi1_cs_number = <2>; spi1_cs_bitmap = <3>; status = "disabled"; }; spi2: spi@05012000 { #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun8i-spi"; device_type = "spi2"; reg = <0x0 0x05012000 0x0 0x1000>; interrupts = ; clocks = <&clk_pll_periph0>, <&clk_spi2>; clock-frequency = <200000000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi2_pins_a &spi2_pins_b>; pinctrl-1 = <&spi2_pins_c>; spi2_cs_number = <1>; spi2_cs_bitmap = <1>; status = "disabled"; }; /* spi3: spi@05013000 { #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun50i-spi"; device_type = "spi3"; reg = <0x0 0x05013000 0x0 0x1000>; interrupts = ; clocks = <&clk_pll_periph0>, <&clk_spi3>; clock-frequency = <200000000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi3_pins_a &spi3_pins_b>; pinctrl-1 = <&spi3_pins_c>; spi3_cs_number = <1>; spi3_cs_bitmap = <1>; status = "disabled"; }; */ auto_print { device_type = "auto_print"; status = "okay"; }; sdc2: sdmmc@04022000 { compatible = "allwinner,sunxi-mmc-v4p5x"; device_type = "sdc2"; reg = <0x0 0x04022000 0x0 0x1000>; interrupts = ; clocks = <&clk_hosc>, <&clk_pll_unix2>, <&clk_sdmmc2_mod>, <&clk_sdmmc2_bus>, <&clk_sdmmc2_rst>; clock-names = "osc24m","pll_periph","mmc","ahb","rst"; pinctrl-names = "default","sleep"; pinctrl-0 = <&sdc2_pins_a&sdc2_pins_c>; pinctrl-1 = <&sdc2_pins_b>; bus-width = <8>; /*mmc-ddr-1_8v;*/ /*mmc-hs200-1_8v;*/ /*mmc-hs400-1_8v;*/ cap-sd-highspeed; cap-mmc-highspeed; cap-wait-while-busy; mmc-high-capacity-erase-size; cap-erase; /*non-removable;*/ /*max-frequency = <200000000>;*/ max-frequency = <50000000>; /*-- speed mode --*/ /*sm0: DS26_SDR12*/ /*sm1: HSSDR52_SDR25*/ /*sm2: HSDDR52_DDR50*/ /*sm3: HS200_SDR104*/ /*sm4: HS400*/ /*-- frequency point --*/ /*f0: CLK_400K*/ /*f1: CLK_25M*/ /*f2: CLK_50M*/ /*f3: CLK_100M*/ /*f4: CLK_150M*/ /*f5: CLK_200M*/ sdc_tm4_sm0_freq0 = <0>; sdc_tm4_sm0_freq1 = <0>; sdc_tm4_sm1_freq0 = <0x00000000>; sdc_tm4_sm1_freq1 = <0>; sdc_tm4_sm2_freq0 = <0x00000000>; sdc_tm4_sm2_freq1 = <0>; sdc_tm4_sm3_freq0 = <0x05000000>; sdc_tm4_sm3_freq1 = <0x00000005>; sdc_tm4_sm4_freq0 = <0x00050000>; sdc_tm4_sm4_freq1 = <0x00000004>; /*vmmc-supply = <®_3p3v>;*/ /*vqmc-supply = <®_3p3v>;*/ /*vdmc-supply = <®_3p3v>;*/ /*vmmc = "vcc-card";*/ /*vqmc = "";*/ /*vdmc = "";*/ /*sunxi-power-save-mode;*/ /*status = "disabled";*/ status = "disable"; }; sdc0: sdmmc@04020000 { compatible = "allwinner,sunxi-mmc-v4p1x"; device_type = "sdc0"; reg = <0x0 0x04020000 0x0 0x1000>; interrupts = ; clocks = <&clk_hosc>, <&clk_pll_unix2>, <&clk_sdmmc0_mod>, <&clk_sdmmc0_bus>, <&clk_sdmmc0_rst>; clock-names = "osc24m","pll_periph","mmc","ahb","rst"; pinctrl-names = "default","sleep", "uart_jtag"; pinctrl-0 = <&sdc0_pins_a>; pinctrl-1 = <&sdc0_pins_b>; pinctrl-2 = <&sdc0_pins_c>; max-frequency = <50000000>; bus-width = <4>; /*non-removable;*/ /*broken-cd;*/ /*cd-inverted*/ /*cd-gpios = <&pio PF 6 0 1 2 0>;*/ /* vmmc-supply = <®_3p3v>;*/ /* vqmc-supply = <®_3p3v>;*/ /* vdmc-supply = <®_3p3v>;*/ /*vmmc = "vcc-card";*/ /*vqmc = "";*/ /*vdmc = "";*/ /*sd-uhs-sdr50;*/ /*sd-uhs-ddr50;*/ cap-sd-highspeed; cap-mmc-highspeed; cap-wait-while-busy; /*cap-sdio-irq;*/ /*keep-power-in-suspend;*/ /*ignore-pm-notify;*/ /*sunxi-power-save-mode;*/ /*sunxi-dly-400k = <1 0 0 0>; */ /*sunxi-dly-26M = <1 0 0 0>;*/ /*sunxi-dly-52M = <1 0 0 0>;*/ /*sunxi-dly-52M-ddr4 = <1 0 0 0>;*/ /*sunxi-dly-52M-ddr8 = <1 0 0 0>;*/ /*sunxi-dly-104M = <1 0 0 0>;*/ /*sunxi-dly-208M = <1 0 0 0>;*/ /*sunxi-dly-104M-ddr = <1 0 0 0>;*/ /*sunxi-dly-208M-ddr = <1 0 0 0>;*/ status = "okay"; }; sdc1: sdmmc@04021000 { compatible = "allwinner,sunxi-mmc-v4p1x"; device_type = "sdc1"; reg = <0x0 0x04021000 0x0 0x1000>; interrupts = ; clocks = <&clk_hosc>, <&clk_pll_unix2>, <&clk_sdmmc1_mod>, <&clk_sdmmc1_bus>, <&clk_sdmmc1_rst>; clock-names = "osc24m","pll_periph","mmc","ahb","rst"; pinctrl-names = "default","sleep"; pinctrl-0 = <&sdc1_pins_a>; pinctrl-1 = <&sdc1_pins_b>; max-frequency = <50000000>; bus-width = <4>; /*broken-cd;*/ /*cd-inverted*/ /*cd-gpios = <&pio PG 6 6 1 2 0>;*/ /* vmmc-supply = <®_3p3v>;*/ /* vqmc-supply = <®_3p3v>;*/ /* vdmc-supply = <®_3p3v>;*/ /*vmmc = "vcc-card";*/ /*vqmc = "";*/ /*vdmc = "";*/ /*sd-uhs-sdr50;*/ /*sd-uhs-ddr50;*/ /*sd-uhs-sdr104;*/ cap-sd-highspeed; cap-mmc-highspeed; cap-wait-while-busy; /*cap-sdio-irq;*/ /*keep-power-in-suspend;*/ /*ignore-pm-notify;*/ /*sunxi-power-save-mode;*/ /*sunxi-dly-400k = <1 0 0 0 0>; */ /*sunxi-dly-26M = <1 0 0 0 0>;*/ /*sunxi-dly-52M = <1 0 0 0 0>;*/ sunxi-dly-52M-ddr4 = <1 0 0 0 2>; /*sunxi-dly-52M-ddr8 = <1 0 0 0 0>;*/ sunxi-dly-104M = <1 0 0 0 1>; /*sunxi-dly-208M = <1 1 0 0 0>;*/ sunxi-dly-208M = <1 0 0 0 1>; /*sunxi-dly-104M-ddr = <1 0 0 0 0>;*/ /*sunxi-dly-208M-ddr = <1 0 0 0 0>;*/ status = "disabled"; }; disp: disp@01000000 { compatible = "allwinner,sunxi-disp"; reg = <0x0 0x01000000 0x0 0x3fffff>,/*de*/ <0x0 0x06510000 0x0 0xfff>,/*disp_if_top*/ <0x0 0x06511000 0x0 0xfff>,/*tcon_lcd0*/ <0x0 0x06504000 0x0 0x2000>;/*dsi0*/ interrupts = , , ; /*dsi0*/ clocks = <&clk_de>, <&clk_display_top>, <&clk_tcon_lcd>, <&clk_mipi_dphy0>, <&clk_mipi_host0>; boot_disp = <0>; fb_base = <0>; iommus = <&mmu_aw 0 0>; status = "okay"; }; lcd0: lcd0@01c0c000 { compatible = "allwinner,sunxi-lcd0"; pinctrl-names = "active","sleep"; status = "okay"; }; /* hdmi: hdmi@06000000 { compatible = "allwinner,sunxi-hdmi"; reg = <0x0 0x06000000 0x0 0x100000>; interrupts = ; clocks = <&clk_hdmi>,<&clk_hdmi_slow>,<&clk_hdmi_cec>; pinctrl-names = "ddc_active","ddc_sleep","cec_active", "cec_sleep"; pinctrl-0 = <&hdmi_ddc_pin_a>; pinctrl-1 = <&hdmi_ddc_pin_b>; pinctrl-2 = <&hdmi_cec_pin_a>; pinctrl-3 = <&hdmi_cec_pin_b>; status = "okay"; }; tv0: tv0@06524000 { compatible = "allwinner,sunxi-tv"; reg = <0x0 0x06520000 0x0 0x100>, <0x0 0x06524000 0x0 0x3fc>; clocks = <&clk_tve_top>,<&clk_tve>; device_type = "tv0"; pinctrl-names = "active","sleep"; status = "disabled"; }; vdpo0: vdpo0@06542000 { compatible = "allwinner,sunxi-vdpo"; reg = <0x0 0x06542000 0x0 0xfff>; clocks = <&clk_vdpo>; device_type = "vdpo0"; pinctrl-names = "active","sleep"; interrupts = ; status = "okay"; }; */ soc_tr: tr@01000000 { compatible = "allwinner,sun50i-tr"; reg = <0x0 0x01000000 0x0 0x000200bc>; interrupts = ; clocks = <&clk_de>; status = "okay"; }; g2d: g2d@01480000 { compatible = "allwinner,sunxi-g2d"; reg = <0x0 0x01480000 0x0 0xbffff>; interrupts = ; clocks = <&clk_g2d>; iommus = <&mmu_aw 6 1>; status = "okay"; }; dspo: dspo@0 { compatible = "allwinner,sunxi-dspo"; reg = <0x0 0x06543000 0x0 0x3ff>; interrupts = ; clocks = <&clk_dspo>; pinctrl-names = "bt656-seperate","bt656-seperate-sleep", "bt656-embed","bt656-embed-sleep", "bt1120-seperate","bt1120-seperate-sleep", "bt1120-embed","bt1120-embed-sleep"; status = "okay"; pinctrl-0 = <&bt656_sep_pins_a>; pinctrl-1 = <&bt656_sep_pins_b>; pinctrl-2 = <&bt656_emb_pins_a>; pinctrl-3 = <&bt656_emb_pins_b>; pinctrl-4 = <&bt1120_sep_pins_a>; pinctrl-5 = <&bt1120_sep_pins_b>; pinctrl-6 = <&bt1120_emb_pins_a>; pinctrl-7 = <&bt1120_emb_pins_b>; }; nna: nna@02400000 { compatible = "allwinner,sunxi-nna"; reg = <0x0 0x02400000 0x0 0x1ffff>; interrupts = ; clocks = <&clk_nna>, <&clk_nna_rst>; iommus = <&mmu_aw 2 1>; status = "okay"; }; pwm: pwm@0300a000 { compatible = "allwinner,sunxi-pwm"; reg = <0x0 0x0300a000 0x0 0x400>; status = "okay"; clocks = <&clk_pwm>; pwm-number = <10>; pwm-base = <0x0>; pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>, <&pwm5>, <&pwm6>, <&pwm7>, <&pwm8>, <&pwm9>; }; pwm0: pwm0@0300a000 { compatible = "allwinner,sunxi-pwm0"; pinctrl-names = "active", "sleep"; pinctrl-0 = <&pwm0_pins_a>; pinctrl-1 = <&pwm0_pins_b>; status = "okay"; reg_base = <0x0300a000>; }; pwm1: pwm1@0300a000 { compatible = "allwinner,sunxi-pwm1"; pinctrl-names = "active", "sleep"; reg_base = <0x0300a000>; pinctrl-0 = <&pwm1_pins_a>; pinctrl-1 = <&pwm1_pins_b>; status = "okay"; }; pwm2: pwm2@0300a000 { compatible = "allwinner,sunxi-pwm2"; pinctrl-names = "active", "sleep"; reg_base = <0x0300a000>; pinctrl-0 = <&pwm2_pins_a>; pinctrl-1 = <&pwm2_pins_b>; status = "okay"; }; pwm3: pwm3@0300a000 { compatible = "allwinner,sunxi-pwm3"; pinctrl-names = "active", "sleep"; reg_base = <0x0300a000>; pinctrl-0 = <&pwm3_pins_a>; pinctrl-1 = <&pwm3_pins_b>; status = "okay"; }; pwm4: pwm4@0300a000 { compatible = "allwinner,sunxi-pwm4"; pinctrl-names = "active", "sleep"; reg_base = <0x0300a000>; pinctrl-0 = <&pwm4_pins_a>; pinctrl-1 = <&pwm4_pins_b>; status = "okay"; }; pwm5: pwm5@0300a000 { compatible = "allwinner,sunxi-pwm5"; pinctrl-names = "active", "sleep"; reg_base = <0x0300a000>; pinctrl-0 = <&pwm5_pins_a>; pinctrl-1 = <&pwm5_pins_b>; status = "okay"; }; pwm6: pwm6@0300a000 { compatible = "allwinner,sunxi-pwm6"; pinctrl-names = "active", "sleep"; reg_base = <0x0300a000>; pinctrl-0 = <&pwm6_pins_a>; pinctrl-1 = <&pwm6_pins_b>; status = "okay"; }; pwm7: pwm7@0300a000 { compatible = "allwinner,sunxi-pwm7"; pinctrl-names = "active", "sleep"; reg_base = <0x0300a000>; pinctrl-0 = <&pwm7_pins_a>; pinctrl-1 = <&pwm7_pins_b>; status = "okay"; }; pwm8: pwm8@0300a000 { compatible = "allwinner,sunxi-pwm8"; pinctrl-names = "active", "sleep"; reg_base = <0x0300a000>; pinctrl-0 = <&pwm8_pins_a>; pinctrl-1 = <&pwm8_pins_b>; status = "okay"; }; pwm9: pwm9@0300a000 { compatible = "allwinner,sunxi-pwm9"; pinctrl-names = "active", "sleep"; reg_base = <0x0300a000>; pinctrl-0 = <&pwm9_pins_a>; pinctrl-1 = <&pwm9_pins_b>; status = "okay"; }; boot_disp: boot_disp { compatible = "allwinner,boot_disp"; }; vind0:vind@0 { compatible = "allwinner,sunxi-vin-media", "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; device_id = <0>; vind0_clk = <300000000>; vind0_isp = <200000000>; reg = <0x0 0x06600800 0x0 0x200>, <0x0 0x06600000 0x0 0x800>; interrupts = ; clocks = <&clk_csi_top>, <&clk_pll_csi>, <&clk_csi_master0>, <&clk_hosc>, <&clk_pll_csi>, <&clk_csi_master1>, <&clk_hosc>, <&clk_pll_csi>, <&clk_isp>, <&clk_pll_uni>; pinctrl-names = "mclk0-default","mclk0-sleep","mclk1-default","mclk1-sleep"; pinctrl-0 = <&csi_mclk0_pins_a>; pinctrl-1 = <&csi_mclk0_pins_b>; pinctrl-2 = <&csi_mclk1_pins_a>; pinctrl-3 = <&csi_mclk1_pins_b>; status = "okay"; csi0:csi@0 { device_type = "csi0"; compatible = "allwinner,sunxi-csi"; reg = <0x0 0x06601000 0x0 0x1000>; interrupts = ; device_id = <0>; iommus = <&mmu_aw 4 1>; status = "okay"; }; csi1:csi@1 { device_type = "csi1"; compatible = "allwinner,sunxi-csi"; reg = <0x0 0x06602000 0x0 0x1000>; interrupts = ; pinctrl-names = "default","sleep"; pinctrl-0 = <&csi1_pins_a>; pinctrl-1 = <&csi1_pins_b>; device_id = <1>; iommus = <&mmu_aw 4 1>; status = "okay"; }; mipi0:mipi@0 { compatible = "allwinner,sunxi-mipi"; reg = <0x0 0x0660C000 0x0 0x1000>; interrupts = ; device_id = <0>; status = "okay"; }; isp0:isp@0 { compatible = "allwinner,sunxi-isp"; reg = <0x0 0x02100000 0x0 0x800>; interrupts = ; device_id = <0>; iommus = <&mmu_aw 5 1>; status = "okay"; }; isp1:isp@1 { compatible = "allwinner,sunxi-isp"; device_id = <1>; status = "okay"; }; scaler0:scaler@0 { compatible = "allwinner,sunxi-scaler"; reg = <0x0 0x02104000 0x0 0x400>; device_id = <0>; iommus = <&mmu_aw 5 1>; status = "okay"; }; scaler1:scaler@1 { compatible = "allwinner,sunxi-scaler"; reg = <0x0 0x02104400 0x0 0x400>; device_id = <1>; iommus = <&mmu_aw 5 1>; status = "okay"; }; scaler2:scaler@2 { compatible = "allwinner,sunxi-scaler"; reg = <0x0 0x02104800 0x0 0x400>; device_id = <2>; iommus = <&mmu_aw 5 1>; status = "okay"; }; scaler3:scaler@3 { compatible = "allwinner,sunxi-scaler"; reg = <0x0 0x02104C00 0x0 0x400>; device_id = <3>; iommus = <&mmu_aw 5 1>; status = "okay"; }; actuator0:actuator@0 { device_type = "actuator0"; compatible = "allwinner,sunxi-actuator"; actuator0_name = "ad5820_act"; actuator0_slave = <0x18>; actuator0_af_pwdn = <>; actuator0_afvdd = "afvcc-csi"; actuator0_afvdd_vol = <2800000>; status = "disabled"; }; flash0:flash@0 { device_type = "flash0"; compatible = "allwinner,sunxi-flash"; flash0_type = <2>; flash0_en = <>; flash0_mode = <>; flash0_flvdd = ""; flash0_flvdd_vol = <>; device_id = <0>; status = "disabled"; }; sensor0:sensor@0 { device_type = "sensor0"; compatible = "allwinner,sunxi-sensor"; clocks = <&clk_csi_master0>, <&clk_hosc>, <&clk_pll_csi>; pinctrl-names = "mclk0-default","mclk0-sleep"; pinctrl-0 = <&csi_mclk0_pins_a>; pinctrl-1 = <&csi_mclk0_pins_b>; sensor0_mname = "ov5640"; sensor0_twi_cci_id = <0>; sensor0_twi_addr = <0x78>; sensor0_mclk_id = <2>; sensor0_pos = "rear"; sensor0_isp_used = <0>; sensor0_fmt = <0>; sensor0_stby_mode = <0>; sensor0_vflip = <0>; sensor0_hflip = <0>; sensor0_iovdd-supply = <>; sensor0_iovdd_vol = <1800000>; sensor0_avdd-supply = <>; sensor0_avdd_vol = <2800000>; sensor0_dvdd-supply = <>; sensor0_dvdd_vol = <1200000>; sensor0_power_en = <>; sensor0_reset = <&pio PI 3 1 0 1 0>; sensor0_pwdn = <&pio PI 4 1 0 1 0>; flash_handle = <&flash0>; act_handle = <&actuator0>; device_id = <0>; status = "okay"; }; sensor1:sensor@1 { device_type = "sensor1"; compatible = "allwinner,sunxi-sensor"; clocks = <&clk_csi_master1>, <&clk_hosc>, <&clk_pll_csi>; pinctrl-names = "mclk1-default","mclk1-sleep"; pinctrl-0 = <&csi_mclk1_pins_a>; pinctrl-1 = <&csi_mclk1_pins_b>; sensor1_mname = "ov5647"; sensor1_twi_cci_id = <1>; sensor1_twi_addr = <0x6c>; sensor1_mclk_id = <3>; sensor1_pos = "front"; sensor1_isp_used = <0>; sensor1_fmt = <0>; sensor1_stby_mode = <0>; sensor1_vflip = <0>; sensor1_hflip = <0>; sensor1_iovdd-supply = <>; sensor1_iovdd_vol = <2800000>; sensor1_avdd-supply = <>; sensor1_avdd_vol = <2800000>; sensor1_dvdd-supply = <>; sensor1_dvdd_vol = <1500000>; sensor1_power_en = <>; sensor1_reset = <&pio PI 3 1 0 1 0>; sensor1_pwdn = <&pio PI 4 1 0 1 0>; flash_handle = <>; act_handle = <>; device_id = <1>; status = "okay"; }; vinc0:vinc@0 { device_type = "vinc0"; compatible = "allwinner,sunxi-vin-core"; reg = <0x0 0x06609000 0x0 0x200>; interrupts = ; vinc0_csi_sel = <1>; vinc0_mipi_sel = <0xff>; vinc0_isp_sel = <1>; vinc0_rear_sensor_sel = <0>; vinc0_front_sensor_sel = <0>; vinc0_sensor_list = <0>; device_id = <0>; iommus = <&mmu_aw 4 1>; status = "okay"; }; vinc1:vinc@1 { device_type = "vinc1"; compatible = "allwinner,sunxi-vin-core"; reg = <0x0 0x06609200 0x0 0x200>; interrupts = ; vinc1_csi_sel = <1>; vinc1_mipi_sel = <0xff>; vinc1_isp_sel = <1>; vinc1_rear_sensor_sel = <0>; vinc1_front_sensor_sel = <0>; vinc1_sensor_list = <0>; device_id = <1>; iommus = <&mmu_aw 4 1>; status = "disabled"; }; vinc2:vinc@2 { device_type = "vinc2"; compatible = "allwinner,sunxi-vin-core"; reg = <0x0 0x06609400 0x0 0x200>; interrupts = ; vinc2_csi_sel = <3>; vinc2_mipi_sel = <0xff>; vinc2_isp_sel = <1>; vinc2_rear_sensor_sel = <0>; vinc2_front_sensor_sel = <1>; vinc2_sensor_list = <0>; device_id = <2>; iommus = <&mmu_aw 4 1>; status = "disabled"; }; vinc3:vinc@3 { device_type = "vinc3"; compatible = "allwinner,sunxi-vin-core"; reg = <0x0 0x06609600 0x0 0x200>; interrupts = ; vinc3_csi_sel = <3>; vinc3_mipi_sel = <0xff>; vinc3_isp_sel = <1>; vinc3_rear_sensor_sel = <0>; vinc3_front_sensor_sel = <1>; vinc3_sensor_list = <0>; device_id = <3>; iommus = <&mmu_aw 4 1>; status = "disabled"; }; }; Vdevice: vdevice@0 { compatible = "allwinner,sun8i-vdevice"; device_type = "Vdevice"; interrupt-parent = <&pio>; interrupts = < PD 3 IRQ_TYPE_LEVEL_HIGH>; /* bank offset type */ pinctrl-names = "default"; pinctrl-0 = <&vdevice_pins_a>; test-gpios = <&pio PC 3 1 2 2 1>; suspend-gpios = <&r_pio PL 4 1 2 2 1>; /* PA 0 0=in/1=out drive pull level */ wakeup-source; status = "okay"; }; cryptoengine: ce@1904000 { compatible = "allwinner,sunxi-ce"; device_name = "ce"; reg = <0x0 0x01904000 0x0 0xa0>, <0x0 0x01904800 0x0 0xa0>; /* Unused */ interrupts = , ; /* Unused */ clock-frequency = <300000000>; /* 300MHz */ clocks = <&clk_ce>, <&clk_pll_periph0x2>; }; nmi:nmi@0x01f00c00{ #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sunxi-nmi"; reg = <0x0 0x01f00c00 0x0 0x50>; nmi_irq_ctrl = <0x0c>; nmi_irq_en = <0x40>; nmi_irq_status = <0x10>; nmi_irq_mask = <0x50>; status = "okay"; }; /* nand0:nand0@04011000 { compatible = "allwinner,sun8iw16-nand"; device_type = "nand0"; reg = <0x0 0x04011000 0x0 0x1000>; interrupts = ; clocks = <&clk_pll_periph1x2>,<&clk_nand0>,<&clk_nand1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&nand0_pins_a &nand0_pins_b>; pinctrl-1 = <&nand0_pins_c>; nand0_regulator1 = "vcc-nand"; nand0_regulator2 = "none"; nand0_cache_level = <0x55aaaa55>; nand0_flush_cache_num = <0x55aaaa55>; nand0_capacity_level = <0x55aaaa55>; nand0_id_number_ctl = <0x55aaaa55>; nand0_print_level = <0x55aaaa55>; nand0_p0 = <0x55aaaa55>; nand0_p1 = <0x55aaaa55>; nand0_p2 = <0x55aaaa55>; nand0_p3 = <0x55aaaa55>; status = "okay"; }; */ sunxi_thermal_sensor:thermal_sensor{ compatible = "allwinner,thermal_sensor"; reg = <0x0 0x05070400 0x0 0x400>; interrupts = ; clocks = <&clk_hosc>,<&clk_ths>; /* * sensor 0 in CPU, sensor1 in VE, * sensor 2 in ISP, sensor 3 in DDR */ sensor_num = <4>; combine_num = <4>; shut_temp= <115000>;/*millicelsius*/ status = "okay"; ths_combine0:ths_combine0{ compatible = "allwinner,ths_combine"; #thermal-sensor-cells = <1>; combine_sensor_num = <1>; combine_sensor_type = "CPU"; combine_sensor_temp_type = "max"; combine_sensor_id = <0>; }; ths_combine1:ths_combine1{ compatible = "allwinner,ths_combine"; #thermal-sensor-cells = <1>; combine_sensor_num = <1>; combine_sensor_type = "VE"; combine_sensor_temp_type = "max"; combine_sensor_id = <1>; }; ths_combine2:ths_combine2{ compatible = "allwinner,ths_combine"; #thermal-sensor-cells = <1>; combine_sensor_num = <1>; combine_sensor_type = "ISP"; combine_sensor_temp_type = "max"; combine_sensor_id = <2>; }; ths_combine3:ths_combine3{ compatible = "allwinner,ths_combine"; #thermal-sensor-cells = <1>; combine_sensor_num = <1>; combine_sensor_type = "DDR"; combine_sensor_temp_type = "max"; combine_sensor_id = <3>; }; }; cpu_budget_cooling:cpu_budget_cool{ compatible = "allwinner,budget_cooling"; device_type = "cpu_budget_cooling"; #cooling-cells = <2>; status = "okay"; state_cnt = <2>; cluster_num = <1>; state0 = <1104000 1>; state1 = <600000 1>; }; thermal-zones{ cpu_thermal_zone{ polling-delay-passive = <1000>; polling-delay = <1000>; thermal-sensors = <&ths_combine0 0>; trips{ cpu_trip0:t0{ temperature = <80000>;/*millicelsius */ type = "passive"; hysteresis = <0>; }; crt_trip:t2{ temperature = <115000>; type = "critical"; hysteresis = <0>; }; }; cooling-maps{ bind0{ contribution = <0>; trip = <&cpu_trip0>; cooling-device = <&cpu_budget_cooling 1 1>; }; }; }; ve_thermal_zone{ polling-delay-passive = <1000>; polling-delay = <10000>; thermal-sensors = <&ths_combine1 1>; trips{ ve_crt_trip0:t0{ temperature = <115000>;/*millicelsius */ type = "critical"; hysteresis = <0>; }; }; }; isp_thermal_zone{ polling-delay-passive = <1000>; polling-delay = <10000>; thermal-sensors = <&ths_combine2 2>; trips{ isp_crt_trip0:t0{ temperature = <115000>;/*millicelsius */ type = "critical"; hysteresis = <0>; }; }; }; ddr_thermal_zone{ polling-delay-passive = <1000>; polling-delay = <10000>; thermal-sensors = <&ths_combine3 3>; trips{ ddr_crt_trip0:t0{ temperature = <115000>;/*millicelsius */ type = "critical"; hysteresis = <0>; }; }; }; }; gpadc:gpadc{ compatible = "allwinner,sunxi-gpadc"; reg = <0x0 0x05070000 0x0 0x400>; interrupts = ; clocks = <&clk_gpadc>; status = "disable"; }; gmac0: eth@05020000 { compatible = "allwinner,sunxi-gmac"; reg = <0x0 0x05020000 0x0 0xFFFF>, <0x0 0x03000030 0x0 0x4>; interrupts = ; interrupt-names = "gmacirq"; clocks = <&clk_gmac>, <&clk_ephy_25m>; clock-names = "gmac", "ephy"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&gmac_pins_a>; pinctrl-1 = <&gmac_pins_b>; phy-mode = "rmii"; use_ephy25m = <1>; tx-delay = <7>; rx-delay = <31>; phy-rst = <&pio PD 19 1 1 1 0>; gmac-power0; gmac-power1; gmac-power2; status = "okay"; }; }; };