/* * Allwinner Technology CO., Ltd. sun8iw7p1 platform */ /* kernel used */ /*/memreserve/ 0x43000000 0x00000800; /* super standby range : [0x43000000~0x43000800], size = 2K */ /memreserve/ 0x43080000 0x00010000; /* arisc dram code space range */ /memreserve/ 0x48000000 0x01000000; /* optee code space range */ #include #include #include "sun8iw7p1-clk.dtsi" #include "sun8iw7p1-pinctrl.dtsi" / { model = "sun8iw7p1"; compatible = "allwinner,sun8iw7p1", "allwinner,,sun8iw7p1"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; serial3 = &uart3; twi0 = &twi0; twi1 = &twi1; twi2 = &twi2; spi0 = &spi0; spi1 = &spi1; scr0 = &scr0; gmac0 = &gmac0; global_timer0 = &soc_timer0; mmc0 = &sdc0; mmc2 = &sdc2; nand0 =&nand0; disp = &disp; pwm = &pwm; pwm0 = &pwm0; tv0 = &tv0; hdmi = &hdmi; boot_disp = &boot_disp; }; chosen { bootargs = "earlyprintk=sunxi-uart,0x01c28000 loglevel=8 initcall_debug=1 console=ttyS0 init=/init"; linux,initrd-start = <0x0 0x0>; linux,initrd-end = <0x0 0x0>; }; firmware { optee { compatible = "linaro,optee-tz"; method = "smc"; }; }; psci { compatible = "arm,psci-0.2"; method = "smc"; psci_version = <0x84000000>; cpu_suspend = <0x84000001>; cpu_off = <0x84000002>; cpu_on = <0x84000003>; affinity_info = <0x84000004>; migrate = <0x84000005>; migrate_info_type = <0x84000006>; migrate_info_up_cpu = <0x84000007>; system_off = <0x84000008>; system_reset = <0x84000009>; }; cpus { enable-method = "allwinner,sun8iw7p1"; #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x0>; clocks = <&clk_pll_cpu>; clock-frequency = <1008000000>; clock-latency = <2000000>; /*if divide bin <&cpu_opp_l_table0 &cpu_opp_l_table1>*/ operating-points-v2 = <&cpu_opp_l_table0>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x1>; clocks = <&clk_pll_cpu>; clock-frequency = <1008000000>; clock-latency = <2000000>; /*if divide bin <&cpu_opp_l_table0 &cpu_opp_l_table1>*/ operating-points-v2 = <&cpu_opp_l_table0>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x2>; clocks = <&clk_pll_cpu>; clock-frequency = <1008000000>; clock-latency = <2000000>; /*if divide bin <&cpu_opp_l_table0 &cpu_opp_l_table1>*/ operating-points-v2 = <&cpu_opp_l_table0>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x3>; clocks = <&clk_pll_cpu>; clock-frequency = <1008000000>; clock-latency = <2000000>; /*if divide bin <&cpu_opp_l_table0 &cpu_opp_l_table1>*/ operating-points-v2 = <&cpu_opp_l_table0>; }; }; opp_dvfs_table:opp_dvfs_table { cluster_num = <1>; opp_table_count = <1>; cpu_opp_l_table0: opp_l_table0 { /* compatible = "operating-points-v2"; */ compatible = "allwinner,opp_l_table0"; opp-shared; opp00 { opp-hz = /bits/ 64 <480000000>; opp-microvolt = <1300000>; axi-bus-divide-ratio = <3>; clock-latency-ns = <2000000>; }; opp01 { opp-hz = /bits/ 64 <648000000>; opp-microvolt = <1300000>; axi-bus-divide-ratio = <3>; clock-latency-ns = <2000000>; }; opp02 { opp-hz = /bits/ 64 <720000000>; opp-microvolt = <1300000>; axi-bus-divide-ratio = <3>; clock-latency-ns = <2000000>; }; opp03 { opp-hz = /bits/ 64 <816000000>; opp-microvolt = <1300000>; axi-bus-divide-ratio = <3>; clock-latency-ns = <2000000>; }; opp04 { opp-hz = /bits/ 64 <912000000>; opp-microvolt = <1300000>; axi-bus-divide-ratio = <3>; clock-latency-ns = <2000000>; }; opp05 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <1300000>; axi-bus-divide-ratio = <3>; clock-latency-ns = <2000000>; }; }; }; n_brom { compatible = "allwinner,n-brom"; reg = <0x0 0x0 0x0 0xc000>; }; s_brom { compatible = "allwinner,s-brom"; reg = <0x0 0x0 0x0 0x10000>; }; prcm { compatible = "allwinner,prcm"; reg = <0x0 0x01f01400 0x0 0x400>; }; cpuscfg { compatible = "allwinner,cpuscfg"; reg = <0x0 0x01f01c00 0x0 0x400>; }; ion { compatible = "allwinner,sunxi-ion"; /*types list here: ION_HEAP_TYPE_SYSTEM = 0, ION_HEAP_TYPE_SYSTEM_CONTIG = 1, ION_HEAP_TYPE_CARVEOUT = 2, ION_HEAP_TYPE_CHUNK = 3, ION_HEAP_TYPE_DMA = 4 ION_HEAP_TYPE_SECURE = 6, **/ heap_sys_user@0{ compatible = "allwinner,sys_user"; heap-name = "sys_user"; heap-id = <0x0>; heap-base = <0x0>; heap-size = <0x0>; heap-type = "ion_system"; }; heap_sys_contig@0{ compatible = "allwinner,sys_contig"; heap-name = "sys_contig"; heap-id = <0x1>; heap-base = <0x0>; heap-size = <0x0>; heap-type = "ion_contig"; }; heap_cma@0{ compatible = "allwinner,cma"; heap-name = "cma"; heap-id = <0x4>; heap-base = <0x0>; heap-size = <0x0>; heap-type = "ion_cma"; }; heap_secure@0{ compatible = "allwinner,secure"; heap-name = "secure"; heap-id = <0x6>; heap-base = <0x0>; heap-size = <0x0>; heap-type = "ion_secure"; }; }; dram: dram { compatible = "allwinner,dram"; clocks = <&clk_pll_ddr>; clock-names = "pll_ddr"; dram_clk = <672>; dram_type = <3>; dram_zq = <0x003F3FDD>; dram_odt_en = <1>; dram_para1 = <0x10f41000>; dram_para2 = <0x00001200>; dram_mr0 = <0x1A50>; dram_mr1 = <0x40>; dram_mr2 = <0x10>; dram_mr3 = <0>; dram_tpr0 = <0x04E214EA>; dram_tpr1 = <0x004214AD>; dram_tpr2 = <0x10A75030>; dram_tpr3 = <0>; dram_tpr4 = <0>; dram_tpr5 = <0>; dram_tpr6 = <0>; dram_tpr7 = <0>; dram_tpr8 = <0>; dram_tpr9 = <0>; dram_tpr10 = <0>; dram_tpr11 = <0>; dram_tpr12 = <168>; dram_tpr13 = <0x823>; }; memory@40000000 { device_type = "memory"; reg = <0x00000000 0x40000000 0x00000000 0x40000000>; }; gic: interrupt-controller@1c81000 { compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <0>; device_type = "gic"; interrupt-controller; reg = <0x0 0x01c81000 0 0x1000>, /* GIC Dist */ <0x0 0x01c82000 0 0x2000>, /* GIC CPU */ <0x0 0x01c84000 0 0x2000>, /* GIC VCPU Control */ <0x0 0x01c86000 0 0x2000>; /* GIC VCPU */ interrupts = ; /* GIC Maintenence IRQ */ }; sid: sunxi-sid@01c14000 { compatible = "allwinner,sunxi-sid"; device_type = "sid"; reg = <0x0 0x01c14000 0 0x0200>; }; chipid: sunxi-chipid@01c14200 { compatible = "allwinner,sunxi-chipid"; device_type = "chipid"; reg = <0x0 0x01c14200 0 0x0200>; }; timer { compatible = "arm,armv7-timer"; interrupts = , /* Secure Phys IRQ */ ; /* Non-secure Phys IRQ */ clock-frequency = <24000000>; arm,cpu-registers-not-fw-configured; }; wdt: watchdog@01c20ca0 { compatible = "allwinner,sun4i-wdt"; reg = <0x0 0x01c20c90 0 0x18>; }; pmu { compatible = "arm,cotex-a7-pmu"; interrupts = , , , ; }; dvfs_table: dvfs_table { compatible = "allwinner,dvfs_table"; max_freq = <1200000000>; min_freq = <480000000>; lv_count = <8>; lv1_freq = <1200000000>; lv1_volt = <1300>; lv2_freq = <1104000000>; lv2_volt = <1240>; lv3_freq = <1008000000>; lv3_volt = <1160>; lv4_freq = <912000000>; lv4_volt = <1100>; lv5_freq = <720000000>; lv5_volt = <1000>; lv6_freq = <0>; lv6_volt = <1000>; lv7_freq = <0>; lv7_volt = <1000>; lv8_freq = <0>; lv8_volt = <1000>; }; dramfreq { compatible = "allwinner,sunxi-dramfreq"; reg = <0x0 0x01c62000 0x0 0x1000>, <0x0 0x01c63000 0x0 0x1000>, <0x0 0x01c20000 0x0 0x800>; interrupts = ; clocks = <&clk_pll_ddr>, <&clk_ahb1>; status = "okay"; }; uboot: uboot { }; gpu: gpu@0x01c40000 { compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0x01c40000 0x0 0x10000>; interrupts = , , , , , ; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clocks = <&clk_pll_gpu>, <&clk_gpu>; }; soc: soc@01c00000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; device_type = "soc"; sram-controller@01c00000 { device_type = "sram-controller"; compatible = "allwinner,sram_ctrl"; reg = <0x0 0x01c00000 0x0 0x24>; #address-cells = <1>; #size-cells = <1>; sram_a: sram@00000000 { compatible = "mmio-sram"; reg = <0x00000000 0xc000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00000000 0xc000>; emac_sram: sram-section@8000 { compatible = "allwinner,sun4i-a10-sram-a3-a4"; #size-cells = <1>; reg = <0x8000 0x4000>; status = "okay"; }; }; sram_d: sram@00010000 { compatible = "mmio-sram"; reg = <0x00010000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00010000 0x1000>; otg_sram: sram-section@0000 { compatible = "allwinner,sun4i-a10-sram-d"; #size-cells = <1>; reg = <0x0000 0x1000>; status = "disabled"; }; }; }; dma0:dma-controller@01c02000 { compatible = "allwinner,sun8i-dma"; reg = <0x0 0x01c02000 0x0 0x1000>; interrupts = ; clocks = <&clk_dma>; #dma-cells = <1>; }; mbus0:mbus-controller@01c62000 { compatible = "allwinner,sun8i-mbus"; reg = <0x0 0x01c62000 0x0 0x110>; #mbus-cells = <1>; }; arisc { compatible = "allwinner,sunxi-arisc"; #address-cells = <2>; #size-cells = <2>; clocks = <&clk_losc>, <&clk_iosc>, <&clk_hosc>, <&clk_pll_periph0>; clock-names = "losc", "iosc", "hosc", "pll_periph0"; powchk_used = <0x0>; power_reg = <0x02309621>; system_power = <50>; }; arisc_space { compatible = "allwinner,arisc_space"; /* num dst offset size */ space1 = <0x00040000 0x00000000 0x0000c000>; /*srama2*/ space2 = <0x43080000 0x00000000 0x00010000>; /*dram*/ space3 = <0x00000000 0x00000000 0x00000000>; /*para*/ space4 = <0x0004b800 0x00000000 0x00000800>; /*msgpool*/ }; standby_space { compatible = "allwinner,standby_space"; /* num dst offset size */ space1 = <0x43000000 0x00000000 0x00000800>; }; msgbox: msgbox@1c17000 { compatible = "allwinner,msgbox"; clocks = <&clk_msgbox>; clock-names = "clk_msgbox"; reg = <0x0 0x01c17000 0x0 0x1000>; interrupts = ; status = "okay"; }; hwspinlock: hwspinlock@1c18000 { compatible = "allwinner,sunxi-hwspinlock"; clocks = <&clk_hwspinlock_rst>, <&clk_hwspinlock_bus>; clock-names = "clk_hwspinlock_rst", "clk_hwspinlock_bus"; reg = <0x0 0x01c18000 0x0 0x1000>; num-locks = <8>; /* the number hwspinlock */ status = "okay"; }; s_cir0: s_cir@0x01f02000 { compatible = "allwinner,s_cir"; reg = <0x0 0x01f02000 0x0 0x400>; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&s_cir0_pins_a>; clocks = <&clk_hosc>,<&clk_cpurcir>; ir_power_key_code = <0x1a>; ir_addr_code = <0xfb04>; supply = ""; supply_vol = ""; status = "okay"; }; s_uart0: s_uart@0x01f02800 { compatible = "allwinner,s_uart"; reg = <0x0 0x01f02800 0x0 0x400>; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&s_uart0_pins_a>; status = "okay"; }; s_twi0: s_twi@0x01f02400 { compatible = "allwinner,s_twi"; reg = <0x0 0x01f02400 0x0 0x400>; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&s_twi0_pins_a>; status = "okay"; }; s_cpuscfg: s_cpuscfg@0x01f01c00 { compatible = "allwinner,s_cpuscfg"; reg = <0x0 0x01f01c00 0x0 0x400>; status = "okay"; }; box_start_os: box_start_os0 { compatible = "allwinner,box_start_os"; start_type = <0x0>; irkey_used = <0x0>; pmukey_used = <0x0>; pmukey_num = <0x0>; led_power = <0x0>; led_state = <0x0>; status = "disable"; }; soc_timer0: timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; device_type = "soc_timer"; reg = <0x0 0x01c20c00 0x0 0x90>; interrupts = ; /* On FPGA, timer can only use the losc. * On IC, timer should use the hosc. */ clocks = <&clk_hosc>, <&clk_losc>; }; rtc: rtc@01f000000 { compatible = "allwinner,sun8i-rtc"; device_type = "rtc"; reg = <0x0 0x01f00000 0x0 0x1FC>; interrupts = ; gpr_offset = <0x100>; gpr_len = <4>; }; ve: ve@01c0e000 { compatible = "allwinner,sunxi-cedar-ve"; reg = <0x0 0x01c0e000 0x0 0x1000>, <0x0 0x01c00000 0x0 0x10>, <0x0 0x01c20000 0x0 0x800>; interrupts = ; clocks = <&clk_pll_ve>, <&clk_ve>; }; uart0: uart@01c28000 { compatible = "allwinner,sun8i-uart"; device_type = "uart0"; reg = <0x0 0x01c28000 0x0 0x400>; interrupts = ; clocks = <&clk_uart0>; pinctrl-0 = <&uart0_pins_a>; pinctrl-1 = <&uart0_pins_b>; pinctrl-names = "default", "sleep"; uart0_port = <0>; uart0_type = <2>; status = "okay"; }; uart1: uart@01c28400 { compatible = "allwinner,sun8i-uart"; device_type = "uart1"; reg = <0x0 0x01c28400 0x0 0x400>; interrupts = ; clocks = <&clk_uart1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart1_pins_a>; pinctrl-1 = <&uart1_pins_b>; uart1_port = <1>; uart1_type = <8>; status = "okay"; }; uart2: uart@01c28800 { compatible = "allwinner,sun8i-uart"; device_type = "uart2"; reg = <0x0 0x01c28800 0x0 0x400>; interrupts = ; clocks = <&clk_uart2>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart2_pins_a>; pinctrl-1 = <&uart2_pins_b>; uart2_port = <2>; uart2_type = <4>; status = "disabled"; }; uart3: uart@01c28c00 { compatible = "allwinner,sun8i-uart"; device_type = "uart3"; reg = <0x0 0x01c28c00 0x0 0x400>; interrupts = ; clocks = <&clk_uart3>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart3_pins_a>; pinctrl-1 = <&uart3_pins_b>; uart3_port = <3>; uart3_type = <4>; status = "disabled"; }; twi0: twi@0x01c2ac00{ #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun8i-twi"; device_type = "twi0"; reg = <0x0 0x01c2ac00 0x0 0x400>; interrupts = ; clocks = <&clk_twi0>; clock-frequency = <400000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&twi0_pins_a>; pinctrl-1 = <&twi0_pins_b>; status = "disabled"; }; twi1: twi@0x01c2b000{ #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun8i-twi"; device_type = "twi1"; reg = <0x0 0x01c2b000 0x0 0x400>; interrupts = ; clocks = <&clk_twi1>; clock-frequency = <200000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&twi1_pins_a>; pinctrl-1 = <&twi1_pins_b>; status = "disabled"; }; twi2: twi@0x01c2b400{ #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun8i-twi"; device_type = "twi2"; reg = <0x0 0x01c2b400 0x0 0x400>; interrupts = ; clocks = <&clk_twi2>; clock-frequency = <200000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&twi2_pins_a>; pinctrl-1 = <&twi2_pins_b>; status = "disabled"; }; spi0: spi@01c68000 { #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun8i-spi"; device_type = "spi0"; reg = <0x0 0x01c68000 0x0 0x1000>; interrupts = ; clocks = <&clk_pll_periph0>, <&clk_spi0>; clock-frequency = <100000000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi0_pins_a &spi0_pins_b>; pinctrl-1 = <&spi0_pins_c>; spi0_cs_number = <1>; spi0_cs_bitmap = <1>; status = "disabled"; }; spi1: spi@01c69000 { #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sun8i-spi"; device_type = "spi1"; reg = <0x0 0x01c69000 0x0 0x1000>; interrupts = ; clocks = <&clk_pll_periph0>, <&clk_spi1>; clock-frequency = <100000000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi1_pins_a &spi1_pins_b>; pinctrl-1 = <&spi1_pins_c>; spi1_cs_number = <1>; spi1_cs_bitmap = <1>; status = "disabled"; }; usbc0:usbc0@0 { device_type = "usbc0"; compatible = "allwinner,sunxi-otg-manager"; usb_port_type = <2>; usb_detect_type = <1>; usb_detect_mode = <0>; usb_id_gpio; usb_det_vbus_gpio; usb_drv_vbus_gpio; usb_host_init_state = <0>; usb_regulator_io = "nocare"; usb_wakeup_suspend = <0>; usb_luns = <3>; usb_serial_unique = <0>; usb_serial_number = "20080411"; rndis_wceis = <1>; status = "okay"; }; udc:udc-controller@0x01c19000 { compatible = "allwinner,sunxi-udc"; reg = <0x0 0x01c19000 0x0 0x1000>, /*udc base*/ <0x0 0x01c00000 0x0 0x100>; /*sram base*/ interrupts = ; clocks = <&clk_usbphy0>, <&clk_usbotg>; status = "okay"; }; ehci0:ehci0-controller@0x01c1a000 { compatible = "allwinner,sunxi-ehci0"; reg = <0x0 0x01c1a000 0x0 0xFFF>, /*hci0 base*/ <0x0 0x01c00000 0x0 0x100>, /*sram base*/ <0x0 0x01c19000 0x0 0x1000>; /*otg base*/ interrupts = ; clocks = <&clk_usbphy0>, <&clk_usbehci0>; hci_ctrl_no = <0>; status = "okay"; }; ohci0:ohci0-controller@0x01c1a400 { compatible = "allwinner,sunxi-ohci0"; reg = <0x0 0x01c1a000 0x0 0xFFF>, /*hci0 base*/ <0x0 0x01c00000 0x0 0x100>, /*sram base*/ <0x0 0x01c19000 0x0 0x1000>; /*otg base*/ interrupts = ; clocks = <&clk_usbphy0>, <&clk_usbohci0>; hci_ctrl_no = <0>; status = "okay"; }; usbc1:usbc1@0 { device_type = "usbc1"; usb_drv_vbus_gpio; usb_host_init_state = <1>; usb_regulator_io = "nocare"; usb_wakeup_suspend = <0>; status = "okay"; }; ehci1:ehci1-controller@0x01c1b000 { compatible = "allwinner,sunxi-ehci1"; reg = <0x0 0x01c1b000 0x0 0xFFF>, /*hci1 base*/ <0x0 0x01c00000 0x0 0x100>, /*sram base*/ <0x0 0x01c19000 0x0 0x1000>; /*otg base*/ interrupts = ; clocks = <&clk_usbphy1>, <&clk_usbehci1>; hci_ctrl_no = <1>; status = "okay"; }; ohci1:ohci1-controller@0x01c1b400 { compatible = "allwinner,sunxi-ohci1"; reg = <0x0 0x01c1b000 0x0 0xFFF>, /*hci1 base*/ <0x0 0x01c00000 0x0 0x100>, /*sram base*/ <0x0 0x01c19000 0x0 0x1000>; /*otg base*/ interrupts = ; clocks = <&clk_usbphy1>, <&clk_usbohci1>; hci_ctrl_no = <1>; status = "okay"; }; usbc2:usbc2@0 { device_type = "usbc2"; usb_drv_vbus_gpio; usb_host_init_state = <1>; usb_regulator_io = "nocare"; usb_wakeup_suspend = <0>; status = "okay"; }; ehci2:ehci2-controller@0x01c1c000 { compatible = "allwinner,sunxi-ehci2"; reg = <0x0 0x01c1c000 0x0 0xFFF>, /*hci2 base*/ <0x0 0x01c00000 0x0 0x100>, /*sram base*/ <0x0 0x01c19000 0x0 0x1000>; /*otg base*/ interrupts = ; clocks = <&clk_usbphy2>, <&clk_usbehci2>; hci_ctrl_no = <2>; status = "okay"; }; ohci2:ohci2-controller@0x01c1c400 { compatible = "allwinner,sunxi-ohci2"; reg = <0x0 0x01c1c000 0x0 0xFFF>, /*hci2 base*/ <0x0 0x01c00000 0x0 0x100>, /*sram base*/ <0x0 0x01c19000 0x0 0x1000>; /*otg base*/ interrupts = ; clocks = <&clk_usbphy2>, <&clk_usbohci2>; hci_ctrl_no = <2>; status = "okay"; }; usbc3:usbc3@0 { device_type = "usbc3"; usb_drv_vbus_gpio; usb_host_init_state = <1>; usb_regulator_io = "nocare"; usb_wakeup_suspend = <0>; status = "okay"; }; ehci3:ehci3-controller@0x01c1d000 { compatible = "allwinner,sunxi-ehci3"; reg = <0x0 0x01c1d000 0x0 0xFFF>, /*hci2 base*/ <0x0 0x01c00000 0x0 0x100>, /*sram base*/ <0x0 0x01c19000 0x0 0x1000>; /*otg base*/ interrupts = ; clocks = <&clk_usbphy3>, <&clk_usbehci3>; hci_ctrl_no = <3>; status = "okay"; }; ohci3:ohci3-controller@0x01c1d400 { compatible = "allwinner,sunxi-ohci3"; reg = <0x0 0x01c1d000 0x0 0xFFF>, /*hci2 base*/ <0x0 0x01c00000 0x0 0x100>, /*sram base*/ <0x0 0x01c19000 0x0 0x1000>; /*otg base*/ interrupts = ; clocks = <&clk_usbphy3>, <&clk_usbohci3>; hci_ctrl_no = <3>; status = "okay"; }; codec:codec@0x01c22c00 { compatible = "allwinner,sunxi-internal-codec"; reg = <0x0 0x01c22c00 0x0 0x2bc>,/*digital baseadress*/ <0x0 0x01c22f00 0x0 0x4>;/*analog baseadress*/ clocks = <&clk_pll_audio>,<&clk_adda_com>; headphonevol = <0x3b>; spkervol = <0x1b>; maingain = <0x4>; hp_dirused = <0x0>; pa_sleep_time = <0x15e>; status = "disabled"; }; cpudai:cpudai0-controller@0x01c22c00 { compatible = "allwinner,sunxi-internal-cpudai"; reg = <0x0 0x01c22c00 0x0 0x2bc>;/*digital baseadress*/ status = "disabled"; }; daudio0:daudio@0x01c22000 { compatible = "allwinner,sunxi-daudio"; reg = <0x0 0x01c22000 0x0 0x70>; clocks = <&clk_pll_audio>,<&clk_i2s0>; pinctrl-names = "default","sleep"; pinctrl-0 = <&daudio0_pins_a>; pinctrl-1 = <&daudio0_pins_b>; pcm_lrck_period = <0x20>; slot_width_select = <0x20>; daudio_master = <0x04>; audio_format = <0x01>; signal_inversion = <0x01>; frametype = <0x0>; tdm_config = <0x01>; mclk_div = <0x0>; tdm_num = <0x0>; status = "disabled"; }; daudio1:daudio@0x01c22400 { compatible = "allwinner,sunxi-daudio"; reg = <0x0 0x01c22400 0x0 0x70>; pinctrl-names = "default","sleep"; pinctrl-0 = <&daudio1_pins_a>; pinctrl-1 = <&daudio1_pins_b>; clocks = <&clk_pll_audio>,<&clk_i2s1>; pcm_lrck_period = <0x20>; slot_width_select = <0x20>; daudio_master = <0x04>; audio_format = <0x01>; signal_inversion = <0x01>; frametype = <0x0>; tdm_config = <0x01>; mclk_div = <0x0>; tdm_num = <0x1>; status = "disabled"; }; audiohdmi:daudio@0x01c22800{ compatible = "allwinner,sunxi-tdmhdmi"; reg = <0x0 0x01c22800 0x0 0x58>; clocks = <&clk_pll_audio>,<&clk_i2s2>; status = "disabled"; }; sndcodec:sound@0 { compatible = "allwinner,sunxi-codec-machine"; interrupts = ; sunxi,cpudai-controller = <&cpudai>; sunxi,audio-codec = <&codec>; hp_detect_case = <0x00>; /* jack_det_gpio = <&pio PH 12 1 0 1 0>; */ /* invert: 0->high is plug_in, 1->high is plug_out */ jack_invert = <1>; status = "disabled"; }; snddaudio0:sound@1{ compatible = "allwinner,sunxi-daudio0-machine"; sunxi,daudio0-controller = <&daudio0>; status = "disabled"; }; snddaudio1:sound@2{ compatible = "allwinner,sunxi-daudio1-machine"; sunxi,daudio1-controller = <&daudio1>; status = "disabled"; }; sndhdmi:sound@3{ compatible = "allwinner,sunxi-hdmi-machine"; sunxi,hdmi-controller = <&audiohdmi>; status = "disabled"; }; sndspdif:sound@4{ compatible = "allwinner,sunxi-spdif-machine"; status = "disabled"; }; sdc2: sdmmc@01C11000 { compatible = "allwinner,sunxi-mmc-v4p10x"; device_type = "sdc2"; reg = <0x0 0x01C11000 0x0 0x1000>; interrupts = ; /* */ clocks = <&clk_hosc>,<&clk_pll_periph0>, <&clk_sdmmc2_module>,<&clk_sdmmc2_mode>, <&clk_sdmmc2_bus>,<&clk_sdmmc2_rst>; clock-names = "osc24m","pll_periph","mmc", "sdmmc2mod","ahb","rst"; pinctrl-names = "default","sleep"; pinctrl-0 = <&sdc2_pins_a>; pinctrl-1 = <&sdc2_pins_b>; bus-width = <8>; cap-mmc-highspeed; cap-sd-highspeed; mmc-ddr-1_8v; /*mmc-hs200-1_8v;*/ /*mmc-hs400-1_8v;*/ non-removable; /*max-frequency = <200000000>;*/ max-frequency = <50000000>; cap-erase; mmc-high-capacity-erase-size; /*-- speed mode --*/ /*sm0: DS26_SDR12*/ /*sm1: HSSDR52_SDR25*/ /*sm2: HSDDR52_DDR50*/ /*sm3: HS200_SDR104*/ /*sm4: HS400*/ /*-- frequency point -- /*f0: CLK_400K*/ /*f1: CLK_25M*/ /*f2: CLK_50M*/ /*f3: CLK_100M*/ /*f4: CLK_150M*/ /*f5: CLK_200M*/ sdc_tm4_sm0_freq0 = <0>; sdc_tm4_sm0_freq1 = <0>; sdc_tm4_sm1_freq0 = <0x00000000>; sdc_tm4_sm1_freq1 = <0>; sdc_tm4_sm2_freq0 = <0x00000000>; sdc_tm4_sm2_freq1 = <0>; sdc_tm4_sm3_freq0 = <0x05000000>; sdc_tm4_sm3_freq1 = <0x00000005>; sdc_tm4_sm4_freq0 = <0x00050000>; sdc_tm4_sm4_freq1 = <0x00000004>; /*vmmc-supply = <®_3p3v>;*/ /*vqmc-supply = <®_3p3v>;*/ /*vdmc-supply = <®_3p3v>;*/ /*vmmc = "vcc-card";*/ /*vqmc = "";*/ /*vdmc = "";*/ /*sunxi-power-save-mode;*/ /*status = "disabled";*/ status = "okay"; }; sdc0: sdmmc@01c0f000 { compatible = "allwinner,sunxi-mmc-v4p00x"; device_type = "sdc0"; reg = <0x0 0x01c0f000 0x0 0x1000>; /* only sdmmc0 */ interrupts = ; /* */ clocks = <&clk_hosc>,<&clk_pll_periph0>, <&clk_sdmmc0_mod>,<&clk_sdmmc0_bus>, <&clk_sdmmc0_rst>; clock-names = "osc24m","pll_periph","mmc","ahb","rst"; pinctrl-names = "default","sleep","uart_jtag"; pinctrl-0 = <&sdc0_pins_a>; pinctrl-1 = <&sdc0_pins_b>; pinctrl-2 = <&sdc0_pins_c>; max-frequency = <50000000>; bus-width = <4>; /*broken-cd;*/ /*non-removable;*/ /*cd-inverted*/ cd-gpios = <&pio PF 6 0 1 2 1>; /* vmmc-supply = <®_3p3v>;*/ /* vqmc-supply = <®_3p3v>;*/ /* vdmc-supply = <®_3p3v>;*/ /*vmmc = "vcc-card";*/ /*vqmc = "";*/ /*vdmc = "";*/ cap-sd-highspeed; cap-mmc-highspeed; cap-wait-while-busy; /*sd-uhs-sdr50;*/ /*sd-uhs-ddr50;*/ /*cap-sdio-irq;*/ /*keep-power-in-suspend;*/ /*ignore-pm-notify;*/ /*sunxi-power-save-mode;*/ /*sunxi-dly-400k = <1 0 0 0>; */ /*sunxi-dly-26M = <1 0 0 0>;*/ /*sunxi-dly-52M = <1 0 0 0>;*/ /*sunxi-dly-52M-ddr4 = <1 0 0 0>;*/ /*sunxi-dly-52M-ddr8 = <1 0 0 0>;*/ /*sunxi-dly-104M = <1 0 0 0>;*/ /*sunxi-dly-208M = <1 0 0 0>;*/ /*sunxi-dly-104M-ddr = <1 0 0 0>;*/ /*sunxi-dly-208M-ddr = <1 0 0 0>;*/ status = "okay"; /*status = "disabled";*/ }; sdc1: sdmmc@1C10000 { compatible = "allwinner,sunxi-mmc-v4p00x"; device_type = "sdc1"; reg = <0x0 0x1C10000 0x0 0x1000>; interrupts = ; /* */ clocks = <&clk_hosc>,<&clk_pll_periph0>, <&clk_sdmmc1_module>,<&clk_sdmmc1_mode>, <&clk_sdmmc1_bus>,<&clk_sdmmc1_rst>; clock-names = "osc24m","pll_periph","mmc", "sdmmc2mod","ahb","rst"; pinctrl-names = "default","sleep"; pinctrl-0 = <&sdc1_pins_a>; pinctrl-1 = <&sdc1_pins_b>; max-frequency = <50000000>; bus-width = <4>; /*broken-cd;*/ /*cd-inverted*/ /*cd-gpios = <&pio PG 6 6 1 2 0>;*/ /* vmmc-supply = <®_3p3v>;*/ /* vqmc-supply = <®_3p3v>;*/ /* vdmc-supply = <®_3p3v>;*/ /*vmmc = "vcc-card";*/ /*vqmc = "";*/ /*vdmc = "";*/ cap-sd-highspeed; cap-mmc-highspeed; /*sd-uhs-sdr50;*/ /*sd-uhs-ddr50;*/ /*sd-uhs-sdr104;*/ /*cap-sdio-irq;*/ /*keep-power-in-suspend;*/ /*ignore-pm-notify;*/ /*sunxi-power-save-mode;*/ /*sunxi-dly-400k = <1 0 0 0 0>; */ /*sunxi-dly-26M = <1 0 0 0 0>;*/ /*sunxi-dly-52M = <1 0 0 0 0>;*/ /*sunxi-dly-52M-ddr4 = <1 0 0 0 2>;*/ /*sunxi-dly-52M-ddr8 = <1 0 0 0 0>;*/ /*sunxi-dly-104M = <1 0 0 0 1>;*/ /*sunxi-dly-208M = <1 1 0 0 0>;*/ /*sunxi-dly-208M = <1 0 0 0 1>;*/ /*sunxi-dly-104M-ddr = <1 0 0 0 0>;*/ /*sunxi-dly-208M-ddr = <1 0 0 0 0>;*/ /*status = "okay";*/ status = "disabled"; }; disp: disp@01000000 { compatible = "allwinner,sunxi-disp"; reg = <0x0 0x01000000 0x0 0x00300000>,/*de*/ <0x0 0x01c0c000 0x0 0xfff>,/*tcon0*/ <0x0 0x01c0d000 0x0 0xfff>;/*tcon1*/ interrupts = , ; clocks = <&clk_de>,<&clk_tcon0>,<&clk_tcon1>; boot_disp = <0>; fb_base = <0>; status = "okay"; }; hdmi: hdmi@01ee0000 { compatible = "allwinner,sunxi-hdmi"; reg = <0x0 0x01ee0000 0x0 0x20000>; clocks = <&clk_hdmi>,<&clk_hdmi_slow>; status = "okay"; }; tv0: tv0@01c94000 { compatible = "allwinner,sunxi-tv"; reg = <0x0 0x01e00000 0x0 0x100>; clocks = <&clk_tve>; device_type = "tv0"; pinctrl-names = "active","sleep"; status = "disabled"; }; soc_tr: tr@01000000 { compatible = "allwinner,sun8iw11-tr"; reg = <0x0 0x01000000 0x0 0x000200bc>; interrupts = ; clocks = <&clk_de>; status = "disabled"; }; g2d: g2d@01e80000 { compatible = "allwinner,sunxi-g2d"; reg = <0x0 0x01e80000 0x0 0x800>; interrupts = ; status = "disabled"; }; pwm: pwm@01c23400 { compatible = "allwinner,sunxi-pwm"; reg = <0x0 0x01c23400 0x0 0x154>; pwm-number = <1>; pwm-base = <0x0>; pwms = <&pwm0>, <&pwm1>; }; pwm0: pwm0@01c23400 { compatible = "allwinner,sunxi-pwm0"; pinctrl-names = "active", "sleep"; reg_base = <0x01c23400>; reg_peci_offset = <0x00>; reg_peci_shift = <0x00>; reg_peci_width = <0x01>; reg_pis_offset = <0x04>; reg_pis_shift = <0x00>; reg_pis_width = <0x01>; reg_crie_offset = <0x10>; reg_crie_shift = <0x00>; reg_crie_width = <0x01>; reg_cfie_offset = <0x10>; reg_cfie_shift = <0x01>; reg_cfie_width = <0x01>; reg_cris_offset = <0x14>; reg_cris_shift = <0x00>; reg_cris_width = <0x01>; reg_cfis_offset = <0x14>; reg_cfis_shift = <0x01>; reg_cfis_width = <0x01>; reg_clk_src_offset = <0x20>; reg_clk_src_shift = <0x07>; reg_clk_src_width = <0x02>; reg_bypass_offset = <0x20>; reg_bypass_shift = <0x05>; reg_bypass_width = <0x01>; reg_clk_gating_offset = <0x20>; reg_clk_gating_shift = <0x04>; reg_clk_gating_width = <0x01>; reg_clk_div_m_offset = <0x20>; reg_clk_div_m_shift = <0x00>; reg_clk_div_m_width = <0x04>; reg_pdzintv_offset = <0x30>; reg_pdzintv_shift = <0x08>; reg_pdzintv_width = <0x08>; reg_dz_en_offset = <0x30>; reg_dz_en_shift = <0x00>; reg_dz_en_width = <0x01>; reg_enable_offset = <0x40>; reg_enable_shift = <0x00>; reg_enable_width = <0x01>; reg_cap_en_offset = <0x44>; reg_cap_en_shift = <0x00>; reg_cap_en_width = <0x01>; reg_period_rdy_offset = <0x60>; reg_period_rdy_shift = <0x0b>; reg_period_rdy_width = <0x01>; reg_pul_start_offset = <0x60>; reg_pul_start_shift = <0x0a>; reg_pul_start_width = <0x01>; reg_mode_offset = <0x60>; reg_mode_shift = <0x09>; reg_mode_width = <0x01>; reg_act_sta_offset = <0x60>; reg_act_sta_shift = <0x08>; reg_act_sta_width = <0x01>; reg_prescal_offset = <0x60>; reg_prescal_shift = <0x00>; reg_prescal_width = <0x08>; reg_entire_offset = <0x64>; reg_entire_shift = <0x10>; reg_entire_width = <0x10>; reg_active_offset = <0x64>; reg_active_shift = <0x00>; reg_active_width = <0x10>; }; pwm1: pwm1@01c23400 { compatible = "allwinner,sunxi-pwm1"; pinctrl-names = "active", "sleep"; reg_base = <0x01c23400>; reg_peci_offset = <0x00>; reg_peci_shift = <0x01>; reg_peci_width = <0x01>; reg_pis_offset = <0x04>; reg_pis_shift = <0x01>; reg_pis_width = <0x01>; reg_crie_offset = <0x10>; reg_crie_shift = <0x00>; reg_crie_width = <0x01>; reg_cfie_offset = <0x10>; reg_cfie_shift = <0x01>; reg_cfie_width = <0x01>; reg_cris_offset = <0x14>; reg_cris_shift = <0x01>; reg_cris_width = <0x01>; reg_cfis_offset = <0x14>; reg_cfis_shift = <0x01>; reg_cfis_width = <0x01>; reg_clk_src_offset = <0x20>; reg_clk_src_shift = <0x07>; reg_clk_src_width = <0x02>; reg_bypass_offset = <0x20>; reg_bypass_shift = <0x06>; reg_bypass_width = <0x01>; reg_clk_gating_offset = <0x20>; reg_clk_gating_shift = <0x04>; reg_clk_gating_width = <0x01>; reg_clk_div_m_offset = <0x20>; reg_clk_div_m_shift = <0x00>; reg_clk_div_m_width = <0x04>; reg_pdzintv_offset = <0x30>; reg_pdzintv_shift = <0x08>; reg_pdzintv_width = <0x08>; reg_dz_en_offset = <0x30>; reg_dz_en_shift = <0x00>; reg_dz_en_width = <0x01>; reg_enable_offset = <0x40>; reg_enable_shift = <0x01>; reg_enable_width = <0x01>; reg_cap_en_offset = <0x44>; reg_cap_en_shift = <0x01>; reg_cap_en_width = <0x01>; reg_period_rdy_offset = <0x80>; reg_period_rdy_shift = <0x0b>; reg_period_rdy_width = <0x01>; reg_pul_start_offset = <0x80>; reg_pul_start_shift = <0x0a>; reg_pul_start_width = <0x01>; reg_mode_offset = <0x80>; reg_mode_shift = <0x09>; reg_mode_width = <0x01>; reg_act_sta_offset = <0x80>; reg_act_sta_shift = <0x08>; reg_act_sta_width = <0x01>; reg_prescal_offset = <0x80>; reg_prescal_shift = <0x00>; reg_prescal_width = <0x08>; reg_entire_offset = <0x84>; reg_entire_shift = <0x10>; reg_entire_width = <0x10>; reg_active_offset = <0x84>; reg_active_shift = <0x00>; reg_active_width = <0x10>; }; boot_disp: boot_disp { compatible = "allwinner,boot_disp"; }; vind0:vind@0 { compatible = "allwinner,sunxi-vin-media", "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; clocks = <&clk_csi_s>, <&clk_pll_periph0>, <&clk_hosc>, <&clk_hosc>, <&clk_hosc>, <&clk_hosc>; pinctrl-names = "mclk0-default","mclk0-sleep","mclk1-default","mclk1-sleep"; device_id = <0>; status = "disabled"; csi_cci0:cci@0x01cb3000 { compatible = "allwinner,sunxi-csi_cci"; reg = <0x0 0x01cb3000 0x0 0x1000>; interrupts = ; device_id = <0>; status = "disabled"; }; csi0:csi@0x01c09000 { device_type = "csi0"; compatible = "allwinner,sunxi-csi"; reg = <0x0 0x01c09000 0x0 0x1000>; pinctrl-names = "default","sleep"; pinctrl-0 = <&csi0_pins_a>; pinctrl-1 = <&csi0_pins_b>; device_id = <0>; status = "okay"; }; csi1:csi@0x01c1d000 { device_type = "csi1"; compatible = "allwinner,sunxi-csi"; reg = <0x0 0X01c1d000 0x0 0x1000>; pinctrl-names = "default","sleep"; device_id = <1>; status = "okay"; }; mipi0:mipi@0 { compatible = "allwinner,sunxi-mipi"; device_id = <0>; status = "disabled"; }; mipi1:mipi@1 { compatible = "allwinner,sunxi-mipi"; device_id = <1>; status = "disabled"; }; isp0:isp@0 { compatible = "allwinner,sunxi-isp"; device_id = <0>; status = "okay"; }; isp1:isp@1 { compatible = "allwinner,sunxi-isp"; device_id = <1>; status = "okay"; }; scaler0:scaler@0 { compatible = "allwinner,sunxi-scaler"; device_id = <0>; status = "okay"; }; scaler1:scaler@1 { compatible = "allwinner,sunxi-scaler"; device_id = <1>; status = "okay"; }; scaler2:scaler@2 { compatible = "allwinner,sunxi-scaler"; device_id = <2>; status = "okay"; }; scaler3:scaler@3 { compatible = "allwinner,sunxi-scaler"; device_id = <3>; status = "okay"; }; actuator0:actuator@0 { device_type = "actuator0"; compatible = "allwinner,sunxi-actuator"; actuator0_name = "ad5820_act"; actuator0_slave = <0x18>; actuator0_af_pwdn = <>; actuator0_afvdd = "afvcc-csi"; actuator0_afvdd_vol = <2800000>; status = "disabled"; }; flash0:flash@0 { device_type = "flash0"; compatible = "allwinner,sunxi-flash"; flash0_type = <2>; flash0_en = <>; flash0_mode = <>; flash0_flvdd = ""; flash0_flvdd_vol = <>; status = "disabled"; }; sensor0:sensor@0{ device_type = "sensor0"; sensor0_mname = "ov5640"; sensor0_twi_addr = <0x78>; sensor0_pos = "rear"; sensor0_isp_used = <0>; sensor0_fmt = <0>; sensor0_stby_mode = <0>; sensor0_vflip = <0>; sensor0_hflip = <0>; sensor0_iovdd = "csi-iovdd"; sensor0_iovdd_vol = <2800000>; sensor0_avdd = ""; sensor0_avdd_vol = <2800000>; sensor0_dvdd = ""; sensor0_dvdd_vol = <1500000>; sensor0_power_en = <>; sensor0_reset = <&pio PH 13 1 0 1 0>; sensor0_pwdn = <&pio PH 16 1 0 1 0>; flash_handle = <&flash0>; act_handle = <&actuator0>; status = "okay"; }; sensor1:sensor@1{ device_type = "sensor1"; sensor1_mname = "ov2686"; sensor1_twi_addr = <0x20>; sensor1_pos = "front"; sensor1_isp_used = <0>; sensor1_fmt = <0>; sensor1_stby_mode = <0>; sensor1_vflip = <0>; sensor1_hflip = <0>; sensor1_iovdd = "csi-iovdd"; sensor1_iovdd_vol = <2800000>; sensor1_avdd = ""; sensor1_avdd_vol = <2800000>; sensor1_dvdd = ""; sensor1_dvdd_vol = <1500000>; sensor1_power_en = <>; sensor1_reset = <&pio PH 14 1 0 1 0>; sensor1_pwdn = <&pio PH 17 1 0 1 0>; flash_handle = <>; act_handle = <>; status = "okay"; }; vinc0:vinc@0 { device_type = "vinc0"; compatible = "allwinner,sunxi-vin-core"; interrupts = ; cci_sel = <1>; csi_sel = <0>; mipi_sel = <0xff>; isp_sel = <0>; scaler_sel = <0>; vinc0_sensor_list = <1>; isp_handle = <&isp0>; sensor_handle = <&sensor0>; device_id = <0>; status = "okay"; }; vinc1:vinc@1 { device_type = "vinc1"; compatible = "allwinner,sunxi-vin-core"; interrupts = ; cci_sel = <1>; csi_sel = <1>; mipi_sel = <0xff>; isp_sel = <1>; scaler_sel = <1>; vinc1_sensor_list = <1>; isp_handle = <&isp1>; sensor_handle = <&sensor1>; device_id = <1>; status = "okay"; }; }; Vdevice: vdevice@0{ compatible = "allwinner,sun8i-vdevice"; device_type = "Vdevice"; pinctrl-names = "default"; pinctrl-0 = <&vdevice_pins_a>; test-gpios = <&pio PG 10 1 2 2 1>; status = "okay"; }; cryptoengine: ce@1c15000 { compatible = "allwinner,sunxi-ce"; device_name = "ce"; reg = <0x0 0x01c15000 0x0 0x80>, <0x0 0x01c15800 0x0 0x80>; /* Unused */ interrupts = , ; /* Unused */ clock-frequency = <300000000 200000000>; /* 300MHz */ clocks = <&clk_ss>, <&clk_pll_periph0>; }; di:deinterlace@0x01400000{ #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sunxi-deinterlace"; reg = <0x0 0x01400000 0x0 0x77c>; interrupts = ; clocks = <&clk_deinterlace> ,<&clk_pll_periph0>; status = "okay"; }; scr0:smartcard@0x01c2c400{ #address-cells = <1>; #size-cells = <0>; compatible = "allwinner,sunxi-scr"; reg = <0x0 0x01c2c400 0x0 0x400>; interrupts = ; clocks = <&clk_scr>, <&clk_apb2>; clock-frequency = <24000000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&scr0_pins_a &scr0_pins_b>; pinctrl-1 = <&scr0_pins_c>; status = "disabled"; }; nand0:nand0@01c03000 { compatible = "allwinner,sun8iw7-nand"; device_type = "nand0"; reg = <0x0 0x01c03000 0x0 0x1000>; /* nand0 */ interrupts = ; clocks = <&clk_pll_periph0>,<&clk_nand>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&nand0_pins_a &nand0_pins_b>; pinctrl-1 = <&nand0_pins_c>; nand0_regulator1 = "vcc-nand"; nand0_regulator2 = "none"; nand0_cache_level = <0x55aaaa55>; nand0_flush_cache_num = <0x55aaaa55>; nand0_capacity_level = <0x55aaaa55>; nand0_id_number_ctl = <0x55aaaa55>; nand0_print_level = <0x55aaaa55>; nand0_p0 = <0x55aaaa55>; nand0_p1 = <0x55aaaa55>; nand0_p2 = <0x55aaaa55>; nand0_p3 = <0x55aaaa55>; status = "okay"; }; sunxi_thermal_sensor:thermal_sensor{ compatible = "allwinner,thermal_sensor"; reg = <0x0 0x01c25000 0x0 0x84>; interrupts = ; clocks = <&clk_hosc>,<&clk_ths>; clock-frequency = <6000000>; combine_num = <1>; sensor_num = <1>; shut_temp= <115>; status = "okay"; ths_combine0:ths_combine0{ compatible = "allwinner,ths_combine0"; #thermal-sensor-cells = <1>; combine_sensor_num = <1>; combine_sensor_type = "CPU"; combine_sensor_temp_type = "max"; combine_sensor_id = <0>; }; }; cpu_budget_cooling:cpu_budget_cool{ compatible = "allwinner,budget_cooling"; device_type = "cpu_budget_cooling"; #cooling-cells = <2>; status = "okay"; state_cnt = <5>; cluster_num = <1>; state0 = <1008000 4>; state1 = <1008000 3>; state2 = <1008000 2>; state3 = <1008000 1>; state4 = <504000 1>; }; gpu_cooling:gpu_cooling{ compatible = "allwinner,gpu_cooling"; device_type = "gpu_cooling"; reg = <0x0 0x0 0x0 0x0>; #cooling-cells = <2>; status = "okay"; state_cnt = <4>; state0 = <0>; state1 = <1>; state2 = <2>; state3 = <3>; }; thermal-zones{ soc_thermal{ polling-delay-passive = <1000>; polling-delay = <1000>; thermal-sensors = <&ths_combine0 0>; trips{ cpu_trip0:t0{ temperature = <85>; type = "passive"; hysteresis = <0>; }; cpu_trip1:t1{ temperature = <95>; type = "passive"; hysteresis = <0>; }; cpu_trip2:t2{ temperature = <105>; type = "passive"; hysteresis = <0>; }; gpu_trip0:t3{ temperature = <90>; type = "passive"; hysteresis = <0>; }; gpu_trip1:t4{ temperature = <100>; type = "passive"; hysteresis = <0>; }; gpu_trip2:t5{ temperature = <110>; type = "passive"; hysteresis = <0>; }; crt_trip:t6{ temperature = <115>; type = "critical"; hysteresis = <0>; }; }; cooling-maps{ bind0{ contribution = <0>; trip = <&cpu_trip0>; cooling-device = <&cpu_budget_cooling 1 1>; }; bind1{ contribution = <0>; trip = <&cpu_trip1>; cooling-device = <&cpu_budget_cooling 2 2>; }; bind2{ contribution = <0>; trip = <&cpu_trip2>; cooling-device = <&cpu_budget_cooling 3 4>; }; bind3{ contribution = <0>; trip = <&gpu_trip0>; cooling-device = <&gpu_cooling 1 1>; }; bind4{ contribution = <0>; trip = <&gpu_trip1>; cooling-device = <&gpu_cooling 2 2>; }; bind5{ contribution = <0>; trip = <&gpu_trip2>; cooling-device = <&gpu_cooling 3 3>; }; }; }; }; keyboard0:keyboard{ compatible = "allwinner,keyboard_2000mv"; reg = <0x0 0x01c21800 0x0 0x400>; interrupts = ; status = "okay"; key_cnt = <5>; key0 = <190 115>; key1 = <390 114>; key2 = <600 139>; key3 = <800 28>; key4 = <980 102>; }; gmac0: eth@01c30000 { compatible = "allwinner,sunxi-gmac"; reg = <0x0 0x01c30000 0x0 0x40000>, <0x0 0x01c00030 0x0 0x04>; interrupts = ; interrupt-names = "gmacirq"; clocks = <&clk_gmac>, <&clk_ephy>; clock-names = "gmac", "ephy"; phy-mode = "mii"; tx-delay = <7>; rx-delay = <31>; phy-rst; gmac-power0 = ""; gmac-power1 = ""; gmac-power2 = ""; status = "disabled"; }; emac0: eth@01c0B000 { compatible = "allwinner,sun4i-emac"; reg = <0x0 0x01c0b000 0x0 0x0c000>; pinctrl-names = "default"; interrupts = ; interrupt-names = "emacirq"; clock-names = "emac"; phy = <&phy1>; phy-rst; allwinner,sram = <&emac_sram 1>; emac_power1 = ""; emac_power2 = ""; emac_power3 = ""; status = "disabled"; }; mdio: mdio@01c0b080 { compatible = "allwinner,sun4i-a10-mdio"; reg = <0x0 0x01c0b080 0x0 0x14>; #address-cells = <1>; #size-cells = <0>; status = "okay"; phy1: ethernet-phy@1 { reg = <1>; }; }; cpucfg@01c25c00 { compatible = "allwinner,sunxi-cpucfg"; reg = <0x0 0x01c25c00 0x0 0x288>; }; sysctl@01c00000 { /** *sun8iw7 use the region of cpus to bring up cpu1~3, *in order to compatible with current framework, use *this node to transmit the parameters of cpus. */ compatible = "allwinner,sunxi-sysctl"; reg = <0x0 0x01f01c00 0x0 0x288>; cpu-soft-entry; }; }; };