/*
 *
 * include/linux/dma/sunxi/dma-sun50iw11.h
 *
 * Copyright (C) 2017 Allwinner.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 */

#ifndef __DMA_SUN50IW11__
#define __DMA_SUN50IW11__

/*
 * The source DRQ type and port corresponding relation
 */
#define DRQSRC_SRAM		0
#define DRQSRC_SDRAM		0
#define DRQSRC_SPDIFRX		2
#define DRQSRC_DAUDIO_0_RX	3
#define DRQSRC_DAUDIO_1_RX	4
#define DRQSRC_DAUDIO_2_RX	5
#define DRQSRC_R_AUDIO_CODEC	6
#define DRQSRC_R_DMIC		7
/* #define DRQSRC_RESERVE       8 */
#define DRQSRC_CE		9
#define DRQSRC_NAND		10
/* #define DRQSRC_RESERVE       11 */
#define DRQSRC_R_GPADC		12
/* #define DRQSRC_RESERVE       13 */
#define DRQSRC_UART0_RX		14
#define DRQSRC_UART1_RX		15
#define DRQSRC_UART2_RX		16
#define DRQSRC_UART3_RX		17
/* #define DRQSRC_RESERVE       18 */
/* #define DRQSRC_RESERVE       19 */
/* #define DRQSRC_RESERVE       20 */
/* #define DRQSRC_RESERVE       21 */
#define DRQSRC_SPI0_RX		22
#define DRQSRC_SPI1_RX		23
/* #define DRQSRC_RESERVE	24 */
/* #define DRQSRC_RESERVE	25 */
/* #define DRQSRC_RESERVE       26 */
/* #define DRQSRC_RESERVE       27 */
/* #define DRQSRC_RESERVE       28 */
/* #define DRQSRC_RESERVE       29 */
#define DRQSRC_OTG0_EP1		30
#define DRQSRC_OTG0_EP2		31
#define DRQSRC_OTG0_EP3		32
#define DRQSRC_OTG0_EP4		33
#define DRQSRC_OTG0_EP5		34
#define DRQSRC_OTG_EP1		DRQSRC_OTG0_EP1
#define DRQSRC_OTG_EP2		DRQSRC_OTG0_EP2
#define DRQSRC_OTG_EP3		DRQSRC_OTG0_EP3
#define DRQSRC_OTG_EP4		DRQSRC_OTG0_EP4
#define DRQSRC_OTG_EP5		DRQSRC_OTG0_EP5
#define DRQSRC_OTG1_EP1		35
#define DRQSRC_OTG1_EP2		36
#define DRQSRC_OTG1_EP3		37
#define DRQSRC_OTG1_EP4		38
#define DRQSRC_OTG1_EP5		39
/* reserved: 40~42 */
#define DRQSRC_TWI0_RX		43
#define DRQSRC_TWI1_RX		44
/* reserved: 45~47 */
#define DRQSRC_R_MAD		48
#define DRQSRC_R_TWI0		49  /* new */
#define DRQSRC_R_UART0		50  /* new */
#define DRQSRC_R_DAUDIO_0_RX	51  /* new */
#define DRQSRC_R_DAUDIO_1_RX	52  /* new */
#define DRQSRC_R_PSRAM		53  /* new */

/*
 * The destination DRQ type and port corresponding relation
 */
#define DRQDST_SRAM		0
#define DRQDST_SDRAM		0
#define DRQDST_SPDIFTX		2
#define DRQDST_DAUDIO_0_TX      3
#define DRQDST_DAUDIO_1_TX      4
#define DRQDST_DAUDIO_2_TX      5
#define DRQDST_R_AUDIO_CODEC	6
#define DRQDST_R_DMIC		7
/* #define DRQDST_RESERVE       8 */
#define DRQDST_CE		9
#define DRQDST_NAND0		10
/* reserved: 11~12 */
#define DRQDST_IR_TX		13
#define DRQDST_UART0_TX		14
#define DRQDST_UART1_TX		15
#define DRQDST_UART2_TX		16
#define DRQDST_UART3_TX		17
/* reserved: 18~21 */
#define DRQDST_SPI0_TX		22
#define DRQDST_SPI1_TX		23
/* reserved: 24~29 */
#define DRQDST_OTG0_EP1		30
#define DRQDST_OTG0_EP2		31
#define DRQDST_OTG0_EP3		32
#define DRQDST_OTG0_EP4		33
#define DRQDST_OTG0_EP5		34
#define DRQDST_OTG_EP1		DRQDST_OTG0_EP1
#define DRQDST_OTG_EP2		DRQDST_OTG0_EP2
#define DRQDST_OTG_EP3		DRQDST_OTG0_EP3
#define DRQDST_OTG_EP4		DRQDST_OTG0_EP4
#define DRQDST_OTG_EP5		DRQDST_OTG0_EP5
#define DRQDST_OTG1_EP1		35
#define DRQDST_OTG1_EP2		36
#define DRQDST_OTG1_EP3		37
#define DRQDST_OTG1_EP4		38
#define DRQDST_OTG1_EP5		39
/* reserved: 40~41 */
#define DRQDST_LEDC		42
#define DRQDST_TWI0_TX		43
#define DRQDST_TWI1_TX		44
/* reserved: 45~47 */
#define DRQDST_R_MAD		48
#define DRQDST_R_TWI0		49  /* new */
#define DRQDST_R_UART0		50  /* new */
#define DRQDST_R_DAUDIO_0_TX	51  /* new */
#define DRQDST_R_DAUDIO_1_TX	52  /* new */
#define DRQDST_R_PSRAM		53  /* new */

#endif /*__DMA_SUN50IW11__  */