/*
 * dspo_drv.h
 *
 * Copyright (c) 2007-2021 Allwinnertech Co., Ltd.
 * Author: zhengxiaobin <zhengxiaobin@allwinnertech.com>
 *
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */
#ifndef _DSPO_DRV_H
#define _DSPO_DRV_H

#include <linux/types.h>
#include <linux/ioctl.h>


enum dspo_output_mode {
	DSPO_MOD_NTSC = 0,
	DSPO_MOD_PAL = 1,
	DSPO_MOD_720X480I_60 = 2,
	DSPO_MOD_720X576I_60 = 3,
	DSPO_MOD_720X480P_60 = 4,
	DSPO_MOD_720X576P_50 = 5,

	DSPO_MOD_1280X720P_25 = 6,
	DSPO_MOD_1280X720P_50 = 7,
	DSPO_MOD_1280X720P_60 = 8,

	DSPO_MOD_1920X1080I_50 = 9,
	DSPO_MOD_1920X1080I_60 = 10,
	DSPO_MOD_1920X1080P_50 = 11,
	DSPO_MOD_1920X1080P_60 = 12,

	DSPO_MOD_3840X1080P_30 = 13,
	DSPO_CUSTOM_MODE = 14,//do not change this value
};

enum dspo_protocol_t {
	DSPO_BT1120,
	DSPO_BT656,
};

enum dspo_datawidth_t {
	DSPO_8_BIT,
	DSPO_16_BIT,
};

enum dspo_data_seq_t {
	DSPO_CB_Y_CR_Y,
	DSPO_CR_Y_CB_Y,
	DSPO_Y_CB_Y_CR,
	DSPO_Y_CR_Y_CB,
};

struct dspo_video_timings {
	enum dspo_output_mode tv_mode;
	__u32 pixel_clk;
	__u32 pixel_repeat; /* pixel repeat (pixel_repeat+1) times */
	__u32 x_res;
	__u32 y_res;
	__u32 hor_total_time;
	__u32 hor_back_porch;
	__u32 hor_front_porch;
	__u32 hor_sync_time;
	__u32 ver_total_time;
	__u32 ver_back_porch;
	__u32 ver_front_porch;
	__u32 ver_sync_time;
	__u32 hor_sync_polarity;	/* 0: negative, 1: positive */
	__u32 ver_sync_polarity;	/* 0: negative, 1: positive */
	bool b_interlace;
	__u32 vactive_space;
	__u32 trd_mode;
};

struct dspo_dclk_adjust_t {
	bool dclk_en;
	bool dclk_invt;
	__u32 dclk_dly_num;
};

struct dspo_config_t {
	enum dspo_protocol_t protocol;
	enum dspo_datawidth_t bit_width;
	bool separate_sync;
	enum dspo_data_seq_t data_seq_sel;
	struct dspo_dclk_adjust_t dclk_set;
	enum dspo_output_mode output_mode;
	struct dspo_video_timings timing_info;
};

enum dspo_infmt_t {
	DSPO_FORMAT_ARGB888 = 0,
	DSPO_FORMAT_YUV444 = 0x1,
	DSPO_FORMAT_YUV422_I_VYUY = 0x4,	/* MSB  V0-Y1-U0-Y0  LSB */
	DSPO_FORMAT_YUV422_I_YVYU = 0x5,	/* MSB  Y1-V0-Y0-U0  LSB */
	DSPO_FORMAT_YUV422_I_UYVY = 0x6,	/* MSB  U0-Y1-V0-Y0  LSB */
	DSPO_FORMAT_YUV422_I_YUYV = 0x7,	/* MSB  Y1-U0-Y0-V0  LSB */
	DSPO_FORMAT_YUV422_SP_UVUV = 0x8,	/* MSB  V1-U1-V0-U0  LSB */
	DSPO_FORMAT_YUV422_SP_VUVU = 0xa,	/* MSB  U1-V1-U0-V0  LSB */
	DSPO_FORMAT_YUV420_SP_UVUV = 0xc, /* MSB  V1-U1-V0-U0  LSB */
	DSPO_FORMAT_YUV420_SP_VUVU = 0xe, /* MSB  U1-V1-U0-V0  LSB */
	DSPO_FORMAT_INVALID,
};

struct dspo_dma_info_t {
	enum dspo_infmt_t fmt;
	__u32 height;
	__u32 width;
	int		 fd;
	unsigned long long addr[2];
	bool use_phy_addr;
};

#define SUNXI_DSPO_IOC_MAGIC 'P'
//#define SUNXI_G2D_IO(nr)          _IO(SUNXI_G2D_IOC_MAGIC, nr)
//#define SUNXI_G2D_IOR(nr, size)   _IOR(SUNXI_G2D_IOC_MAGIC, nr, size)
//#define SUNXI_G2D_IOW(nr, size)   _IOW(SUNXI_G2D_IOC_MAGIC, nr, size)
//#define SUNXI_G2D_IOWR(nr, size)  _IOWR(SUNXI_G2D_IOC_MAGIC, nr, size)

//definition of dspo ioctl command
#define DSPO_CMD_DEVICE_SWITCH _IOW(SUNXI_DSPO_IOC_MAGIC, 0x01, struct dspo_config_t)
#define DSPO_CMD_COMMIT _IOW(SUNXI_DSPO_IOC_MAGIC, 0x02, struct dspo_dma_info_t)
//#define DSPO_CMD_DESC_COMMIT _IOW(SUNXI_DSPO_IOC_MAGIC, 0x03, struct dspo_config_t)

#endif /*End of file*/