/*
* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
*
* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
* the the People's Republic of China and other countries.
* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
*
* DISCLAIMER
* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
* IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
* IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
*
*
* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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*/

#ifndef __PLATFORM_GPIO_H__
#define __PLATFORM_GPIO_H__

#ifdef __cplusplus
extern "C" {
#endif

#define GPIO_MAX_BANK PG_BASE
#define BANK_BOUNDARY PL_BASE
#define SUNXI_GPIO_PBASE 0x02000000
#define SUNXI_GPIO_RES_SIZE 0x07FF

/* sunxi gpio irq*/
#if defined(CONFIG_ARCH_SUN8IW21) /* ARM */
#define SUNXI_GIC_START 32
#define SUNXI_IRQ_GPIOA (SUNXI_GIC_START + 99)
#define SUNXI_IRQ_GPIOC (SUNXI_GIC_START + 103)
#define SUNXI_IRQ_GPIOD (SUNXI_GIC_START + 105)
#define SUNXI_IRQ_GPIOE (SUNXI_GIC_START + 107)
#define SUNXI_IRQ_GPIOF (SUNXI_GIC_START + 109)
#define SUNXI_IRQ_GPIOG (SUNXI_GIC_START + 111)
#define SUNXI_IRQ_GPIOH (SUNXI_GIC_START + 113)
#define SUNXI_IRQ_GPIOI (SUNXI_GIC_START + 115)
#elif defined(CONFIG_SOC_SUN20IW3) /* RISC-V */
#define SUNXI_IRQ_GPIOA (83)
#define SUNXI_IRQ_GPIOC (87)
#define SUNXI_IRQ_GPIOD (89)
#define SUNXI_IRQ_GPIOE (91)
#define SUNXI_IRQ_GPIOF (93)
#define SUNXI_IRQ_GPIOG (95)
#define SUNXI_IRQ_GPIOH (97)
#define SUNXI_IRQ_GPIOI (99)
#endif /* CONFIG_CORE_DSP0 */

typedef enum
{
    GPIO_PA0 = GPIOA(0),
    GPIO_PA1 = GPIOA(1),
    GPIO_PA2 = GPIOA(2),
    GPIO_PA3 = GPIOA(3),
    GPIO_PA4 = GPIOA(4),
    GPIO_PA5 = GPIOA(5),
    GPIO_PA6 = GPIOA(6),
    GPIO_PA7 = GPIOA(7),
    GPIO_PA8 = GPIOA(8),
    GPIO_PA9 = GPIOA(9),
    GPIO_PA10 = GPIOA(10),
    GPIO_PA11 = GPIOA(11),
    GPIO_PA12 = GPIOA(12),
    GPIO_PA13 = GPIOA(13),
    GPIO_PA14 = GPIOA(14),
    GPIO_PA15 = GPIOA(15),
    GPIO_PA16 = GPIOA(16),
    GPIO_PA17 = GPIOA(17),
    GPIO_PA18 = GPIOA(18),
    GPIO_PA19 = GPIOA(19),
    GPIO_PA20 = GPIOA(20),
    GPIO_PA21 = GPIOA(21),

    GPIO_PC0 = GPIOC(0),
    GPIO_PC1 = GPIOC(1),
    GPIO_PC2 = GPIOC(2),
    GPIO_PC3 = GPIOC(3),
    GPIO_PC4 = GPIOC(4),
    GPIO_PC5 = GPIOC(5),
    GPIO_PC6 = GPIOC(6),
    GPIO_PC7 = GPIOC(7),
    GPIO_PC8 = GPIOC(8),
    GPIO_PC9 = GPIOC(9),
    GPIO_PC10 = GPIOC(10),
    GPIO_PC11 = GPIOC(11),

    GPIO_PD0 = GPIOD(0),
    GPIO_PD1 = GPIOD(1),
    GPIO_PD2 = GPIOD(2),
    GPIO_PD3 = GPIOD(3),
    GPIO_PD4 = GPIOD(4),
    GPIO_PD5 = GPIOD(5),
    GPIO_PD6 = GPIOD(6),
    GPIO_PD7 = GPIOD(7),
    GPIO_PD8 = GPIOD(8),
    GPIO_PD9 = GPIOD(9),
    GPIO_PD10 = GPIOD(10),
    GPIO_PD11 = GPIOD(11),
    GPIO_PD12 = GPIOD(12),
    GPIO_PD13 = GPIOD(13),
    GPIO_PD14 = GPIOD(14),
    GPIO_PD15 = GPIOD(15),
    GPIO_PD16 = GPIOD(16),
    GPIO_PD17 = GPIOD(17),
    GPIO_PD18 = GPIOD(18),
    GPIO_PD19 = GPIOD(19),
    GPIO_PD20 = GPIOD(20),
    GPIO_PD21 = GPIOD(21),
    GPIO_PD22 = GPIOD(22),

    GPIO_PE0 = GPIOE(0),
    GPIO_PE1 = GPIOE(1),
    GPIO_PE2 = GPIOE(2),
    GPIO_PE3 = GPIOE(3),
    GPIO_PE4 = GPIOE(4),
    GPIO_PE5 = GPIOE(5),
    GPIO_PE6 = GPIOE(6),
    GPIO_PE7 = GPIOE(7),
    GPIO_PE8 = GPIOE(8),
    GPIO_PE9 = GPIOE(9),
    GPIO_PE10 = GPIOE(10),
    GPIO_PE11 = GPIOE(11),
    GPIO_PE12 = GPIOE(12),
    GPIO_PE13 = GPIOE(13),
    GPIO_PE14 = GPIOE(14),
    GPIO_PE15 = GPIOE(15),
    GPIO_PE16 = GPIOE(16),
    GPIO_PE17 = GPIOE(17),

    GPIO_PF0 = GPIOF(0),
    GPIO_PF1 = GPIOF(1),
    GPIO_PF2 = GPIOF(2),
    GPIO_PF3 = GPIOF(3),
    GPIO_PF4 = GPIOF(4),
    GPIO_PF5 = GPIOF(5),
    GPIO_PF6 = GPIOF(6),

    GPIO_PG0 = GPIOG(0),
    GPIO_PG1 = GPIOG(1),
    GPIO_PG2 = GPIOG(2),
    GPIO_PG3 = GPIOG(3),
    GPIO_PG4 = GPIOG(4),
    GPIO_PG5 = GPIOG(5),
    GPIO_PG6 = GPIOG(6),
    GPIO_PG7 = GPIOG(7),

    GPIO_PH0 = GPIOH(0),
    GPIO_PH1 = GPIOH(1),
    GPIO_PH2 = GPIOH(2),
    GPIO_PH3 = GPIOH(3),
    GPIO_PH4 = GPIOH(4),
    GPIO_PH5 = GPIOH(5),
    GPIO_PH6 = GPIOH(6),
    GPIO_PH7 = GPIOH(7),
    GPIO_PH8 = GPIOH(8),
    GPIO_PH9 = GPIOH(9),
    GPIO_PH10 = GPIOH(10),
    GPIO_PH11 = GPIOH(11),
    GPIO_PH12 = GPIOH(12),
    GPIO_PH13 = GPIOH(13),
    GPIO_PH14 = GPIOH(14),
    GPIO_PH15 = GPIOH(15),

    GPIO_PI0 = GPIOI(0),
    GPIO_PI1 = GPIOI(1),
    GPIO_PI2 = GPIOI(2),
    GPIO_PI3 = GPIOI(3),
    GPIO_PI4 = GPIOI(4),

    /* To aviod compile warnings. */
    GPIO_MAX = GPIOO(31),

} gpio_pin_t;

#ifdef __cplusplus
}
#endif
#endif /* __PLATFORM_GPIO_H__ */