/* * dspo_reg.h * * Copyright (c) 2007-2021 Allwinnertech Co., Ltd. * Author: zhengxiaobin * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * */ #ifndef DSPO_REG_H_ #define DSPO_REG_H_ // DSPO(Video data parallel output) // offset:0x00 typedef union { __u32 dwval; struct { __u32 dspo_mudule_en : 1; __u32 seperate_sync_en : 1; __u32 soft_rst : 1; __u32 dma_aidb_sel : 1; __u32 bist_mode : 1; __u32 res00 : 27; } bits; } dspo_ctrl_reg; // DSPO(Video data parallel output) // offset:0x04 typedef union { __u32 dwval; struct { __u32 output_data_width : 1; __u32 interlace_mode : 1; __u32 data_src_sel : 1; __u32 res00 : 1; __u32 embedded_sync_fmt : 1; __u32 res01 : 3; __u32 data_seq_sel : 2; __u32 res02 : 22; } bits; } dspo_fmt_reg; // DSPO(Video data parallel output) // offset:0x08 typedef union { __u32 dwval; struct { __u32 h_blank_pol : 1; __u32 v_blank_pol : 1; __u32 field_pol : 1; __u32 dclk_invert : 1; __u32 dclk_dly_num : 6; __u32 dclk_dly_en : 1; __u32 res00 : 21; } bits; } dspo_sync_ctrl_reg; // DSPO(Video data parallel output) // offset:0xc typedef union { __u32 dwval; struct { __u32 line_match_int_en : 1; __u32 vb_int_en : 1; __u32 res00 : 2; __u32 dma_desc_int_en : 1; __u32 dma_done_int_en : 1; __u32 line_int_en : 1; __u32 frame_int_en : 1; __u32 dma_uv_line_int_en : 1; __u32 line_buf_uv_underflow_int_en : 1; __u32 line_buf_y_underflow_int_en : 1; __u32 line_buf_uv_overflow_int_en : 1; __u32 line_buf_y_overflow_int_en : 1; __u32 res01 : 3; __u32 line_match_int_flag : 1; __u32 vb_int_flag : 1; __u32 res02 : 2; __u32 dma_desc_int_flag : 1; __u32 dma_done_int_flag : 1; __u32 line_int_flag : 1; __u32 frame_int_flag : 1; __u32 dma_uv_line_int_flag : 1; __u32 line_buf_uv_underflow_int_flag : 1; __u32 line_buf_y_underflow_int_flag : 1; __u32 line_buf_uv_overflow_int_flag : 1; __u32 line_buf_y_overflow_int_flag : 1; __u32 res03 : 3; } bits; } dspo_int_ctrl_reg; // DSPO(Video data parallel output) // offset:0x10 typedef union { __u32 dwval; struct { __u32 int_line_num : 12; __u32 res00 : 20; } bits; } dspo_line_int_num_reg; // DSPO(Video data parallel output) // offset:0x14 typedef union { __u32 dwval; struct { __u32 current_line : 13; __u32 res00 : 3; __u32 field_pol_sta : 1; __u32 res010 : 15; } bits; } dspo_status_reg; // DSPO(Video data parallel output) // offset:0x18 typedef union { __u32 dwval; struct { __u32 cb_hori_spl_type : 3; __u32 res00 : 1; __u32 cr_hori_spl_type : 3; __u32 res01 : 15; } bits; } dspo_hor_spl_ctrl_reg; // DSPO(Video data parallel output) // offset:0x1c typedef union { __u32 dwval; struct { __u32 y_val_range_min : 8; __u32 res00 : 8; __u32 y_val_range_max : 8; __u32 res01 : 8; } bits; } dspo_clamp_reg0; // DSPO(Video data parallel output) // offset:0x20 typedef union { __u32 dwval; struct { __u32 cb_val_range_min : 8; __u32 res00 : 8; __u32 cb_val_range_max : 8; __u32 res01 : 8; } bits; } dspo_clamp_reg1; // DSPO(Video data parallel output) // offset:0x24 typedef union { __u32 dwval; struct { __u32 cr_val_range_min : 8; __u32 res00 : 8; __u32 cr_val_range_max : 8; __u32 res01 : 8; } bits; } dspo_clamp_reg2; // offset:0x30 typedef union { __u32 dwval; struct { __u32 v_total_para : 13; __u32 res00 : 2; __u32 V_total_cfg_auto : 1; __u32 interlace_mode_op : 1; __u32 res01 : 15; } bits; } dspo_interlace_mode_reg; // offset:0x34 typedef union { __u32 dwval; struct { __u32 h_sync : 10; __u32 res00 : 6; __u32 h_fp : 12; __u32 res01 : 4; } bits; } dspo_h_timing_reg0; // offset:0x38 typedef union { __u32 dwval; struct { __u32 h_active : 13; __u32 res00 : 3; __u32 h_bp : 12; __u32 res01 : 4; } bits; } dspo_h_timing_reg1; // offset:0x3C typedef union { __u32 dwval; struct { __u32 v_sync : 10; __u32 res00 : 6; __u32 v_fp : 12; __u32 res01 : 4; } bits; } dspo_v_timing_reg0; // offset:0x40 typedef union { __u32 dwval; struct { __u32 v_active : 12; __u32 res00 : 4; __u32 v_bp : 12; __u32 res01 : 4; } bits; } dspo_v_timing_reg1; // offset:0x44 typedef union { __u32 dwval; struct { __u32 dma_start : 1; __u32 res01 : 31; } bits; } dspo_dma_start_reg; // offset:0x4C typedef union { __u32 dwval; struct { __u32 input_data_type : 4; __u32 res00 : 1; __u32 dma_block_size_sel : 2; __u32 descriptor_mode : 1; __u32 res01 : 1; __u32 dma_start_check_en : 1; __u32 res02 : 2; __u32 dma_start_check : 7; __u32 res03 : 6; __u32 tcon_tri_mode : 1; __u32 tcon_tri : 1; __u32 tcon_manu : 1; __u32 tcon_manu_en : 1; __u32 res04 : 3; } bits; } dspo_dma_tcon_ctrl_reg; // offset:0x50 typedef union { __u32 dwval; struct { __u32 y : 16; __u32 x : 16; } bits; } dspo_dma_size_reg; // offset:0x54 typedef union { __u32 dwval; struct { __u32 buf0_addr : 32; } bits; } dspo_dma_y_base_addr_reg; // offset:0x58 typedef union { __u32 dwval; struct { __u32 buf1_addr : 32; } bits; } dspo_dma_crcb_base_addr_reg; // offset:0x5C typedef union { __u32 dwval; struct { __u32 buf0_line_stride : 16; __u32 buf1_line_stride : 16; } bits; } dspo_dma_buf_line_stride_reg; // offset:0x60 typedef union { __u32 dwval; struct { __u32 desc_base_addr : 32; } bits; } dspo_desc_base_addr_reg; // offset:0x64 typedef union { __u32 dwval; struct { __u32 ceu_en : 1; } bits; } dspo_csc_ceu_ctl_reg; // offset:0x70~0x98 typedef union { __u32 dwval; struct { __u32 ceu_coef_mul_val : 13; __u32 res00 : 19; } bits; } dspo_csc_ceu_coef_mul_reg; // offset:0xA0~0xA8 typedef union { __u32 dwval; struct { __u32 ceu_coef_add_val : 19; __u32 res00 : 13; } bits; } dspo_csc_ceu_coef_reg; // offset:0xB0~0xB8 typedef union { __u32 dwval; struct { __u32 ceu_coef_range_max : 8; __u32 res00 : 8; __u32 ceu_coef_range_min : 8; __u32 res01 : 8; } bits; } dspo_csc_ceu_coef_rang_reg; // offset:0xC0 typedef union { __u32 dwval; struct { __u32 dma_mode_lb_y_cap : 12; __u32 res00 : 20; } bits; } dspo_line_buf_rang_reg0; // offset:0xC4 typedef union { __u32 dwval; struct { __u32 dma_mode_lb_uv_cap : 12; __u32 res00 : 20; } bits; } dspo_line_buf_rang_reg1; // offset:0xC8 typedef union { __u32 dwval; struct { __u32 aidb_mode_lb_cap : 12; __u32 res00 : 20; } bits; } dspo_line_buf_rang_reg2; // offset:0xCC typedef union { __u32 dwval; struct { __u32 line_buf_cap_rdy : 1; __u32 res00 : 31; } bits; } dspo_line_buf_rang_reg3; // offset:0xD0 typedef union { __u32 dwval; struct { __u32 aidb_capture_en : 1; __u32 aidb_first_frm_discard : 1; __u32 res00 : 2; __u32 aidb_tri_dly : 18; __u32 res01 : 10; } bits; } dspo_aidb_ctrl_reg; // offset:0xD4 typedef union { __u32 dwval; struct { __u32 aidb_v_blank_num : 31; } bits; } dspo_aidb_v_timing_reg0; // offset:0xD8 typedef union { __u32 dwval; struct { __u32 aidb_v_active_num : 31; } bits; } dspo_aidb_v_timing_reg1; // offset:0xDC typedef union { __u32 dwval; struct { __u32 aidb_h_blank_num : 31; } bits; } dspo_aidb_h_timing_reg0; // offset:0xE0 typedef union { __u32 dwval; struct { __u32 aidb_h_active_num : 31; } bits; } dspo_aidb_h_timing_reg1; // offset:0x100 typedef union { __u32 dwval; struct { __u32 bist_en : 1; __u32 bist_wdata_pat : 3; __u32 bist_addr_mode_sel : 1; __u32 bist_reg_sel : 3; __u32 bist_busy : 1; __u32 bist_stop : 1; __u32 bist_err_cyc : 2; __u32 bist_err_pat : 3; __u32 bist_err_sta : 1; __u32 res00 : 16; } bits; } dspo_bist_ctrl_reg; // offset:0x104 typedef union { __u32 dwval; struct { __u32 bist_start_addr : 31; } bits; } dspo_bist_start_addr_reg; // offset:0x108 typedef union { __u32 dwval; struct { __u32 bist_end_addr : 31; } bits; } dspo_bist_end_addr_reg; // offset:0x10C typedef union { __u32 dwval; struct { __u32 bist_data_mask : 31; } bits; } dspo_bist_data_mask_reg; typedef union { __u32 dwval; struct { __u32 res00 : 31; } bits; } dspo_res_reg; typedef struct { dspo_ctrl_reg module_ctrl; // 0x00 dspo_fmt_reg fmt_ctrl; // 0x04 dspo_sync_ctrl_reg sync_ctrl; // 0x08 dspo_int_ctrl_reg int_ctrl; // 0x0c dspo_line_int_num_reg line_int_num; // 0x10 dspo_status_reg status; // 0x14 dspo_hor_spl_ctrl_reg hor_spl_ctrl; // 0x18 dspo_clamp_reg0 clamp0; // 0x1c dspo_clamp_reg1 clamp1; // 0x20 dspo_clamp_reg2 clamp2; // 0x24 dspo_res_reg res000; // 0x28 dspo_res_reg res001; // 0x2C dspo_interlace_mode_reg interlace_mode; // 0x30 dspo_h_timing_reg0 h_timing0; // 0x34 dspo_h_timing_reg1 h_timing1; // 0x38 dspo_v_timing_reg0 v_timing0; // 0x3C dspo_v_timing_reg1 v_timing1; // 0x40 dspo_dma_start_reg dma_start; // 0x44 dspo_res_reg res002; // 0x48 dspo_dma_tcon_ctrl_reg dma_tcon_ctrl; // 0x4C dspo_dma_size_reg dma_size; // 0x50 dspo_dma_y_base_addr_reg dma_y_base_addr; // 0x54 dspo_dma_crcb_base_addr_reg dma_crcb_base_addr; // 0x58 dspo_dma_buf_line_stride_reg dma_buf_line_stride; // 0x5C dspo_desc_base_addr_reg desc_base_addr; // 0x60 dspo_csc_ceu_ctl_reg csc_ceu_ctl; // 0x64 dspo_res_reg res003; // 0x68 dspo_res_reg res004; // 0x6C dspo_csc_ceu_coef_mul_reg csc_ceu_coef_mul_rr; // 0x70 dspo_csc_ceu_coef_mul_reg csc_ceu_coef_mul_rg; // 0x74 dspo_csc_ceu_coef_mul_reg csc_ceu_coef_mul_rb; // 0x78 dspo_res_reg res005; // 0x7C dspo_csc_ceu_coef_mul_reg csc_ceu_coef_mul_gr; // 0x80 dspo_csc_ceu_coef_mul_reg csc_ceu_coef_mul_gg; // 0x84 dspo_csc_ceu_coef_mul_reg csc_ceu_coef_mul_gb; // 0x88 dspo_res_reg res006; // 0x8C dspo_csc_ceu_coef_mul_reg csc_ceu_coef_mul_br; // 0x90 dspo_csc_ceu_coef_mul_reg csc_ceu_coef_mul_bg; // 0x94 dspo_csc_ceu_coef_mul_reg csc_ceu_coef_mul_bb; // 0x98 dspo_res_reg res007; // 0x9C dspo_csc_ceu_coef_reg csc_ceu_coef_rc; // 0xA0 dspo_csc_ceu_coef_reg csc_ceu_coef_gc; // 0xA4 dspo_csc_ceu_coef_reg csc_ceu_coef_bc; // 0xA8 dspo_res_reg res008; // 0xAC dspo_csc_ceu_coef_rang_reg csc_ceu_coef_rang_y; // 0xB0 dspo_csc_ceu_coef_rang_reg csc_ceu_coef_rang_u; // 0xB4 dspo_csc_ceu_coef_rang_reg csc_ceu_coef_rang_v; // 0xB8 dspo_res_reg res009; // 0xBC dspo_line_buf_rang_reg0 line_buf_rang0; // 0xC0 dspo_line_buf_rang_reg1 line_buf_rang1; // 0xC4 dspo_line_buf_rang_reg2 line_buf_rang2; // 0xC8 dspo_line_buf_rang_reg3 line_buf_rang3; // 0xCC dspo_aidb_ctrl_reg aidb_ctrl; // 0xD0 dspo_aidb_v_timing_reg0 aidb_v_timing0; // 0xD4 dspo_aidb_v_timing_reg1 aidb_v_timing1; // 0xD8 dspo_aidb_h_timing_reg0 aidb_h_timing0; // 0xDC dspo_aidb_h_timing_reg1 aidb_h_timing1; // 0xE0 dspo_res_reg res010[7]; // 0xE4~0xFc dspo_bist_ctrl_reg bist_ctrl; // 0x100 dspo_bist_start_addr_reg bist_start_addr; // 0x104 dspo_bist_end_addr_reg bist_end_addr; // 0x108 dspo_bist_data_mask_reg bist_data_mask; // 0x10C } __dspo_dev; extern volatile __dspo_dev *dspo_dev[1]; // function member void dspo_module_en(u32 dev_sel, u32 module_en, u32 sepa_sync_en); void dspo_fmt_set(u32 dev_sel, u32 data_seq_sel, u32 sync_fmt, u32 data_width, u32 interlace); void dspo_chroma_spl_set(u32 dev_sel, u8 cr_type, u8 cb_type); void dspo_clamp_set(u32 dev_sel, u16 y_min, u16 y_max, u16 cb_min, u16 cb_max, u16 cr_min, u16 cr_max); void dspo_sync_pol_set(u32 dev_sel, u8 hb_pol, u8 vb_pol, u8 field_pol); void dspo_dclk_adjust(u32 dev_sel, u8 dclk_invt, u8 dly_en, u8 dly_num); u32 dspo_get_curline(u32 sel); u32 dspo_get_field(u32 sel); void dspo_irq_en(u32 sel, u32 int_type, u32 line); void dspo_irq_disable(u32 sel, u32 int_type); u32 dspo_irq_process(u32 sel); u32 dspo_clr_irq(u32 sel, u32 int_type); void dspo_timing_set(u32 sel, u32 h_active, u32 hbp, u32 hfp, u32 hsync, u32 v_active, u32 vbp, u32 v_total, u32 vfp, u32 vsync, u32 interlace, u32 itl_mode); void dspo_set_reg_base(u32 sel, unsigned long base); void dspo_yuv_data_src_sel(u32 dev_sel, u32 sel); void dspo_dma_start(u32 sel); void dspo_dma_ctrl_set(u32 sel, u32 desc_mode, u32 block_size_sel, u32 input_data_type); void dspo_rgb2yuv(u32 sel); void dspo_dma_start_check_set(u32 sel, u32 start_chk_dly, u32 start_chk_en); void dspo_dma_size_set(u32 sel, u32 x, u32 y); void dspo_dma_mode_line_buf_range_set(u32 sel, u32 x); void dspo_dma_y_addr_set(u32 sel, u32 addr); void dspo_dma_uv_addr_set(u32 sel, u32 addr); void dspo_dma_buf_line_stride_set(u32 sel, u32 y_line_stride, u32 uv_line_stride); void dspo_ceu_enable(u32 sel, u32 en); #endif