/* * Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _DRIVER_CHIP_HAL_PRCM_H_ #define _DRIVER_CHIP_HAL_PRCM_H_ #include "driver/chip/hal_def.h" #if (CONFIG_CHIP_ARCH_VER == 2) #include "driver/chip/hal_ccm.h" #endif #ifdef __cplusplus extern "C" { #endif /* prcm system module control */ typedef struct { __IO uint32_t SYS_TOP_LDO_CTRL; /* offset: 0x0000, System TOP_LDO control register */ __IO uint32_t SYS_LDO_SW_CTRL; /* offset: 0x0004, System LDO and switch control register */ __IO uint32_t SYS_LFCLK_CTRL; /* offset: 0x0008, System LFCLK control register */ __IO uint32_t SYS_HOSC_CTRL; /* offset: 0x000C, System HOSC type register */ __IO uint32_t SYS_RCOSC_CALIB_CTRL; /* offset: 0x0010, System RCOSC calibration control register */ uint32_t RESERVED0[3]; __IO uint32_t SYS_PLL_CTRL; /* offset: 0x0020, System PLL control register */ __IO uint32_t SYS_CLK1_CTRL; /* offset: 0x0024, System clock 1 control register */ __IO uint32_t RESERVED28; __IO uint32_t SYS_CLK3_CTRL; /* offset: 0x002C, System clock 3 control register */ #if (CONFIG_CHIP_ARCH_VER == 2) __IO uint32_t AUD_PLL_CTRL; /* offset: 0x0030, Audio PLL control register */ #elif (CONFIG_CHIP_ARCH_VER == 3) uint32_t RESERVED30; #endif __IO uint32_t DEV_CLK_CTRL; /* offset: 0x0034, Device clock control register */ uint32_t RESERVED1[3]; #if (CONFIG_CHIP_ARCH_VER == 2) __IO uint32_t AUD_PLL_BIAS; /* offset: 0x0044, Audio PLL bias register */ uint32_t RESERVED2[3]; __IO uint32_t AUD_PLL_PAT_CTRL; /* offset: 0x0054, Audio PLL pattern control register */ #elif (CONFIG_CHIP_ARCH_VER == 3) uint32_t RESERVED54[5]; #endif __IO uint32_t DCXO_CTRL; /* offset: 0x0058, DCXO control register */ #if (CONFIG_CHIP_ARCH_VER == 2) __IO uint32_t HXTALOUT_CTRL; /* offset: 0x005C, HXTALOUT control register */ uint32_t RESERVED3[12]; #elif (CONFIG_CHIP_ARCH_VER == 3) uint32_t RESERVED5C[6]; __IO uint32_t POWERCTRL_CFG; /* offset: 0x0074, power control config register */ uint32_t RESERVED78[2]; __I uint32_t SYS1_RST_STATUS; /* offset: 0x0080, system 1 reset status register */ __I uint32_t SYS1_STATUS; /* offset: 0x0084, system 1 control register */ uint32_t RESERVED88[2]; #endif __IO uint32_t SYS3_CTRL; /* offset: 0x0090, System 3 control register */ __I uint32_t SYS3_STATUS; /* offset: 0x0094, System 3 status register */ __IO uint32_t SYS1_WAKEUP_CTRL; /* offset: 0x0098, System 1 wakeup control register */ uint32_t RESERVED9C; __IO uint32_t SYS1_SLEEP_CTRL; /* offset: 0x00A0, System 1 sleep control register */ uint32_t RESERVEDA4; __IO uint32_t DCXO_STABLE_REF_TIME; /* offset: 0x00A8, DCXO stable reference time register */ __IO uint32_t DPLL_STABLE_REF_TIME; /* offset: 0x00AC, DPLL stable reference time register */ __IO uint32_t LDO_STABLE_REF_TIME; /* offset: 0x00B0, LDO stable reference time register */ __IO uint32_t DIG_SWITCH_REF_TIME; /* offset: 0x00B4, Digital switch reference time register */ __IO uint32_t RTC_LDO_VOLT_CTRL; /* offset: 0x00B8, RTC LDO voltage control register */ __IO uint32_t BANDGAP_STABLE_REF_TIME; /* offset: 0x00BC, Band gap stable reference time register */ __IO uint32_t DCDC_STABLE_REF_TIME; /* offset: 0x00C0, DCDC stable reference time register */ #if (CONFIG_CHIP_ARCH_VER == 2) uint32_t RESERVED4[15]; #elif (CONFIG_CHIP_ARCH_VER == 3) uint32_t RESERVEDC4[3]; __IO uint32_t BLE_RTC_RST_CTRL; /* offset: 0x00D0, BLE RTC Reset control register */ __IO uint32_t BLE_RTC_CLK_CTRL; /* offset: 0x00D4, BLE RTC Clk control register */ __IO uint32_t RFAS_CTRL_REG; /* offset: 0x00D8, RFAS Reset control register */ uint32_t RESERVEDDC[9]; #endif __IO uint32_t CPUA_BOOT_FLAG; /* offset: 0x0100, CPUA boot flag register */ __IO uint32_t CPUA_BOOT_ADDR; /* offset: 0x0104, CPUA boot address register */ __IO uint32_t CPUA_BOOT_ARG; /* offset: 0x0108, CPUA boot argument register */ __IO uint32_t CPUA_PRIV_REG_0T3[4]; /* offset: 0x010C~0x0118, CPUA private register 0 to 3 */ __IO uint32_t WDG_NORESET_PERIPH; /* offset: 0x011C, watchdog no reset peripherals */ __IO uint32_t CPUA_WAKE_TIMER_CNT; /* offset: 0x0120, CPUA wakeup timer counter register */ __IO uint32_t CPUA_WAKE_TIMER_CMP; /* offset: 0x0124, CPUA wakeup timer value register */ __IO uint32_t CPUA_PRIV_TIME_L; /* offset: 0x0128, CPUA private time register */ __IO uint32_t CPUA_PRIV_TIME_H; /* offset: 0x012C, CPUA private time register */ __IO uint32_t CPUA_WAKE_IO_EN; /* offset: 0x0130, CPUA IO wakeup enable register */ #if (CONFIG_CHIP_ARCH_VER == 2) __IO uint32_t CPUA_WAKE_IO_MODE; /* offset: 0x0134, CPUA IO wakeup mode register */ #elif (CONFIG_CHIP_ARCH_VER == 3) __IO uint32_t CPUA_WAKE_IO_DEB_CLK; /* offset: 0x0134, CPUA IO wakeup debounce clk register */ #endif __IO uint32_t CPUA_WAKE_IO_STATUS; /* offset: 0x0138, CPUA IO wakeup status register */ __IO uint32_t CPUA_WAKE_IO_HOLD; /* offset: 0x013C, CPUA IO hold control register */ __IO uint32_t CPUA_WAKE_IO_GLOBAL_EN; /* offset: 0x0140, CPUA IO wakeup global enable register */ #if (CONFIG_CHIP_ARCH_VER == 2) __IO uint32_t LDO_MODE_SW_SEL; /* offset: 0x0144, LDO mode software select */ uint32_t RESERVED6[46]; #elif (CONFIG_CHIP_ARCH_VER == 3) __IO uint32_t CPUA_WAKE_IO_DEB_CYCLES0; /* offset: 0x0144, CPUA IO wakeup debounce cycles register */ __IO uint32_t CPUA_WAKE_IO_DEB_CYCLES1; /* offset: 0x0148, CPUA IO wakeup debounce cycles register */ uint32_t RESERVED14C; __IO uint32_t LDO_MODE_SW_SEL; /* offset: 0x0150, LDO mode software select */ uint32_t RESERVED154[43]; #endif __IO uint32_t DCDC_PARAM_CTRL; /* offset: 0x0200, DCDC parameter control register */ __IO uint32_t ANA_BANDGAP; /* offset: 0x0204, Analog band gap control register */ __I uint32_t CLK_LDO_PARAM; /* offset: 0x0208, Clock LDO parameter register */ __IO uint32_t DIG_LDO_PARAM; /* offset: 0x020C, Digital LDO parameter register */ __IO uint32_t DPLL_STATUS; /* offset: 0x0210, DPLL status register */ __I uint32_t BONDING_IO; /* offset: 0x0214, Bonding IO status register */ __IO uint32_t CPU_RESET_SOURCE; /* offset: 0x0218, CPU reset source register */ __IO uint32_t WLAN_HIF_OVERRIDE_CTRL; /* offset: 0x021C, WLAN HIF override control register */ __IO uint32_t SRAM_BIST_CTRL; /* offset: 0x0220, SRAM bist control register */ #if (CONFIG_CHIP_ARCH_VER == 3) __IO uint32_t WLAN_SRAM_SHARE_CTRL; /* offset: 0x0224, wlan sram share control register */ __IO uint32_t BLE_16K_SRAM_SHARE_CTRL; /* offset: 0x0228, ble 16K sram share control register */ uint32_t RESERVED7; __IO uint32_t LPUART0_WAKEUP_CTRL; /* offset: 0x0230, lpuart0 wakeup control register */ __IO uint32_t LPUART1_WAKEUP_CTRL; /* offset: 0x0234, lpuart1 wakeup control register */ __IO uint32_t GPADC_CLK_CTRL; /* offset: 0x0238, gpadc clock control register */ __IO uint32_t CLK_32K_CTRL; /* offset: 0x023C, 32k clock control register */ __IO uint32_t WAKEUP_SRC_BUS_CLK_CTRL; /* offset: 0x0240, wakeup source reset control register */ __IO uint32_t WAKEUP_SRC_RST_CTRL; /* offset: 0x0244, wakeup source reset control register */ uint32_t RESERVED244[2]; __IO uint32_t FLASH_ENCRYPT_AES_NONCE0; /* offset: 0x0250, wakeup source reset control register */ __IO uint32_t FLASH_ENCRYPT_AES_NONCE1; /* offset: 0x0254, wakeup source reset control register */ uint32_t RESERVED260[2]; __IO uint32_t BLE_RCOSC_CALIB_CTRL0; /* offset: 0x0260, ble RCOSC calibration control register0 */ __IO uint32_t BLE_RCOSC_CALIB_CTRL1; /* offset: 0x0264, ble RCOSC calibration control register1 */ __IO uint32_t BLE_CLK32K_SWITCH0; /* offset: 0x0268, ble clk 32k switch register0 */ __I uint32_t BLE_CLK32K_SWITCH1; /* offset: 0x026C, ble clk 32k switch register1 */ #endif } PRCM_T; #define PRCM ((PRCM_T *)PRCM_BASE) /* address: 0x40040000 */ /* * bit field definition of PRCM->SYS_TOP_LDO_CTRL */ #if (CONFIG_CHIP_ARCH_VER == 3) #define PRCM_TOPLDO_VOLT_SHIFT 25 /* R/W */ #define PRCM_TOPLDO_VOLT_MASK (0xFU << PRCM_TOPLDO_VOLT_SHIFT) #define PRCM_TOPLDO_VOLT_VMASK (0xFU) typedef enum { PRCM_TOPLDO_VOLT_0V9 = (0x0U << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_1V0 = (0x1U << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_1V1 = (0x2U << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_1V2 = (0x3U << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_1V3 = (0x4U << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_1V4 = (0x5U << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_1V5 = (0x6U << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_1V6 = (0x7U << PRCM_TOPLDO_VOLT_SHIFT), /* DEFAULT */ PRCM_TOPLDO_VOLT_1V7 = (0x8U << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_1V8 = (0x9U << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_1V9 = (0xAU << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_2V0 = (0xBU << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_2V1 = (0xCU << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_2V2 = (0xDU << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_2V3 = (0xEU << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_2V4 = (0xFU << PRCM_TOPLDO_VOLT_SHIFT), } PRCM_TOPLDOVolt; #endif #define PRCM_TOPLDO_FORCE_ACTIVE_BIT HAL_BIT(24) #if (CONFIG_CHIP_ARCH_VER == 2) #define PRCM_TOPLDO_VOLT_SHIFT 16 /* R/W */ #define PRCM_TOPLDO_VOLT_MASK (0xFU << PRCM_TOPLDO_VOLT_SHIFT) #define PRCM_TOPLDO_VOLT_VMASK (0xFU) typedef enum { PRCM_TOPLDO_VOLT_1V8_DEFAULT = (0x0U << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_1V4 = (0x1U << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_1V7 = (0x2U << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_1V8 = (0x3U << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_1V9 = (0x4U << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_2V0 = (0x5U << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_2V1 = (0x6U << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_2V4 = (0x7U << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_2V5 = (0x8U << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_2V6 = (0x9U << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_2V9 = (0xAU << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_3V0 = (0xBU << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_3V1 = (0xCU << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_3V3 = (0xDU << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_3V4 = (0xEU << PRCM_TOPLDO_VOLT_SHIFT), PRCM_TOPLDO_VOLT_3V6 = (0xFU << PRCM_TOPLDO_VOLT_SHIFT) } PRCM_TOPLDOVolt; #endif #if (CONFIG_CHIP_ARCH_VER == 3) #define PRCM_SMPS_VOLT_SHIFT 12 /* R/W */ #define PRCM_SMPS_VOLT_VMASK (0x0FU) #define PRCM_SMPS_VOLT_MASK (PRCM_SMPS_VOLT_VMASK << PRCM_SMPS_VOLT_SHIFT) typedef enum { PRCM_SMPS_VOLT_1V0 = (0x0U << PRCM_SMPS_VOLT_SHIFT), PRCM_SMPS_VOLT_1V1 = (0x1U << PRCM_SMPS_VOLT_SHIFT), PRCM_SMPS_VOLT_1V2 = (0x2U << PRCM_SMPS_VOLT_SHIFT), PRCM_SMPS_VOLT_1V3 = (0x3U << PRCM_SMPS_VOLT_SHIFT), PRCM_SMPS_VOLT_1V4 = (0x4U << PRCM_SMPS_VOLT_SHIFT), PRCM_SMPS_VOLT_1V5 = (0x5U << PRCM_SMPS_VOLT_SHIFT), PRCM_SMPS_VOLT_1V6 = (0x6U << PRCM_SMPS_VOLT_SHIFT), PRCM_SMPS_VOLT_1V7 = (0x7U << PRCM_SMPS_VOLT_SHIFT), PRCM_SMPS_VOLT_1V8 = (0x8U << PRCM_SMPS_VOLT_SHIFT), /* DEFAULT */ PRCM_SMPS_VOLT_1V9 = (0x9U << PRCM_SMPS_VOLT_SHIFT), PRCM_SMPS_VOLT_2V0 = (0xAU << PRCM_SMPS_VOLT_SHIFT), PRCM_SMPS_VOLT_2V1 = (0xBU << PRCM_SMPS_VOLT_SHIFT), PRCM_SMPS_VOLT_2V2 = (0xCU << PRCM_SMPS_VOLT_SHIFT), PRCM_SMPS_VOLT_2V3 = (0xDU << PRCM_SMPS_VOLT_SHIFT), PRCM_SMPS_VOLT_2V4 = (0xEU << PRCM_SMPS_VOLT_SHIFT), PRCM_SMPS_VOLT_2V5 = (0xFU << PRCM_SMPS_VOLT_SHIFT), } PRCM_SMPSVolt; #define PRCM_DIGLDO_OFF_SMPS_ON_BIT HAL_BIT(9) #define PRCM_SYS_STANDBY_SMPS_OFF_BIT HAL_BIT(8) #define PRCM_SMPS_PWM_SEL_BIT HAL_BIT(7) #define PRCM_SMPS_PWM_SEL_SHIFT 4 /* R/W */ #define PRCM_SMPS_PWM_SEL_MASK (0x7U << PRCM_SMPS_PWM_SEL_SHIFT) #define PRCM_SMPS_PWM_SEL_VMASK (0x7U) typedef enum { PRCM_SMPS_PWM_SEL_CLK_RFIPDPLL = (0x0U << PRCM_SMPS_PWM_SEL_SHIFT), PRCM_SMPS_PWM_SEL_CLK_RFIPDCXO = (0x1U << PRCM_SMPS_PWM_SEL_SHIFT), PRCM_SMPS_PWM_SEL_CLK_WLANPHYEN = (0x2U << PRCM_SMPS_PWM_SEL_SHIFT), PRCM_SMPS_PWM_SEL_CLK_APPCPUEN = (0x3U << PRCM_SMPS_PWM_SEL_SHIFT), PRCM_SMPS_PWM_SEL_CLK_WLANCPUEN = (0x4U << PRCM_SMPS_PWM_SEL_SHIFT), PRCM_SMPS_PWM_SEL_CLK_BLERFEN = (0x5U << PRCM_SMPS_PWM_SEL_SHIFT), } PRCM_SMPSPwmSel; #define PRCM_OVR_SMPS_DETECT_BIT HAL_BIT(2) #define PRCM_SMPS_DETECT_VALUE_BIT HAL_BIT(1) #define PRCM_SMPS_DETECT_BIT HAL_BIT(0) #endif /* * bit field definition of PRCM->SYS_LDO_SW_CTRL */ #if (CONFIG_CHIP_ARCH_VER == 2) #define PRCM_LDO1_RET_VOLT_SHIFT 24 #define PRCM_LDO1_RET_VOLT_MASK (0xFU << PRCM_LDO1_RET_VOLT_SHIFT) typedef enum { PRCM_LDO1_RET_VOLT_1125MV = (0x0U << PRCM_LDO1_RET_VOLT_SHIFT), PRCM_LDO1_RET_VOLT_1025MV = (0x1U << PRCM_LDO1_RET_VOLT_SHIFT), PRCM_LDO1_RET_VOLT_925MV = (0x2U << PRCM_LDO1_RET_VOLT_SHIFT), PRCM_LDO1_RET_VOLT_825MV = (0x3U << PRCM_LDO1_RET_VOLT_SHIFT), PRCM_LDO1_RET_VOLT_725MV = (0x4U << PRCM_LDO1_RET_VOLT_SHIFT), PRCM_LDO1_RET_VOLT_625MV = (0x5U << PRCM_LDO1_RET_VOLT_SHIFT), PRCM_LDO1_RET_VOLT_1175MV = (0x8U << PRCM_LDO1_RET_VOLT_SHIFT), PRCM_LDO1_RET_VOLT_1225MV = (0x9U << PRCM_LDO1_RET_VOLT_SHIFT), PRCM_LDO1_RET_VOLT_1275MV = (0xAU << PRCM_LDO1_RET_VOLT_SHIFT), PRCM_LDO1_RET_VOLT_1325MV = (0xBU << PRCM_LDO1_RET_VOLT_SHIFT), PRCM_LDO1_RET_VOLT_1375MV = (0xCU << PRCM_LDO1_RET_VOLT_SHIFT), } PRCM_LDO1RetVolt; #elif (CONFIG_CHIP_ARCH_VER == 3) #define PRCM_DIGLDO_RET_VOLT_SHIFT 24 #define PRCM_DIGLDO_RET_VOLT_MASK (0xFU << PRCM_DIGLDO_RET_VOLT_SHIFT) typedef enum { PRCM_DIGLDO_RET_VOLT_1125MV = (0x0U << PRCM_DIGLDO_RET_VOLT_SHIFT), PRCM_DIGLDO_RET_VOLT_1025MV = (0x1U << PRCM_DIGLDO_RET_VOLT_SHIFT), PRCM_DIGLDO_RET_VOLT_925MV = (0x2U << PRCM_DIGLDO_RET_VOLT_SHIFT), PRCM_DIGLDO_RET_VOLT_825MV = (0x3U << PRCM_DIGLDO_RET_VOLT_SHIFT), PRCM_DIGLDO_RET_VOLT_725MV = (0x4U << PRCM_DIGLDO_RET_VOLT_SHIFT), PRCM_DIGLDO_RET_VOLT_625MV = (0x5U << PRCM_DIGLDO_RET_VOLT_SHIFT), PRCM_DIGLDO_RET_VOLT_1175MV = (0x8U << PRCM_DIGLDO_RET_VOLT_SHIFT), PRCM_DIGLDO_RET_VOLT_1225MV = (0x9U << PRCM_DIGLDO_RET_VOLT_SHIFT), PRCM_DIGLDO_RET_VOLT_1275MV = (0xAU << PRCM_DIGLDO_RET_VOLT_SHIFT), PRCM_DIGLDO_RET_VOLT_1325MV = (0xBU << PRCM_DIGLDO_RET_VOLT_SHIFT), PRCM_DIGLDO_RET_VOLT_1375MV = (0xCU << PRCM_DIGLDO_RET_VOLT_SHIFT), } PRCM_DIGLDORetVolt; #define PRCM_EXT_LDO_BYPASS_BIT HAL_BIT(23) #define PRCM_EXT_LDO_SW_TRIM_SHIFT 21 #define PRCM_EXT_LDO_SW_TRIM_MASK (0x3U << PRCM_EXT_LDO_SW_TRIM_SHIFT) #define PRCM_EXT_LDO_SW_MODE_BIT HAL_BIT(20) #endif #if (CONFIG_CHIP_ARCH_VER == 2) #define PRCM_EXT_LDO_VOLT_BIT HAL_BIT(18) #define PRCM_EXT_LDO_VOLT_SHIFT 18 #define PRCM_EXT_LDO_VOLT_MASK (0x1U << PRCM_EXT_LDO_VOLT_SHIFT) typedef enum { PRCM_EXT_LDO_3V3 = (0x0U << PRCM_EXT_LDO_VOLT_SHIFT), PRCM_EXT_LDO_3V1 = (0x1U << PRCM_EXT_LDO_VOLT_SHIFT), } PRCM_EXTLDOVolt; #elif (CONFIG_CHIP_ARCH_VER == 3) #define PRCM_EXT_LDO_VOLT_SHIFT 18 #define PRCM_EXT_LDO_VOLT_MASK (0x3U << PRCM_EXT_LDO_VOLT_SHIFT) typedef enum { PRCM_EXT_LDO_3V3 = (0x0U << PRCM_EXT_LDO_VOLT_SHIFT), PRCM_EXT_LDO_3V1 = (0x1U << PRCM_EXT_LDO_VOLT_SHIFT), PRCM_EXT_LDO_2V8 = (0x2U << PRCM_EXT_LDO_VOLT_SHIFT), PRCM_EXT_LDO_2V5 = (0x3U << PRCM_EXT_LDO_VOLT_SHIFT), } PRCM_EXTLDOVolt; #endif #define PRCM_EXT_LDO_MODE_SHIFT 16 /* R/W */ #define PRCM_EXT_LDO_MODE_MASK (0x3U << PRCM_EXT_LDO_MODE_SHIFT) typedef enum { PRCM_EXTLDO_ALWAYS_OFF = (0x0U << PRCM_EXT_LDO_MODE_SHIFT), PRCM_EXTLDO_SAME_TOPLDO = (0x1U << PRCM_EXT_LDO_MODE_SHIFT), PRCM_EXTLDO_ALWAYS_ON = (0x2U << PRCM_EXT_LDO_MODE_SHIFT), } PRCM_ExtLDOMode; #if (CONFIG_CHIP_ARCH_VER == 2) #define PRCM_SR_SW3_BIT HAL_BIT(15) #endif #define PRCM_SW5_STATUS_BIT HAL_BIT(14) #if (CONFIG_CHIP_ARCH_VER == 2) #define PRCM_SW4_STATUS_BIT HAL_BIT(13) #define PRCM_SW3_STATUS_BIT HAL_BIT(12) #define PRCM_SW2_STATUS_BIT HAL_BIT(11) #endif #define PRCM_SW1_STATUS_BIT HAL_BIT(8) /* R */ #if (CONFIG_CHIP_ARCH_VER == 2) #define PRCM_LDO1_VOLT_SHIFT 4 /* R/W */ #define PRCM_LDO1_VOLT_MASK (0xFU << PRCM_LDO1_VOLT_SHIFT) typedef enum { PRCM_LDO1_VOLT_1125MV = (0x0U << PRCM_LDO1_VOLT_SHIFT), PRCM_LDO1_VOLT_1025MV = (0x1U << PRCM_LDO1_VOLT_SHIFT), PRCM_LDO1_VOLT_925MV = (0x2U << PRCM_LDO1_VOLT_SHIFT), PRCM_LDO1_VOLT_825MV = (0x3U << PRCM_LDO1_VOLT_SHIFT), PRCM_LDO1_VOLT_725MV = (0x4U << PRCM_LDO1_VOLT_SHIFT), PRCM_LDO1_VOLT_625MV = (0x5U << PRCM_LDO1_VOLT_SHIFT), PRCM_LDO1_VOLT_1175MV = (0x8U << PRCM_LDO1_VOLT_SHIFT), PRCM_LDO1_VOLT_1225MV = (0x9U << PRCM_LDO1_VOLT_SHIFT), PRCM_LDO1_VOLT_1275MV = (0xAU << PRCM_LDO1_VOLT_SHIFT), PRCM_LDO1_VOLT_1325MV = (0xBU << PRCM_LDO1_VOLT_SHIFT), PRCM_LDO1_VOLT_1375MV = (0xCU << PRCM_LDO1_VOLT_SHIFT), } PRCM_LDO1Volt; #define PRCM_LDO1_STATUS_BIT HAL_BIT(2) /* R */ #elif (CONFIG_CHIP_ARCH_VER == 3) #define PRCM_DIGLDO_VOLT_SHIFT 4 /* R/W */ #define PRCM_DIGLDO_VOLT_MASK (0xFU << PRCM_DIGLDO_VOLT_SHIFT) typedef enum { PRCM_DIGLDO_VOLT_1125MV = (0x0U << PRCM_DIGLDO_VOLT_SHIFT), PRCM_DIGLDO_VOLT_1025MV = (0x1U << PRCM_DIGLDO_VOLT_SHIFT), PRCM_DIGLDO_VOLT_925MV = (0x2U << PRCM_DIGLDO_VOLT_SHIFT), PRCM_DIGLDO_VOLT_825MV = (0x3U << PRCM_DIGLDO_VOLT_SHIFT), PRCM_DIGLDO_VOLT_725MV = (0x4U << PRCM_DIGLDO_VOLT_SHIFT), PRCM_DIGLDO_VOLT_625MV = (0x5U << PRCM_DIGLDO_VOLT_SHIFT), PRCM_DIGLDO_VOLT_1175MV = (0x8U << PRCM_DIGLDO_VOLT_SHIFT), PRCM_DIGLDO_VOLT_1225MV = (0x9U << PRCM_DIGLDO_VOLT_SHIFT), PRCM_DIGLDO_VOLT_1275MV = (0xAU << PRCM_DIGLDO_VOLT_SHIFT), PRCM_DIGLDO_VOLT_1325MV = (0xBU << PRCM_DIGLDO_VOLT_SHIFT), PRCM_DIGLDO_VOLT_1375MV = (0xCU << PRCM_DIGLDO_VOLT_SHIFT), } PRCM_DIGLDOVolt; #endif #if (CONFIG_CHIP_ARCH_VER == 2) #define PRCM_DIGLDO_STATUS_BIT HAL_BIT(2) /* R */ #define PRCM_PLL_LDO_EN_BIT HAL_BIT(1) /* R/W */ #define PRCM_LDO1_EN_BIT HAL_BIT(0) /* R */ #elif (CONFIG_CHIP_ARCH_VER == 3) #define PRCM_PLL_LDO_EN_BIT HAL_BIT(1) /* R/W */ #define PRCM_DIGLDO_STATUS_BIT HAL_BIT(0) /* R */ #endif /* * bit field definition of PRCM->SYS_LFCLK_CTRL */ #define PRCM_LFCLK_EXT32K_EN_BIT HAL_BIT(31) /* R/W */ #define PRCM_LFCLK_INTER32K_EN_BIT HAL_BIT(30) /* R/W */ #define PRCM_LFCLK_BASE_SRC_SHIFT 24 /* R/W */ #define PRCM_LFCLK_BASE_SRC_MASK (0x1U << PRCM_LFCLK_BASE_SRC_SHIFT) typedef enum { PRCM_LFCLK_BASE_SRC_INTER32K = (0x0U << PRCM_LFCLK_BASE_SRC_SHIFT), PRCM_LFCLK_BASE_SRC_EXT32K = (0x1U << PRCM_LFCLK_BASE_SRC_SHIFT) } PRCM_LFCLKBaseSrc; #define PRCM_PAD_CLK_OUT_FACTOR_M_SHIFT 8 #define PRCM_PAD_CLK_OUT_FACTOR_M_MASK (0x0FFFFU << PRCM_PAD_CLK_OUT_FACTOR_M_SHIFT) #define PRCM_PAD_CLK_OUT_FACTOR_M_VAL(v) (((v) & 0x0FFFFU) << PRCM_PAD_CLK_OUT_FACTOR_M_SHIFT) #define PRCM_PAD_CLK_OUT_SOURCE_SHIFT 1 #define PRCM_PAD_CLK_OUT_SOURCE_MASK (0x3U << PRCM_PAD_CLK_OUT_SOURCE_SHIFT) typedef enum { PRCM_PAD_CLK_OUT_LFCLK_RC = (0x0U << PRCM_PAD_CLK_OUT_SOURCE_SHIFT), PRCM_PAD_CLK_OUT_LFCLK_CRYSTAL = (0x1U << PRCM_PAD_CLK_OUT_SOURCE_SHIFT), #if (CONFIG_CHIP_ARCH_VER == 2) PRCM_PAD_CLK_OUT_HFCLK_CRYSTAL = (0x2U << PRCM_PAD_CLK_OUT_SOURCE_SHIFT), #elif (CONFIG_CHIP_ARCH_VER == 3) PRCM_PAD_CLK_OUT_LFCLK_RCO_CALIB = (0x2U << PRCM_PAD_CLK_OUT_SOURCE_SHIFT), PRCM_PAD_CLK_OUT_HFCLK_CRYSTAL = (0x3U << PRCM_PAD_CLK_OUT_SOURCE_SHIFT), #endif } PRCM_PadClkOutSource; #define PRCM_PAD_CLK_OUT_EN_BIT HAL_BIT(0) typedef enum { PRCM_LFCLK_MODULE_SYS, /* power ctrl, cpu, bus, lpuart0/1, gpadc, keyboard */ #if (CONFIG_CHIP_ARCH_VER == 3) PRCM_LFCLK_MODULE_WKTIMER, /* wakeup timer */ PRCM_LFCLK_MODULE_WLAN, /* wlan */ PRCM_LFCLK_MODULE_RTC, /* rtc, free running timer */ PRCM_LFCLK_MODULE_BLE, /* ble */ #endif PRCM_LFCLK_MODULE_MAX, } PRCM_LFClkModule; typedef enum { PRCM_LFCLK_SRC_LOSC, /* external, 32.768K */ PRCM_LFCLK_SRC_RCOSC, /* rcosc/32, 20~50K */ PRCM_LFCLK_SRC_RCCAL, /* rcosc calibration, about 32K */ PRCM_LFCLK_SRC_DIV32K, /* from 32M or HOSC division, 32K */ PRCM_LFCLK_SRC_MAX, } PRCM_LFClkSrc; /* * bit field definition of PRCM->SYS_HOSC_CTRL */ #define PRCM_HOSC_TYPE_SHIFT 0 /* R/W */ #define PRCM_HOSC_TYPE_VMASK 0x3U #define PRCM_HOSC_TYPE_MASK (PRCM_HOSC_TYPE_VMASK << PRCM_HOSC_TYPE_SHIFT) typedef enum { PRCM_HOSC_TYPE_26M = (0U << PRCM_HOSC_TYPE_SHIFT), PRCM_HOSC_TYPE_40M = (1U << PRCM_HOSC_TYPE_SHIFT), PRCM_HOSC_TYPE_24M = (2U << PRCM_HOSC_TYPE_SHIFT), #if (CONFIG_CHIP_ARCH_VER == 2) PRCM_HOSC_TYPE_52M = (3U << PRCM_HOSC_TYPE_SHIFT) #elif (CONFIG_CHIP_ARCH_VER == 3) PRCM_HOSC_TYPE_32M = (3U << PRCM_HOSC_TYPE_SHIFT) #endif } PRCM_HOSCType; /* * bit field definition of PRCM->SYS_RCOSC_CALIB_CTRL */ #define PRCM_RCOSC_CALIB_FREQ_SHIFT 8 /* R */ #define PRCM_RCOSC_CALIB_FREQ_VMASK 0xFFFFFU #define PRCM_RCOSC_CALIB_EN_BIT HAL_BIT(0) /* R/W */ /* * bit field definition of PRCM->SYS_PLL_CTRL */ #define PRCM_SYS_PLL_EN_BIT HAL_BIT(31) /* R/W */ #define PRCM_SYS_PLL_PARAM_SHIFT 0 #define PRCM_SYS_PLL_PARAM_MASK 0x7FFFFFFFU /* Fout = Fhosc * N.f/M, must be in range of 960~1920MHz * bit29~30: DPLL_DITHER_DISABLE * bit13~28: DPLL_FRAC, Vfrac = f*(2^16) * bit12 : DPLL_FRAC_CTRL * bit4~11 : DPLL_NDIV * bit0~3 : FACTOR_M */ typedef enum { #if (CONFIG_CHIP_ARCH_VER == 2) PRCM_SYS_PLL_PARAM_HOSC24M = 0x60000501U, PRCM_SYS_PLL_PARAM_HOSC26M = 0x1B13B491U, PRCM_SYS_PLL_PARAM_HOSC40M = 0x60000301U, PRCM_SYS_PLL_PARAM_HOSC52M = 0x1D89D241U #elif (CONFIG_CHIP_ARCH_VER == 3) PRCM_SYS_PLL_PARAM_HOSC24M = 0x60000281U, PRCM_SYS_PLL_PARAM_HOSC26M = 0x1D89D241U, PRCM_SYS_PLL_PARAM_HOSC40M = 0x60000181U, PRCM_SYS_PLL_PARAM_HOSC32M = 0x600001E1U #endif } PRCM_SysPLLParam; /* * bit field definition of * - PRCM->SYS_CLK1_CTRL (R/W) * - PRCM->SYS_CLK3_CTRL (R/W) */ #define PRCM_SYS_CLK_EN_BIT HAL_BIT(31) /* R/W, R, R */ /* NB: the following bits are for SYS_CLK1_CTRL only */ #define PRCM_CPU_CLK_SRC_SHIFT 16 /* R/W, R */ #define PRCM_CPU_CLK_SRC_MASK (0x3 << PRCM_CPU_CLK_SRC_SHIFT) typedef enum { PRCM_CPU_CLK_SRC_HFCLK = (0x0U << PRCM_CPU_CLK_SRC_SHIFT), PRCM_CPU_CLK_SRC_LFCLK = (0x1U << PRCM_CPU_CLK_SRC_SHIFT), PRCM_CPU_CLK_SRC_SYSCLK = (0x2U << PRCM_CPU_CLK_SRC_SHIFT) } PRCM_CPUClkSrc; /* * PRCM_SYS_CLOCK = SYS_PLL_CLOCK / M / N * - SYS_PLL_CLOCK: 1920 MHz on XR872/XR808, 960 MHz on XR806 * - M: [5, 9] * - N: [1, 16] */ #define PRCM_SYS_CLK_FACTORM_SHIFT 8 /* R/W */ #define PRCM_SYS_CLK_FACTORM_VMASK 0x7U #define PRCM_SYS_CLK_FACTORM_MASK (PRCM_SYS_CLK_FACTORM_VMASK << PRCM_SYS_CLK_FACTORM_SHIFT) #if (CONFIG_CHIP_ARCH_VER == 2) #define PRCM_SYS_CLK_FACTORM_START 5 #elif (CONFIG_CHIP_ARCH_VER == 3) #define PRCM_SYS_CLK_FACTORM_START 4 #endif typedef enum { #if (CONFIG_CHIP_ARCH_VER == 2) PRCM_SYS_CLK_FACTORM_5 = (0U << PRCM_SYS_CLK_FACTORM_SHIFT), PRCM_SYS_CLK_FACTORM_6 = (1U << PRCM_SYS_CLK_FACTORM_SHIFT), PRCM_SYS_CLK_FACTORM_7 = (2U << PRCM_SYS_CLK_FACTORM_SHIFT), PRCM_SYS_CLK_FACTORM_8 = (3U << PRCM_SYS_CLK_FACTORM_SHIFT), PRCM_SYS_CLK_FACTORM_9 = (4U << PRCM_SYS_CLK_FACTORM_SHIFT), #elif (CONFIG_CHIP_ARCH_VER == 3) PRCM_SYS_CLK_FACTORM_4 = (0U << PRCM_SYS_CLK_FACTORM_SHIFT), PRCM_SYS_CLK_FACTORM_5 = (1U << PRCM_SYS_CLK_FACTORM_SHIFT), PRCM_SYS_CLK_FACTORM_6 = (2U << PRCM_SYS_CLK_FACTORM_SHIFT), PRCM_SYS_CLK_FACTORM_7 = (3U << PRCM_SYS_CLK_FACTORM_SHIFT), PRCM_SYS_CLK_FACTORM_9 = (4U << PRCM_SYS_CLK_FACTORM_SHIFT), #endif } PRCM_SysClkFactorM; #define PRCM_SYS_CLK_FACTORN_SHIFT 0 /* R/W */ #define PRCM_SYS_CLK_FACTORN_VMASK 0xFU #define PRCM_SYS_CLK_FACTORN_MASK (PRCM_SYS_CLK_FACTORN_VMASK << PRCM_SYS_CLK_FACTORN_SHIFT) typedef enum { PRCM_SYS_CLK_FACTORN_1 = (0U << PRCM_SYS_CLK_FACTORN_SHIFT), PRCM_SYS_CLK_FACTORN_2 = (1U << PRCM_SYS_CLK_FACTORN_SHIFT), PRCM_SYS_CLK_FACTORN_3 = (2U << PRCM_SYS_CLK_FACTORN_SHIFT), PRCM_SYS_CLK_FACTORN_4 = (3U << PRCM_SYS_CLK_FACTORN_SHIFT), PRCM_SYS_CLK_FACTORN_5 = (4U << PRCM_SYS_CLK_FACTORN_SHIFT), PRCM_SYS_CLK_FACTORN_6 = (5U << PRCM_SYS_CLK_FACTORN_SHIFT), PRCM_SYS_CLK_FACTORN_7 = (6U << PRCM_SYS_CLK_FACTORN_SHIFT), PRCM_SYS_CLK_FACTORN_8 = (7U << PRCM_SYS_CLK_FACTORN_SHIFT), PRCM_SYS_CLK_FACTORN_9 = (8U << PRCM_SYS_CLK_FACTORN_SHIFT), PRCM_SYS_CLK_FACTORN_10 = (9U << PRCM_SYS_CLK_FACTORN_SHIFT), PRCM_SYS_CLK_FACTORN_11 = (10U << PRCM_SYS_CLK_FACTORN_SHIFT), PRCM_SYS_CLK_FACTORN_12 = (11U << PRCM_SYS_CLK_FACTORN_SHIFT), PRCM_SYS_CLK_FACTORN_13 = (12U << PRCM_SYS_CLK_FACTORN_SHIFT), PRCM_SYS_CLK_FACTORN_14 = (13U << PRCM_SYS_CLK_FACTORN_SHIFT), PRCM_SYS_CLK_FACTORN_15 = (14U << PRCM_SYS_CLK_FACTORN_SHIFT), PRCM_SYS_CLK_FACTORN_16 = (15U << PRCM_SYS_CLK_FACTORN_SHIFT), } PRCM_SysClkFactorN; #define PRCM_SYS_CLK_FACTOR(m, n) ((m) | (n)) #define PRCM_SYS_CLK_FACTOR_MASK (PRCM_SYS_CLK_FACTORM_MASK | PRCM_SYS_CLK_FACTORN_MASK) typedef enum { #if (CONFIG_CHIP_ARCH_VER == 2) PRCM_SYS_CLK_FACTOR_384M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_5, PRCM_SYS_CLK_FACTORN_1), PRCM_SYS_CLK_FACTOR_320M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_6, PRCM_SYS_CLK_FACTORN_1), PRCM_SYS_CLK_FACTOR_274M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_7, PRCM_SYS_CLK_FACTORN_1), PRCM_SYS_CLK_FACTOR_240M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_8, PRCM_SYS_CLK_FACTORN_1), PRCM_SYS_CLK_FACTOR_213M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_9, PRCM_SYS_CLK_FACTORN_1), PRCM_SYS_CLK_FACTOR_192M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_5, PRCM_SYS_CLK_FACTORN_2), PRCM_SYS_CLK_FACTOR_160M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_6, PRCM_SYS_CLK_FACTORN_2), PRCM_SYS_CLK_FACTOR_137M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_7, PRCM_SYS_CLK_FACTORN_2), PRCM_SYS_CLK_FACTOR_128M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_5, PRCM_SYS_CLK_FACTORN_3), PRCM_SYS_CLK_FACTOR_120M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_8, PRCM_SYS_CLK_FACTORN_2), PRCM_SYS_CLK_FACTOR_107M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_9, PRCM_SYS_CLK_FACTORN_2), PRCM_SYS_CLK_FACTOR_96M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_5, PRCM_SYS_CLK_FACTORN_4), PRCM_SYS_CLK_FACTOR_80M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_6, PRCM_SYS_CLK_FACTORN_4), /* default */ PRCM_SYS_CLK_FACTOR_64M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_6, PRCM_SYS_CLK_FACTORN_5), PRCM_SYS_CLK_FACTOR_60M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_8, PRCM_SYS_CLK_FACTORN_4), PRCM_SYS_CLK_FACTOR_48M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_8, PRCM_SYS_CLK_FACTORN_5), PRCM_SYS_CLK_FACTOR_40M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_8, PRCM_SYS_CLK_FACTORN_6), #elif (CONFIG_CHIP_ARCH_VER == 3) PRCM_SYS_CLK_FACTOR_240M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_4, PRCM_SYS_CLK_FACTORN_1), PRCM_SYS_CLK_FACTOR_192M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_5, PRCM_SYS_CLK_FACTORN_1), PRCM_SYS_CLK_FACTOR_160M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_6, PRCM_SYS_CLK_FACTORN_1), /* default */ PRCM_SYS_CLK_FACTOR_120M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_4, PRCM_SYS_CLK_FACTORN_2), PRCM_SYS_CLK_FACTOR_96M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_5, PRCM_SYS_CLK_FACTORN_2), PRCM_SYS_CLK_FACTOR_80M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_6, PRCM_SYS_CLK_FACTORN_2), PRCM_SYS_CLK_FACTOR_64M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_5, PRCM_SYS_CLK_FACTORN_3), PRCM_SYS_CLK_FACTOR_60M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_4, PRCM_SYS_CLK_FACTORN_4), PRCM_SYS_CLK_FACTOR_48M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_4, PRCM_SYS_CLK_FACTORN_5), PRCM_SYS_CLK_FACTOR_40M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_4, PRCM_SYS_CLK_FACTORN_6), PRCM_SYS_CLK_FACTOR_24M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_4, PRCM_SYS_CLK_FACTORN_10), PRCM_SYS_CLK_FACTOR_10M = PRCM_SYS_CLK_FACTOR(PRCM_SYS_CLK_FACTORM_6, PRCM_SYS_CLK_FACTORN_16), #endif } PRCM_SysClkFactor; /* * bit field definition of PRCM->DEV_CLK_CTRL, 0x34 * PRCM_DEV_CLOCK = SYS_PLL_CLOCK / M / N * - SYS_PLL_CLOCK: 1920 MHz for XR872/XR808, 960MHz for XR806 * - M: [5, 9] * - N: [1, 16] */ #if (CONFIG_CHIP_ARCH_VER == 3) #define PRCM_CKADC_AUD_EN_BIT HAL_BIT(31) /* R/W */ #define PRCM_CKCLD_AUD_EN_BIT HAL_BIT(23) /* R/W */ #define PRCM_CKCLD_FACTOR_N_SHIFT 16 #define PRCM_CKCLD_FACTOR_V_MASK (0x1FU) #define PRCM_CKCLD_FACTOR_N_MASK (PRCM_CKCLD_FACTOR_V_MASK << PRCM_CKCLD_FACTOR_N_SHIFT) #define PRCM_CKCLD_FACTOR_N(n) (((n) & PRCM_CKCLD_FACTOR_V_MASK) << PRCM_CKCLD_FACTOR_N_SHIFT) #endif #define PRCM_DEV1_FACTOR_M_SHIFT 8 #define PRCM_DEV1_FACTOR_M_MASK (PRCM_DEV_CLK_FACTORM_VMASK << PRCM_DEV1_FACTOR_M_SHIFT) #define PRCM_DEV_CLK_FACTORM_SHIFT PRCM_DEV1_FACTOR_M_SHIFT /* R/W */ #define PRCM_DEV_CLK_FACTORM_VMASK 0x7U #define PRCM_DEV_CLK_FACTORM_MASK (PRCM_DEV1_FACTOR_M_MASK) #if (CONFIG_CHIP_ARCH_VER == 2) #define PRCM_DEV_CLK_FACTORM_START 5 #elif (CONFIG_CHIP_ARCH_VER == 3) #define PRCM_DEV_CLK_FACTORM_START 4 #endif typedef enum { #if (CONFIG_CHIP_ARCH_VER == 2) PRCM_DEV_CLK_FACTORM_5 = (0U << PRCM_DEV_CLK_FACTORM_SHIFT), PRCM_DEV_CLK_FACTORM_6 = (1U << PRCM_DEV_CLK_FACTORM_SHIFT), PRCM_DEV_CLK_FACTORM_7 = (2U << PRCM_DEV_CLK_FACTORM_SHIFT), PRCM_DEV_CLK_FACTORM_8 = (3U << PRCM_DEV_CLK_FACTORM_SHIFT), #elif (CONFIG_CHIP_ARCH_VER == 3) PRCM_DEV_CLK_FACTORM_4 = (0U << PRCM_DEV_CLK_FACTORM_SHIFT), PRCM_DEV_CLK_FACTORM_5 = (1U << PRCM_DEV_CLK_FACTORM_SHIFT), PRCM_DEV_CLK_FACTORM_6 = (2U << PRCM_DEV_CLK_FACTORM_SHIFT), PRCM_DEV_CLK_FACTORM_7 = (3U << PRCM_DEV_CLK_FACTORM_SHIFT), #endif PRCM_DEV_CLK_FACTORM_9 = (4U << PRCM_DEV_CLK_FACTORM_SHIFT), } PRCM_DevClkFactorM; #define PRCM_DEV1_FACTOR_N_SHIFT 0 #define PRCM_DEV1_FACTOR_N_MASK (PRCM_DEV_CLK_FACTORN_VMASK << PRCM_DEV1_FACTOR_N_SHIFT) #define PRCM_DEV_CLK_FACTORN_SHIFT PRCM_DEV1_FACTOR_N_SHIFT /* R/W */ #define PRCM_DEV_CLK_FACTORN_VMASK 0xFU #define PRCM_DEV_CLK_FACTORN_MASK (PRCM_DEV1_FACTOR_N_MASK) typedef enum { PRCM_DEV_CLK_FACTORN_1 = (0U << PRCM_DEV_CLK_FACTORN_SHIFT), PRCM_DEV_CLK_FACTORN_2 = (1U << PRCM_DEV_CLK_FACTORN_SHIFT), PRCM_DEV_CLK_FACTORN_3 = (2U << PRCM_DEV_CLK_FACTORN_SHIFT), PRCM_DEV_CLK_FACTORN_4 = (3U << PRCM_DEV_CLK_FACTORN_SHIFT), PRCM_DEV_CLK_FACTORN_5 = (4U << PRCM_DEV_CLK_FACTORN_SHIFT), PRCM_DEV_CLK_FACTORN_6 = (5U << PRCM_DEV_CLK_FACTORN_SHIFT), PRCM_DEV_CLK_FACTORN_7 = (6U << PRCM_DEV_CLK_FACTORN_SHIFT), PRCM_DEV_CLK_FACTORN_8 = (7U << PRCM_DEV_CLK_FACTORN_SHIFT), PRCM_DEV_CLK_FACTORN_9 = (8U << PRCM_DEV_CLK_FACTORN_SHIFT), PRCM_DEV_CLK_FACTORN_10 = (9U << PRCM_DEV_CLK_FACTORN_SHIFT), PRCM_DEV_CLK_FACTORN_11 = (10U << PRCM_DEV_CLK_FACTORN_SHIFT), PRCM_DEV_CLK_FACTORN_12 = (11U << PRCM_DEV_CLK_FACTORN_SHIFT), PRCM_DEV_CLK_FACTORN_13 = (12U << PRCM_DEV_CLK_FACTORN_SHIFT), PRCM_DEV_CLK_FACTORN_14 = (13U << PRCM_DEV_CLK_FACTORN_SHIFT), PRCM_DEV_CLK_FACTORN_15 = (14U << PRCM_DEV_CLK_FACTORN_SHIFT), PRCM_DEV_CLK_FACTORN_16 = (15U << PRCM_DEV_CLK_FACTORN_SHIFT), } PRCM_DevClkFactorN; #define PRCM_DEV_CLK_FACTOR(m, n) ((m) | (n)) #define PRCM_DEV_CLK_FACTOR_MASK (PRCM_DEV_CLK_FACTORM_MASK | PRCM_DEV_CLK_FACTORN_MASK) typedef enum { #if (CONFIG_CHIP_ARCH_VER == 2) PRCM_DEV_CLK_FACTOR_384M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_5, PRCM_DEV_CLK_FACTORN_1), PRCM_DEV_CLK_FACTOR_320M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_6, PRCM_DEV_CLK_FACTORN_1), PRCM_DEV_CLK_FACTOR_274M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_7, PRCM_DEV_CLK_FACTORN_1), PRCM_DEV_CLK_FACTOR_240M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_8, PRCM_DEV_CLK_FACTORN_1), PRCM_DEV_CLK_FACTOR_213M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_9, PRCM_DEV_CLK_FACTORN_1), PRCM_DEV_CLK_FACTOR_192M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_5, PRCM_DEV_CLK_FACTORN_2), /* default */ PRCM_DEV_CLK_FACTOR_160M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_6, PRCM_DEV_CLK_FACTORN_2), PRCM_DEV_CLK_FACTOR_137M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_7, PRCM_DEV_CLK_FACTORN_2), PRCM_DEV_CLK_FACTOR_128M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_5, PRCM_DEV_CLK_FACTORN_3), PRCM_DEV_CLK_FACTOR_120M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_8, PRCM_DEV_CLK_FACTORN_2), PRCM_DEV_CLK_FACTOR_107M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_9, PRCM_DEV_CLK_FACTORN_2), PRCM_DEV_CLK_FACTOR_96M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_5, PRCM_DEV_CLK_FACTORN_4), PRCM_DEV_CLK_FACTOR_80M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_8, PRCM_DEV_CLK_FACTORN_3), PRCM_DEV_CLK_FACTOR_64M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_6, PRCM_DEV_CLK_FACTORN_5), PRCM_DEV_CLK_FACTOR_60M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_8, PRCM_DEV_CLK_FACTORN_4), PRCM_DEV_CLK_FACTOR_48M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_8, PRCM_DEV_CLK_FACTORN_5), PRCM_DEV_CLK_FACTOR_24M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_8, PRCM_DEV_CLK_FACTORN_10), #elif (CONFIG_CHIP_ARCH_VER == 3) PRCM_DEV_CLK_FACTOR_240M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_4, PRCM_DEV_CLK_FACTORN_1), PRCM_DEV_CLK_FACTOR_192M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_5, PRCM_DEV_CLK_FACTORN_1), PRCM_DEV_CLK_FACTOR_160M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_6, PRCM_DEV_CLK_FACTORN_1), /* default */ PRCM_DEV_CLK_FACTOR_120M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_4, PRCM_DEV_CLK_FACTORN_2), PRCM_DEV_CLK_FACTOR_96M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_5, PRCM_DEV_CLK_FACTORN_2), PRCM_DEV_CLK_FACTOR_80M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_6, PRCM_DEV_CLK_FACTORN_2), PRCM_DEV_CLK_FACTOR_64M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_5, PRCM_DEV_CLK_FACTORN_3), PRCM_DEV_CLK_FACTOR_60M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_4, PRCM_DEV_CLK_FACTORN_4), PRCM_DEV_CLK_FACTOR_48M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_4, PRCM_DEV_CLK_FACTORN_5), PRCM_DEV_CLK_FACTOR_24M = PRCM_DEV_CLK_FACTOR(PRCM_DEV_CLK_FACTORM_4, PRCM_DEV_CLK_FACTORN_10), #endif } PRCM_DevClkFactor; #if (CONFIG_CHIP_ARCH_VER == 2) /* * bit field definition of PRCM->AUD_PLL_BIAS */ #define PRCM_AUD_PLL_VCO_BIAS_SHIFT 24 /* R/W */ #define PRCM_AUD_PLL_VCO_BIAS_MASK (0x1F << PRCM_AUD_PLL_VCO_BIAS_SHIFT) #define PRCM_AUD_PLL_CUR_BIAS_SHIFT 16 /* R/W */ #define PRCM_AUD_PLL_CUR_BIAS_MASK (0x1F << PRCM_AUD_PLL_CUR_BIAS_SHIFT) /* * bit field definition of PRCM->AUD_PLL_PAT_CTRL */ #define PRCM_AUD_DIG_DELT_PAT_EN_BIT HAL_BIT(31) /* R/W */ #define PRCM_AUD_PLL_PAT_PARAM_SHIFT 0 #define PRCM_AUD_PLL_PAT_PARAM_MASK 0x7FFFFFFFU typedef enum { PRCM_AUD_PLL24M_PAT_PARAM_HOSC13M = 0x00000000U, PRCM_AUD_PLL24M_PAT_PARAM_HOSC19M2 = 0x00000000U, PRCM_AUD_PLL24M_PAT_PARAM_HOSC24M = 0x00000000U, PRCM_AUD_PLL24M_PAT_PARAM_HOSC26M = 0x00000000U, PRCM_AUD_PLL24M_PAT_PARAM_HOSC40M = 0x00000000U, PRCM_AUD_PLL24M_PAT_PARAM_HOSC50M = 0x00000000U, PRCM_AUD_PLL24M_PAT_PARAM_HOSC52M = 0xc0011FAAU, PRCM_AUD_PLL22M_PAT_PARAM_HOSC13M = 0xC0019468U, PRCM_AUD_PLL22M_PAT_PARAM_HOSC19M2 = 0x00000000U, PRCM_AUD_PLL22M_PAT_PARAM_HOSC24M = 0x00000000U, PRCM_AUD_PLL22M_PAT_PARAM_HOSC26M = 0x00000000U, PRCM_AUD_PLL22M_PAT_PARAM_HOSC40M = 0x00000000U, PRCM_AUD_PLL22M_PAT_PARAM_HOSC50M = 0x00000000U, PRCM_AUD_PLL22M_PAT_PARAM_HOSC52M = 0x00000000U } PRCM_AudPLLPatParam; #endif #if (CONFIG_CHIP_ARCH_VER == 2) /* * bit field definition of PRCM->AUD_PLL_CTRL, 0x54 */ #define PRCM_AUD_PLL_EN_BIT HAL_BIT(31) /* R/W */ #define PRCM_AUD_PLL_PARAM_SHIFT 0 #define PRCM_AUD_PLL_PARAM_MASK 0x7FFFFFFFU typedef enum { PRCM_AUD_PLL24M_PARAM_HOSC13M = 0x8003780FU, PRCM_AUD_PLL24M_PARAM_HOSC19M2 = 0x80037F18U, PRCM_AUD_PLL24M_PARAM_HOSC24M = 0x80035514U, PRCM_AUD_PLL24M_PARAM_HOSC26M = 0x8003781FU, PRCM_AUD_PLL24M_PARAM_HOSC40M = 0x80033A17U, PRCM_AUD_PLL24M_PARAM_HOSC50M = 0x8003381CU, PRCM_AUD_PLL24M_PARAM_HOSC52M = 0x81030603U, /*22.5792*/ PRCM_AUD_PLL22M_PARAM_HOSC13M = 0x81031A03U, PRCM_AUD_PLL22M_PARAM_HOSC19M2 = 0x80037E1AU, PRCM_AUD_PLL22M_PARAM_HOSC24M = 0x80034E14U, PRCM_AUD_PLL22M_PARAM_HOSC26M = 0x80034112U, PRCM_AUD_PLL22M_PARAM_HOSC40M = 0x8003451EU, PRCM_AUD_PLL22M_PARAM_HOSC50M = 0x8003371EU, PRCM_AUD_PLL22M_PARAM_HOSC52M = 0x80032012U } PRCM_AudPLLParam; #endif /* * bit field definition of PRCM->DCXO_CTRL, 0x58 (R/W) */ #define PRCM_DCXO_EN_BIT HAL_BIT(31) /* R/W */ #define PRCM_FREQ_OFFSET_SHIFT 20 /* R/W, R */ #define PRCM_FREQ_OFFSET_MASK (0x7f << PRCM_FREQ_OFFSET_SHIFT) #define PRCM_ICTRL_OFFSET_SHIFT 12 /* R/W, R */ #define PRCM_ICTRL_OFFSET_MASK (0x1f << PRCM_ICTRL_OFFSET_SHIFT) #if (CONFIG_CHIP_ARCH_VER == 2) /* * bit field definition of PRCM->HXTALOUT_CTRL */ #define PRCM_HXTALOUT_EN_BIT HAL_BIT(0) /* * bit field definition of PRCM->DEV2_CLK_CTRL */ #define PRCM_DEV2_CLK_EN_BIT HAL_BIT(31) /* * PRCM_DEV_CLOCK = SYS_PLL_CLOCK / M / N * - SYS_PLL_CLOCK: 1920 MHz * - M: [24, 26] * - N: [16, 19] */ #define PRCM_DEV2_FACTOR_M_SHIFT 24 #define PRCM_DEV2_FACTOR_M_VMASK (0x7U) #define PRCM_DEV2_FACTOR_M_MASK (PRCM_DEV2_FACTOR_M_VMASK << PRCM_DEV2_FACTOR_M_SHIFT) typedef enum { PRCM_DEV2_CLK_FACTORM_5 = (0U << PRCM_DEV2_FACTOR_M_SHIFT), PRCM_DEV2_CLK_FACTORM_6 = (1U << PRCM_DEV2_FACTOR_M_SHIFT), PRCM_DEV2_CLK_FACTORM_7 = (2U << PRCM_DEV2_FACTOR_M_SHIFT), PRCM_DEV2_CLK_FACTORM_8 = (3U << PRCM_DEV2_FACTOR_M_SHIFT), PRCM_DEV2_CLK_FACTORM_9 = (4U << PRCM_DEV2_FACTOR_M_SHIFT), } PRCM_Dev2ClkFactorM; #define PRCM_DEV2_FACTOR_N_SHIFT 16 #define PRCM_DEV2_FACTOR_N_VMASK (0xFU) #define PRCM_DEV2_FACTOR_N_MASK (PRCM_DEV2_FACTOR_N_VMASK << PRCM_DEV2_FACTOR_N_SHIFT) typedef enum { PRCM_DEV2_CLK_FACTORN_1 = (0U << PRCM_DEV2_FACTOR_N_SHIFT), PRCM_DEV2_CLK_FACTORN_2 = (1U << PRCM_DEV2_FACTOR_N_SHIFT), PRCM_DEV2_CLK_FACTORN_3 = (2U << PRCM_DEV2_FACTOR_N_SHIFT), PRCM_DEV2_CLK_FACTORN_4 = (3U << PRCM_DEV2_FACTOR_N_SHIFT), PRCM_DEV2_CLK_FACTORN_5 = (4U << PRCM_DEV2_FACTOR_N_SHIFT), PRCM_DEV2_CLK_FACTORN_6 = (5U << PRCM_DEV2_FACTOR_N_SHIFT), PRCM_DEV2_CLK_FACTORN_7 = (6U << PRCM_DEV2_FACTOR_N_SHIFT), PRCM_DEV2_CLK_FACTORN_8 = (7U << PRCM_DEV2_FACTOR_N_SHIFT), PRCM_DEV2_CLK_FACTORN_9 = (8U << PRCM_DEV2_FACTOR_N_SHIFT), PRCM_DEV2_CLK_FACTORN_10 = (9U << PRCM_DEV2_FACTOR_N_SHIFT), PRCM_DEV2_CLK_FACTORN_11 = (10U << PRCM_DEV2_FACTOR_N_SHIFT), PRCM_DEV2_CLK_FACTORN_12 = (11U << PRCM_DEV2_FACTOR_N_SHIFT), PRCM_DEV2_CLK_FACTORN_13 = (12U << PRCM_DEV2_FACTOR_N_SHIFT), PRCM_DEV2_CLK_FACTORN_14 = (13U << PRCM_DEV2_FACTOR_N_SHIFT), PRCM_DEV2_CLK_FACTORN_15 = (14U << PRCM_DEV2_FACTOR_N_SHIFT), PRCM_DEV2_CLK_FACTORN_16 = (15U << PRCM_DEV2_FACTOR_N_SHIFT), } PRCM_Dev2ClkFactorN; #define PRCM_DEV2_CLK_FACTOR(m, n) ((m) | (n)) #define PRCM_DEV2_CLK_FACTOR_MASK (PRCM_DEV2_FACTOR_N_MASK | PRCM_DEV2_FACTOR_M_MASK) typedef enum { PRCM_DEV2_CLK_FACTOR_384M = PRCM_DEV2_CLK_FACTOR(PRCM_DEV2_CLK_FACTORM_5, PRCM_DEV2_CLK_FACTORN_1), PRCM_DEV2_CLK_FACTOR_320M = PRCM_DEV2_CLK_FACTOR(PRCM_DEV2_CLK_FACTORM_6, PRCM_DEV2_CLK_FACTORN_1), PRCM_DEV2_CLK_FACTOR_274M = PRCM_DEV2_CLK_FACTOR(PRCM_DEV2_CLK_FACTORM_7, PRCM_DEV2_CLK_FACTORN_1), PRCM_DEV2_CLK_FACTOR_240M = PRCM_DEV2_CLK_FACTOR(PRCM_DEV2_CLK_FACTORM_8, PRCM_DEV2_CLK_FACTORN_1), PRCM_DEV2_CLK_FACTOR_213M = PRCM_DEV2_CLK_FACTOR(PRCM_DEV2_CLK_FACTORM_9, PRCM_DEV2_CLK_FACTORN_1), PRCM_DEV2_CLK_FACTOR_192M = PRCM_DEV2_CLK_FACTOR(PRCM_DEV2_CLK_FACTORM_5, PRCM_DEV2_CLK_FACTORN_2), /* default */ PRCM_DEV2_CLK_FACTOR_160M = PRCM_DEV2_CLK_FACTOR(PRCM_DEV2_CLK_FACTORM_6, PRCM_DEV2_CLK_FACTORN_2), PRCM_DEV2_CLK_FACTOR_137M = PRCM_DEV2_CLK_FACTOR(PRCM_DEV2_CLK_FACTORM_7, PRCM_DEV2_CLK_FACTORN_2), PRCM_DEV2_CLK_FACTOR_128M = PRCM_DEV2_CLK_FACTOR(PRCM_DEV2_CLK_FACTORM_5, PRCM_DEV2_CLK_FACTORN_3), PRCM_DEV2_CLK_FACTOR_120M = PRCM_DEV2_CLK_FACTOR(PRCM_DEV2_CLK_FACTORM_8, PRCM_DEV2_CLK_FACTORN_2), PRCM_DEV2_CLK_FACTOR_107M = PRCM_DEV2_CLK_FACTOR(PRCM_DEV2_CLK_FACTORM_9, PRCM_DEV2_CLK_FACTORN_2), PRCM_DEV2_CLK_FACTOR_96M = PRCM_DEV2_CLK_FACTOR(PRCM_DEV2_CLK_FACTORM_5, PRCM_DEV2_CLK_FACTORN_4), PRCM_DEV2_CLK_FACTOR_80M = PRCM_DEV2_CLK_FACTOR(PRCM_DEV2_CLK_FACTORM_8, PRCM_DEV2_CLK_FACTORN_3), PRCM_DEV2_CLK_FACTOR_64M = PRCM_DEV2_CLK_FACTOR(PRCM_DEV2_CLK_FACTORM_6, PRCM_DEV2_CLK_FACTORN_5), PRCM_DEV2_CLK_FACTOR_60M = PRCM_DEV2_CLK_FACTOR(PRCM_DEV2_CLK_FACTORM_8, PRCM_DEV2_CLK_FACTORN_4), PRCM_DEV2_CLK_FACTOR_48M = PRCM_DEV2_CLK_FACTOR(PRCM_DEV2_CLK_FACTORM_8, PRCM_DEV2_CLK_FACTORN_5), PRCM_DEV2_CLK_FACTOR_24M = PRCM_DEV2_CLK_FACTOR(PRCM_DEV2_CLK_FACTORM_8, PRCM_DEV2_CLK_FACTORN_10), } PRCM_Dev2ClkFactor; #endif /* * bit field definition of PRCM->POWERCTRL_CFG, 0x74 */ #if (CONFIG_CHIP_ARCH_VER == 3) #define PRCM_RCOSC_CAL_START_SRC_SHIFT (6) #define PRCM_RCOSC_CAL_START_SRC_MASK (0x3U << PRCM_RCOSC_CAL_START_SRC_SHIFT) typedef enum { PRCM_RCOSC_CAL_START_APPSLEEP = (0x0U << PRCM_RCOSC_CAL_START_SRC_SHIFT), PRCM_RCOSC_CAL_START_WLANSLEEP = (0x1U << PRCM_RCOSC_CAL_START_SRC_SHIFT), PRCM_RCOSC_CAL_START_APPANDWLANSLEEP = (0x2U << PRCM_RCOSC_CAL_START_SRC_SHIFT), PRCM_RCOSC_CAL_START_LDO1SHUTDOWN = (0x3U << PRCM_RCOSC_CAL_START_SRC_SHIFT), } PRCM_RcoscCalStartSrc; /* * bit field definition of PRCM->SYS1_RST_STATUS, 0x80 */ #define PRCM_BLE_RESET_BIT HAL_BIT(16) /* R */ #define PRCM_WLAN_RESET_BIT HAL_BIT(17) /* R */ /* * bit field definition of PRCM->SYS1_CTRL, 0x84 */ #endif /* * bit field definition of PRCM->SYS1_CTRL, 0x80 */ #define PRCM_CPUA_RESET_BIT HAL_BIT(1) /* R */ #define PRCM_SYS1_RESET_BIT HAL_BIT(0) /* R */ /* * bit field definition of PRCM->SYS1_STATUS, 0x84 */ #define PRCM_CPUA_SLEEP_STATUS_BIT HAL_BIT(2) /* R */ #define PRCM_CPUA_DEEPSLEEP_STATUS_BIT HAL_BIT(1) /* R */ #define PRCM_SYS1_ALIVE_BIT HAL_BIT(0) /* R */ /* * bit field definition of PRCM->SYS3_CTRL */ #define PRCM_SYS3_RESET_BIT HAL_BIT(0) /* R */ /* * bit field definition of PRCM->SYS3_STATUS */ #define PRCM_CPUW_SLEEP_STATUS_BIT HAL_BIT(2) /* R */ #define PRCM_CPUW_DEEPSLEEP_STATUS_BIT HAL_BIT(1) /* R */ #define PRCM_SYS3_ALIVE_BIT HAL_BIT(0) /* R */ /* * bit field definition of * - PRCM->SYS1_WAKEUP_CTRL (R/W) * - PRCM->SYS1_SLEEP_CTRL (R/W) */ #define PRCM_SYS_WS_PWR_VAL_KEEP 0U /* for all */ #define PRCM_SYS_WS_PWR_VAL_ON 1U /* for PRCM->SYSx_WAKEUP_CTRL */ #define PRCM_SYS_WS_PWR_VAL_OFF 0U /* for PRCM->SYSx_SLEEP_CTRL */ #define PRCM_SYS_WS_PWR_TYPE_LDO1 0U #define PRCM_SYS_WS_PWR_TYPE_SYS1_PWR1 1U #if (CONFIG_CHIP_ARCH_VER == 2) #define PRCM_SYS_WS_PWR_TYPE_SYS1_PWR2 2U #define PRCM_SYS_WS_PWR_TYPE_SYS1_SRAM_PWR1 3U #define PRCM_SYS_WS_PWR_FLAGS_MASK (0x3FU) #elif (CONFIG_CHIP_ARCH_VER == 3) #define PRCM_SYS_WS_PWR_FLAGS_MASK (0x3U) #endif #define PRCM_SYS_WS_PWR_FLAG(val, type) ((val) << (type)) /* * bit field definition of PRCM->SYS1_WAKEUP_CTRL */ #define PRCM_VDDIO_SIP_SW_EN_BIT HAL_BIT(1) /* R/W */ #if (CONFIG_CHIP_ARCH_VER == 2) #define PRCM_SYS_WLAN_SRAM_116K_SWM5_BIT HAL_BIT(28) #define PRCM_SYS_SRAM_32K_SWM4_BIT HAL_BIT(27) #define PRCM_SYS_SRAM_32K_SWM3_BIT HAL_BIT(26) #define PRCM_SYS_SRAM_352K_SWM2_BIT HAL_BIT(25) #define PRCM_SYS_CACHE_SRAM_SWM1_BIT HAL_BIT(24) #define PRCM_SYS_CACHE_SRAM_PWR_CTRL_BIT HAL_BIT(21) #define PRCM_SYS_SRAM_PWR_CTRL_SHIFT 8 #define PRCM_SYS_SRAM_PWR_CTRL_MASK (0x01FFF << PRCM_SYS_SRAM_PWR_CTRL_SHIFT) #define PRCM_SYS_SRAM_PWR_CTRL_MODE(val) ((val) << PRCM_SYS_SRAM_PWR_CTRL_SHIFT) #elif (CONFIG_CHIP_ARCH_VER == 3) #define PRCM_SYS_SRAM_96K_SWM8_BIT HAL_BIT(31) #define PRCM_SYS_SRAM_48K_SWM7_BIT HAL_BIT(30) #define PRCM_SYS_SRAM_16K_SWM6_BIT HAL_BIT(29) #define PRCM_SYS_SRAM_16K_SWM5_BIT HAL_BIT(28) #define PRCM_SYS_SRAM_32K_SWM4_BIT HAL_BIT(27) #define PRCM_SYS_SRAM_96K_SWM3_BIT HAL_BIT(26) #define PRCM_SYS_SRAM_96K_SWM2_BIT HAL_BIT(25) #define PRCM_SYS_SRAM_32K_SWM1_BIT HAL_BIT(24) #define PRCM_SYS_APP_SRAM_PWR_CTRL_MASK (PRCM_SYS_SRAM_48K_SWM7_BIT | \ PRCM_SYS_SRAM_16K_SWM6_BIT | \ PRCM_SYS_SRAM_16K_SWM5_BIT | \ PRCM_SYS_SRAM_32K_SWM4_BIT | \ PRCM_SYS_SRAM_96K_SWM3_BIT | \ PRCM_SYS_SRAM_96K_SWM2_BIT | \ PRCM_SYS_SRAM_32K_SWM1_BIT) #define PRCM_SYS_SRAM_PWR_CTRL_MASK (PRCM_SYS_SRAM_96K_SWM8_BIT | \ PRCM_SYS_APP_SRAM_PWR_CTRL_MASK) #endif /* DCXO_STABLE_REF_TIME, 0xA8 */ #define PRCM_DCXO_STABLE_RFE_TIME_SHIFT 0 /* R/W */ #define PRCM_DCXO_STABLE_RFE_TIME_VMASK 0x03FFU /* DPLL_STABLE_REF_TIME, 0xAC */ #define PRCM_DPLL_STABLE_RFE_TIME_SHIFT 0 /* R/W */ #define PRCM_DPLL_STABLE_RFE_TIME_VMASK 0x00FFU /* LDO_STABLE_REF_TIME, 0xB0 */ #define PRCM_RFIP_LDO_DIG_STABLE_RFE_TIME_SHIFT 8 #define PRCM_RFIP_LDO_DIG_STABLE_REF_TIME_VMASK (0x00FU << PRCM_RFIP_LDO_DIG_STABLE_RFE_TIME_SHIFT) #define PRCM_LDO_STABLE_RFE_TIME_SHIFT 0 #define PRCM_LDO_STABLE_REF_TIME_VMASK (0x0FFU << PRCM_LDO_STABLE_RFE_TIME_SHIFT) /* DIG_SWITCH_REF_TIME, 0xB4 */ #define PRCM_RESET_UP_REF_TIME_SHIFT 16 #define PRCM_RESET_UP_REF_TIME_MASK (0x0FFFF << PRCM_RESET_UP_REF_TIME_SHIFT) #define PRCM_DIG_SWITCH_REF_TIME_SHIFT 0 #define PRCM_DIG_SWITCH_REF_TIME_MASK (0x0FFFF << PRCM_DIG_SWITCH_REF_TIME_SHIFT) /* * bit field definition of PRCM->RTC_LDO_VOLT_CTRL */ #if (__CONFIG_CHIP_ARCH_VER == 2) #define PRCM_RTC_LDO_WORK_VOLT_SHIFT 16 #define PRCM_RTC_LDO_WORK_VOLT_MASK (0x7U << PRCM_RTC_LDO_WORK_VOLT_SHIFT) typedef enum { PRCM_RTC_LDO_WORK_VOLT_1075MV = (0x0U << PRCM_RTC_LDO_WORK_VOLT_SHIFT), PRCM_RTC_LDO_WORK_VOLT_975MV = (0x1U << PRCM_RTC_LDO_WORK_VOLT_SHIFT), PRCM_RTC_LDO_WORK_VOLT_875MV = (0x2U << PRCM_RTC_LDO_WORK_VOLT_SHIFT), PRCM_RTC_LDO_WORK_VOLT_775MV = (0x3U << PRCM_RTC_LDO_WORK_VOLT_SHIFT), PRCM_RTC_LDO_WORK_VOLT_675MV = (0x4U << PRCM_RTC_LDO_WORK_VOLT_SHIFT), PRCM_RTC_LDO_WORK_VOLT_600MV = (0x5U << PRCM_RTC_LDO_WORK_VOLT_SHIFT), PRCM_RTC_LDO_WORK_VOLT_1175MV = (0x6U << PRCM_RTC_LDO_WORK_VOLT_SHIFT), PRCM_RTC_LDO_WORK_VOLT_1275MV = (0x7U << PRCM_RTC_LDO_WORK_VOLT_SHIFT), } PRCM_RTCLDOWorkVolt; #define PRCM_RTC_LDO_RETENTION_VOLT_SHIFT 0 #define PRCM_RTC_LDO_RETENTION_VOLT_MASK (0x7U << PRCM_RTC_LDO_RETENTION_VOLT_SHIFT) typedef enum { PRCM_RTC_LDO_RETENTION_VOLT_1075MV = (0x0U << PRCM_RTC_LDO_RETENTION_VOLT_SHIFT), PRCM_RTC_LDO_RETENTION_VOLT_975MV = (0x1U << PRCM_RTC_LDO_RETENTION_VOLT_SHIFT), PRCM_RTC_LDO_RETENTION_VOLT_875MV = (0x2U << PRCM_RTC_LDO_RETENTION_VOLT_SHIFT), PRCM_RTC_LDO_RETENTION_VOLT_775MV = (0x3U << PRCM_RTC_LDO_RETENTION_VOLT_SHIFT), PRCM_RTC_LDO_RETENTION_VOLT_675MV = (0x4U << PRCM_RTC_LDO_RETENTION_VOLT_SHIFT), PRCM_RTC_LDO_RETENTION_VOLT_600MV = (0x5U << PRCM_RTC_LDO_RETENTION_VOLT_SHIFT), PRCM_RTC_LDO_RETENTION_VOLT_1175MV = (0x6U << PRCM_RTC_LDO_RETENTION_VOLT_SHIFT), PRCM_RTC_LDO_RETENTION_VOLT_1275MV = (0x7U << PRCM_RTC_LDO_RETENTION_VOLT_SHIFT), } PRCM_RTCLDORetentionVolt; #elif (CONFIG_CHIP_ARCH_VER == 3) #define PRCM_RTC_LDO_VOLT_SHIFT 0 #define PRCM_RTC_LDO_VOLT_MASK (0x7U << PRCM_RTC_LDO_VOLT_SHIFT) typedef enum { PRCM_RTC_LDO_VOLT_1075MV = (0x0U << PRCM_RTC_LDO_VOLT_SHIFT), PRCM_RTC_LDO_VOLT_975MV = (0x1U << PRCM_RTC_LDO_VOLT_SHIFT), PRCM_RTC_LDO_VOLT_875MV = (0x2U << PRCM_RTC_LDO_VOLT_SHIFT), PRCM_RTC_LDO_VOLT_775MV = (0x3U << PRCM_RTC_LDO_VOLT_SHIFT), PRCM_RTC_LDO_VOLT_675MV = (0x4U << PRCM_RTC_LDO_VOLT_SHIFT), PRCM_RTC_LDO_VOLT_600MV = (0x5U << PRCM_RTC_LDO_VOLT_SHIFT), PRCM_RTC_LDO_VOLT_1175MV = (0x6U << PRCM_RTC_LDO_VOLT_SHIFT), PRCM_RTC_LDO_VOLT_1275MV = (0x7U << PRCM_RTC_LDO_VOLT_SHIFT), } PRCM_RTCLDOVolt; #endif /* BANDGAP_STABLE_REF_TIME */ #define PRCM_BANDGAP_STABLE_REF_TIME_MASK 0x0FFU /* DCDC_STABLE_REF_TIME, 0xC0 */ #define PRCM_LDOTOPWM_STABLE_RFE_TIME_SHIFT 16 /* R/W */ #define PRCM_LDOTOPWM_STABLE_RFE_TIME_VMASK (0x3FFU << PRCM_LDOTOPWM_STABLE_RFE_TIME_SHIFT) #define PRCM_DCDC_STABLE_RFE_TIME_SHIFT 0 /* R/W */ #define PRCM_DCDC_STABLE_REF_TIME_VMASK (0x3FFU << PRCM_DCDC_STABLE_RFE_TIME_SHIFT) /* BLE_RTC_RST_CTRL, 0xD0 */ #define PRCM_BLE_RTC_RST_RST_BIT HAL_BIT(0) /* R/W */ /* BLE_RTC_CLK_CTRL */ #define PRCM_BLE_32M_RST_CLK_EN_BIT HAL_BIT(1) /* R/W */ #define PRCM_BLE_48M_RST_CLK_EN_BIT HAL_BIT(0) /* R/W */ /* RFAS_CTRL_REG */ #define PRCM_BLE_RFAS_RST_BIT HAL_BIT(0) /* R/W */ /* * bit field definition of PRCM->CPUA_BOOT_FLAG, 0x100 */ #define PRCM_CPUA_BOOT_FLAG_WR_LOCK (0x429BU << 16) /* W */ #define PRCM_CPUA_BOOT_FLAG_SHIFT 0 /* R/W */ #define PRCM_CPUA_BOOT_FLAG_MASK (0xFU << PRCM_CPUA_BOOT_FLAG_SHIFT) typedef enum { PRCM_CPUA_BOOT_FROM_COLD_RESET = (0U << PRCM_CPUA_BOOT_FLAG_SHIFT), PRCM_CPUA_BOOT_FROM_DEEPSLEEP = (1U << PRCM_CPUA_BOOT_FLAG_SHIFT), PRCM_CPUA_BOOT_FROM_SYS_UPDATE = (2U << PRCM_CPUA_BOOT_FLAG_SHIFT) } PRCM_CPUABootFlag; /* PRCM->CPUA_BOOT_ADDR */ /* PRCM->CPUA_BOOT_ARG */ /* PRCM->CPUA_PRIV_REG */ /* PRCM->CPUA_PRIV_REG_0T3, 0x10C~0x118 */ #define PRCM_CPUA_PRIV_DATA_ID_NUM 4 /* * PRCM->WDG_NORESET_PERIPH, 0x11C * - no reset peripherals bits are the same as CCM_BusPeriphBit */ #if (CONFIG_CHIP_ARCH_VER == 2) #define PRCM_WDG_NORESET_PERIPH_EN_BIT HAL_BIT(31) #define PRCM_WDG_NORESET_PERIPH_SHIFT 0U #define PRCM_WDG_NORESET_PERIPH_MASK 0x7FFFFFFFU #elif (CONFIG_CHIP_ARCH_VER == 3) #define PRCM_WDG_NORESET_PERIPH_EN_BIT HAL_BIT(27) #define PRCM_WDG_NORESET_PERIPH_SHIFT 0U #define PRCM_WDG_NORESET_PERIPH_MASK 0xF7FFFFFFU #endif /* * bit field definition of * - PRCM->CPUA_WAKE_TIMER_CNT, 0x120 */ #define PRCM_CPUx_WAKE_TIMER_EN_BIT HAL_BIT(31) /* R/W */ #define PRCM_CPUx_WAKE_TIMER_CUR_VAL_MASK 0x7FFFFFFFU /* R */ /* * bit field definition of * - PRCM->CPUA_WAKE_TIMER_CMP */ #define PRCM_CPUx_WAKE_TIMER_PENDING_BIT HAL_BIT(31) /* R/W */ #define PRCM_CPUx_WAKE_TIMER_CMP_VAL_MASK 0x7FFFFFFFU /* R/W */ /* * bit field definition of * - PRCM->CPUA_WAKE_IO_EN * - PRCM->CPUA_WAKE_IO_MODE * - PRCM->CPUA_WAKE_IO_STATUS * - PRCM->CPUA_WAKE_IO_HOLD */ #if (CONFIG_CHIP_ARCH_VER == 2) #define PRCM_WAKEUP_IO0T3_DEDOUNCE_CYCLE_SHIFT(n) (16 + (n * 4)) #define PRCM_WAKEUP_IO0T3_DEDOUNCE_CYCLE_MASK(n) (0xFU << PRCM_WAKEUP_IO0T3_DEDOUNCE_CYCLE_SHIFT(n)) #elif (CONFIG_CHIP_ARCH_VER == 3) #define PRCM_WAKEUP_IO0T7_DEDOUNCE_CYCLE_SHIFT(n) (0 + (n * 4)) #define PRCM_WAKEUP_IO0T7_DEDOUNCE_CYCLE_MASK(n) (0xFU << PRCM_WAKEUP_IO0T7_DEDOUNCE_CYCLE_SHIFT(n)) #define PRCM_WAKEUP_IO8T13_DEDOUNCE_CYCLE_SHIFT(n) (0 + (n * 4)) #define PRCM_WAKEUP_IO8T13_DEDOUNCE_CYCLE_MASK(n) (0xFU << PRCM_WAKEUP_IO8T13_DEDOUNCE_CYCLE_SHIFT(n)) #endif typedef enum { PRCM_WAKE_IO_0 = HAL_BIT(0), PRCM_WAKE_IO_1 = HAL_BIT(1), PRCM_WAKE_IO_2 = HAL_BIT(2), PRCM_WAKE_IO_3 = HAL_BIT(3), PRCM_WAKE_IO_4 = HAL_BIT(4), PRCM_WAKE_IO_5 = HAL_BIT(5), PRCM_WAKE_IO_6 = HAL_BIT(6), PRCM_WAKE_IO_7 = HAL_BIT(7), PRCM_WAKE_IO_8 = HAL_BIT(8), PRCM_WAKE_IO_9 = HAL_BIT(9), #if (CONFIG_CHIP_ARCH_VER == 2) #define WAKEUP_IO_NUM 10 #define WAKEUP_IO_MAX 10 #elif (CONFIG_CHIP_ARCH_VER == 3) PRCM_WAKE_IO_10 = HAL_BIT(10), PRCM_WAKE_IO_11 = HAL_BIT(11), PRCM_WAKE_IO_12 = HAL_BIT(12), PRCM_WAKE_IO_13 = HAL_BIT(13), #define WAKEUP_IO_NUM 14 #define WAKEUP_IO_MAX 14 #endif } PRCM_WakeIO; #define WAKEUP_IO_MASK ((1 << WAKEUP_IO_MAX) - 1) #define PRCM_WAKEUP_IOx_EN_SHIFT (0) #define PRCM_WAKEUP_IOx_EN_VMASK (WAKEUP_IO_MASK) #define PRCM_WAKEUP_IOx_EN_MASK (WAKEUP_IO_MASK << PRCM_WAKEUP_IOx_EN_SHIFT) #if (CONFIG_CHIP_ARCH_VER == 3) #define PRCM_WAKEUP_IOx_MODE_SHIFT 16 #define PRCM_WAKEUP_IOx_MODE_MASK (PRCM_WAKEUP_IOx_VMASK << PRCM_WAKEUP_IOx_MODE_SHIFT) #define PRCM_WAKEUP_IO_MODE_POSITIVE(n) (1 << (n + PRCM_WAKEUP_IOx_MODE_SHIFT)) #endif /* * bit field definition of * - PRCM->CPUA_WAKE_IO_MODE */ #define PRCM_WKAEUP_DEB_CLK1_SHIFT 28 #define PRCM_WKAEUP_DEB_CLK1_MASK (0xFU << PRCM_WKAEUP_DEB_CLK1_SHIFT) #define PRCM_WKAEUP_DEB_CLK0_SHIFT 24 #define PRCM_WKAEUP_DEB_CLK0_MASK (0xFU << PRCM_WKAEUP_DEB_CLK0_SHIFT) #if (CONFIG_CHIP_ARCH_VER == 2) #define PRCM_WAKEUP_IOX_DEB_CLK_SRC_SHIFT 12 #define PRCM_WAKEUP_IOX_DEB_CLK_SRC_MASK (0x3U << PRCM_WAKEUP_IOX_DEB_CLK_SRC_SHIFT) #endif typedef enum { PRCM_WAKE_IO_EVT_FALLING_EDGE = 0U, PRCM_WAKE_IO_EVT_RISING_EDGE = 1U, } PRCM_WakeIOEvent; /* * bit field definition of PRCM->CPUA_WAKE_IO_GLOBAL_EN */ #define PRCM_WAKEUP_IO9_DEDOUNCE_CYCLE_SHIFT 28 #define PRCM_WAKEUP_IO9_DEDOUNCE_CYCLE_MASK (0xFU << PRCM_WAKEUP_IO9_DEDOUNCE_CYCLE_SHIFT) #define PRCM_WAKEUP_IO8_DEDOUNCE_CYCLE_SHIFT 24 #define PRCM_WAKEUP_IO8_DEDOUNCE_CYCLE_MASK (0xFU << PRCM_WAKEUP_IO8_DEDOUNCE_CYCLE_SHIFT) #define PRCM_WAKEUP_IO7_DEDOUNCE_CYCLE_SHIFT 20 #define PRCM_WAKEUP_IO7_DEDOUNCE_CYCLE_MASK (0xFU << PRCM_WAKEUP_IO7_DEDOUNCE_CYCLE_SHIFT) #define PRCM_WAKEUP_IO6_DEDOUNCE_CYCLE_SHIFT 16 #define PRCM_WAKEUP_IO6_DEDOUNCE_CYCLE_MASK (0xFU << PRCM_WAKEUP_IO6_DEDOUNCE_CYCLE_SHIFT) #define PRCM_WAKEUP_IO5_DEDOUNCE_CYCLE_SHIFT 12 #define PRCM_WAKEUP_IO5_DEDOUNCE_CYCLE_MASK (0xFU << PRCM_WAKEUP_IO5_DEDOUNCE_CYCLE_SHIFT) #define PRCM_WAKEUP_IO4_DEDOUNCE_CYCLE_SHIFT 8 #define PRCM_WAKEUP_IO4_DEDOUNCE_CYCLE_MASK (0xFU << PRCM_WAKEUP_IO4_DEDOUNCE_CYCLE_SHIFT) #define PRCM_WAKEUP_IO4T9_DEDOUNCE_CYCLE_SHIFT(n) (8 + (n - 4) * 4) #define PRCM_WAKEUP_IO4T9_DEDOUNCE_CYCLE_MASK(n) (0xFU << PRCM_WAKEUP_IO4T9_DEDOUNCE_CYCLE_SHIFT(n)) #define PRCM_WAKE_IO_GLOBAL_EN_BIT HAL_BIT(0) /* bit field definition of LDO_MODE_SW_SEL: 0x150 */ #define PRCM_TOP_LDO_LQ_MODE_BIT HAL_BIT(2) #define PRCM_SYS_LDO_LQ_MODE_BIT HAL_BIT(1) #define PRCM_LDO_MODE_SW_SEL_EN_BIT HAL_BIT(0) /* bit field definition of DCDC_PARAM_CTRL 0x200 */ #define PRCM_DCDC_BANDGAP_TRIM_SHIFT 24 #define PRCM_DCDC_BANDGAP_TRIM_MASK (0x1FU << PRCM_DCDC_BANDGAP_TRIM_SHIFT) #define PRCM_TOP_LDO_DEEPSLEEP_EN_BIT HAL_BIT(23) /* bit field definition of DIG_LDO_PARAM 0x020c */ #define PRCM_DIG_LDO_BGOUT_TRIM_SHIFT 8 #define PRCM_DIG_LDO_BGOUT_TRIM_VMASK 0xFU #define PRCM_DIG_LDO_BGOUT_TRIM_MASK (PRCM_DIG_LDO_BGOUT_TRIM_VMASK << PRCM_DIG_LDO_BGOUT_TRIM_SHIFT) /* ANA_BANDGAP */ /* CLK_LDO_PARAM */ /* DIG_LDO_PARAM */ #define PRCM_DIG_LDO_BANDGAP_TRIM_SHIFT 8 #define PRCM_DIG_LDO_BANDGAP_TRIM_MASK (0xFU << PRCM_DIG_LDO_BANDGAP_TRIM_SHIFT) /* DPLL_STATUS */ /* BONDING_IO */ #define PRCM_FLASH_SIP_EN_BIT HAL_BIT(1) #define PRCM_FLASH_SIP_MODE_SHIFT 2 /* R */ #define PRCM_FLASH_SIP_MODE_MASK (0x1U << PRCM_FLASH_SIP_MODE_SHIFT) typedef enum { PRCM_FLASH_SIP_MODE0 = (0x0U << PRCM_FLASH_SIP_MODE_SHIFT), PRCM_FLASH_SIP_MODE1 = (0x1U << PRCM_FLASH_SIP_MODE_SHIFT) } PRCM_FlashSipMode; /* bit field definition of PRCM->CPU_RESET_SOURCE, 0x218 */ #define PRCM_CPU_IS_WATCHDOG_CPU_RST_SHIFT 9 #define PRCM_CPU_IS_WATCHDOG_CPU_RST_MASK (0x3U << PRCM_CPU_IS_WATCHDOG_CPU_RST_SHIFT) typedef enum { PRCM_NO_WATCHDOG_RESET = 0, PRCM_1_TIME_WATCHDOG = 1, PRCM_2_TIME_WATCHDOG = 2, PRCM_3_TIME_WATCHDOG = 3, } PRCM_WATCHDOG_CPU_RST; #define PRCM_CPU_IS_WATCHDOG_ALL_RST_BIT HAL_BIT(8) #define PRCM_CPU_IS_PMU_RST_BIT HAL_BIT(1) #define PRCM_CPU_IS_PWRON_RST_BIT HAL_BIT(0) /* bit field definition of PRCM->WLAN_HIF_OVERRIDE_CTRL */ #define PRCM_WLAN_IRQ_OVR_HIF_BIT HAL_BIT(7) #define PRCM_WLAN_WUP_OVR_HIF_BIT HAL_BIT(6) #define PRCM_WLAN_RESET_CPU_OVR_HIF_BIT HAL_BIT(5) #define PRCM_WLAN_DISABLE_CPU_CLK_OVR_HIF_BIT HAL_BIT(4) #define PRCM_WLAN_WUP_BIT HAL_BIT(2) #define PRCM_WLAN_RESET_CPU_BIT HAL_BIT(1) #define PRCM_WLAN_DISABLE_CPU_CLK_BIT HAL_BIT(0) #if (CONFIG_CHIP_ARCH_VER == 3) /* bit field definition of PRCM->SRAM_BIST_CTRL */ #define PRCM_CLK32K_SW_FORCE_EN_BIT HAL_BIT(24) /* 24 bit */ #define PRCM_CLK32K_SW_FORCE_DOWN_BIT HAL_BIT(26) /* 26 bit */ #define PRCM_CLK32K_SW_FORCE_READY_BIT HAL_BIT(27) /* 27 bit */ /* bit field definition of PRCM->WLAN_SRAM_SHARE_CTRL */ #define PRCM_WLAN_SHARE_SRAM_SHIFT (0) #define PRCM_WLAN_SHARE_SRAM_MASK (0x7F << PRCM_WLAN_SHARE_SRAM_SHIFT) typedef enum { PRCM_WLAN_SHARE_NONE = (0x00 << PRCM_WLAN_SHARE_SRAM_SHIFT), PRCM_WLAN_SHARE_16K = (0x01 << PRCM_WLAN_SHARE_SRAM_SHIFT), PRCM_WLAN_SHARE_32K = (0x03 << PRCM_WLAN_SHARE_SRAM_SHIFT), PRCM_WLAN_SHARE_64K = (0x07 << PRCM_WLAN_SHARE_SRAM_SHIFT), PRCM_WLAN_SHARE_96K = (0x0F << PRCM_WLAN_SHARE_SRAM_SHIFT), PRCM_WLAN_SHARE_128K = (0x1F << PRCM_WLAN_SHARE_SRAM_SHIFT), PRCM_CONNECT_MODE_WLAN_SHARE_128K = (0x20 << PRCM_WLAN_SHARE_SRAM_SHIFT), PRCM_CONNECT_MODE_BLE_DEBUG_SHARE_128K = (0x40 << PRCM_WLAN_SHARE_SRAM_SHIFT), } PRCM_WLAN_ShareSramType; /* bit field definition of PRCM->BLE_16K_SRAM_SHARE_CTRL */ #define PRCM_BLE_16K_SHARE_SRAM_BIT HAL_BIT(0) /* bit field definition of PRCM->LPUART0_WAKEUP_CTRL & PRCM->LPUART1_WAKEUP_CTRL */ #define PRCM_LPUART_WAKEUP_EN_BIT HAL_BIT(31) #define PRCM_LPUART_WAKEUP_IN_SEL_SHIFT 16 #define PRCM_LPUART_WAKEUP_IN_SEL_MASK (0x3U << PRCM_LPUART_WAKEUP_IN_SEL_SHIFT) typedef enum { PRCM_LPUART_WAKEUP_IN_USE_UART0 = 0x0U, PRCM_LPUART_WAKEUP_IN_USE_UART1 = 0x1U, PRCM_LPUART_WAKEUP_IN_USE_UART2 = 0x2U, } PRCM_LPUART_WAKEUP_IN_SEL; #define PRCM_LPUART_CLK_SOURCE_SHIFT 0 #define PRCM_LPUART_CLK_SOURCE_MASK (0x1U << PRCM_LPUART_CLK_SOURCE_SHIFT) typedef enum { PRCM_LPUART_CLK_LFCLK_CRYSTAL = (0x0U << PRCM_LPUART_CLK_SOURCE_SHIFT), PRCM_LPUART_CLK_HFCLK_CRYSTAL = (0x1U << PRCM_LPUART_CLK_SOURCE_SHIFT), } PRCM_LPUART_ClkSource; /* bit field definition of PRCM->GPADC_CLK_CTRL 0x0238 */ #define PRCM_GPADC_MCLK_EN_BIT HAL_BIT(31) #define PRCM_GPADC_MCLK_SOURCE_SHIFT 24 #define PRCM_GPADC_MCLK_SOURCE_MASK (0x3U << PRCM_GPADC_MCLK_SOURCE_SHIFT) typedef enum { PRCM_GPADC_MCLK_HFCLK_CRYSTAL = (0x0U << PRCM_GPADC_MCLK_SOURCE_SHIFT), PRCM_GPADC_MCLK_LFCLK_CRYSTAL = (0x1U << PRCM_GPADC_MCLK_SOURCE_SHIFT), } PRCM_GPADC_MClkSource; #define PRCM_GPADC_FACTOR_N_SHIFT 16 #define PRCM_GPADC_FACTOR_N_MASK (0x3U << PRCM_GPADC_FACTOR_N_SHIFT) typedef enum { PRCM_GPADC_CLK_FACTORN_1 = (0U << PRCM_GPADC_FACTOR_N_SHIFT), PRCM_GPADC_CLK_FACTORN_2 = (1U << PRCM_GPADC_FACTOR_N_SHIFT), PRCM_GPADC_CLK_FACTORN_4 = (2U << PRCM_GPADC_FACTOR_N_SHIFT), PRCM_GPADC_CLK_FACTORN_8 = (3U << PRCM_GPADC_FACTOR_N_SHIFT), } PRCM_GPADC_ClkFactorN; /* M = value + 1 (1 ~ 16) */ #define PRCM_GPADC_CLK_FACTORM_SHIFT (0) #define PRCM_GPADC_CLK_FACTORM_MASK (0x0F << PRCM_GPADC_CLK_FACTORM_SHIFT) #define PRCM_GPADC_CLK_FACTORM_VALUE(val) (((val) << PRCM_GPADC_CLK_FACTORM_SHIFT) & PRCM_GPADC_CLK_FACTORM_MASK) /* bit field definition of PRCM->CLK_32K_CTRL 0x023C */ #define PRCM_WLAN_32K_CLK_SOURCE_SHIFT 3 #define PRCM_WLAN_32K_CLK_SOURCE_MASK (0x1U << PRCM_WLAN_32K_CLK_SOURCE_SHIFT) typedef enum { PRCM_WLAN_32K_CLK_RCO_LOSC = (0x0U << PRCM_WLAN_32K_CLK_SOURCE_SHIFT), PRCM_WLAN_32K_CLK_RCO_CALIB = (0x1U << PRCM_WLAN_32K_CLK_SOURCE_SHIFT), } PRCM_WLAN_32K_ClkSource; #define PRCM_WKTIMER_32K_CLK_SOURCE_SHIFT 2 #define PRCM_WKTIMER_32K_CLK_SOURCE_MASK (0x1U << PRCM_WKTIMER_32K_CLK_SOURCE_SHIFT) typedef enum { PRCM_WKTIMER_32K_CLK_RCO_LOSC = (0x0U << PRCM_WKTIMER_32K_CLK_SOURCE_SHIFT), PRCM_WKTIMER_32K_CLK_RCO_CALIB = (0x1U << PRCM_WKTIMER_32K_CLK_SOURCE_SHIFT), } PRCM_WKTIMER_32K_ClkSource; #define PRCM_RTC_32K_CLK_SOURCE_SHIFT 0 #define PRCM_RTC_32K_CLK_SOURCE_MASK (0x3U << PRCM_RTC_32K_CLK_SOURCE_SHIFT) typedef enum { PRCM_RTC_32K_CLK_RCO_LOSC = (0x0U << PRCM_RTC_32K_CLK_SOURCE_SHIFT), PRCM_RTC_32K_CLK_RCO_CALIB = (0x1U << PRCM_RTC_32K_CLK_SOURCE_SHIFT), PRCM_RTC_32K_CLK_HOSC_DIV32K = (0x2U << PRCM_RTC_32K_CLK_SOURCE_SHIFT), } PRCM_RTC_32K_ClkSource; /* bit field definition of PRCM->WAKEUP_SRC_BUS_CLK_CTRL 0x0240 */ typedef enum { PRCM_WAKEUP_SRC_BUS_CLK_BIT_RCCAL = HAL_BIT(7), PRCM_WAKEUP_SRC_BUS_CLK_BIT_GPADC = HAL_BIT(6), PRCM_WAKEUP_SRC_BUS_CLK_BIT_LPUART1 = HAL_BIT(4), PRCM_WAKEUP_SRC_BUS_CLK_BIT_LPUART0 = HAL_BIT(2), PRCM_WAKEUP_SRC_BUS_CLK_BIT_CAPSEN = HAL_BIT(0), } PRCM_WAKEUP_SRC_BusClkBit; /* bit field definition of PRCM->WAKEUP_SRC_RST_CTRL 0x0244 */ typedef enum { PRCM_WAKEUP_SRC_RST_BIT_RCCAL = HAL_BIT(7), PRCM_WAKEUP_SRC_RST_BIT_GPADC = HAL_BIT(6), PRCM_WAKEUP_SRC_RST_BIT_LPUART1 = HAL_BIT(4), PRCM_WAKEUP_SRC_RST_BIT_LPUART0 = HAL_BIT(2), PRCM_WAKEUP_SRC_RST_BIT_CAPSEN = HAL_BIT(0), } PRCM_WAKEUP_SRC_RstBit; /* bit field definition of PRCM->BLE_RCOSC_CALIB_CTRL0 0x0260 */ #define PRCM_BLE_RCOSC_CALIB_EN_BIT HAL_BIT(29) #define PRCM_BLE_RCOSC_CALIB_RST_PUL_BIT HAL_BIT(28) /* write 1 to reset */ #define PRCM_RCOSC_CALIB_CS_SHIFT 24 #define PRCM_RCOSC_CALIB_CS_MASK (0x7U << PRCM_RCOSC_CALIB_CS_SHIFT) typedef enum { PRCM_RCOSC_CALIB_CS_IDLE = (0x0U << PRCM_RCOSC_CALIB_CS_SHIFT), PRCM_RCOSC_CALIB_CS_WAIT_DCXO_READY = (0x1U << PRCM_RCOSC_CALIB_CS_SHIFT), PRCM_RCOSC_CALIB_CS_WAIT_CAL_FINISH = (0x3U << PRCM_RCOSC_CALIB_CS_SHIFT), PRCM_RCOSC_CALIB_CS_CAL_FINISH = (0x6U << PRCM_RCOSC_CALIB_CS_SHIFT), PRCM_RCOSC_CALIB_CS_WAIT_TIMER = (0x2U << PRCM_RCOSC_CALIB_CS_SHIFT), } PRCM_RCOSC_CALIB_CurrentState; #define PRCM_RCOSC_CALIB_SW_REQ_PUL_BIT HAL_BIT(20) #define PRCM_RCOSC_WK_TIME_EN_BIT HAL_BIT(16) #define PRCM_RCOSC_WK_TIME_SHIFT 0 #define PRCM_RCOSC_WK_TIME_MASK (0x01FFFU << PRCM_RCOSC_WK_TIME_SHIFT) #define PRCM_RCOSC_WK_TIME_VAL(n) (n << PRCM_RCOSC_WK_TIME_SHIFT) /* bit field definition of PRCM->BLE_RCOSC_CALIB_CTRL1 0x0264 */ #define PRCM_RCOSC_SCALE_PHASE2_NUM_SHIFT 16 #define PRCM_RCOSC_SCALE_PHASE2_NUM_MASK (0x0FU << PRCM_RCOSC_SCALE_PHASE2_NUM_SHIFT) #define PRCM_RCOSC_SCALE_PHASE1_NUM_SHIFT 12 #define PRCM_RCOSC_SCALE_PHASE1_NUM_MASK (0x0FU << PRCM_RCOSC_SCALE_PHASE1_NUM_SHIFT) #define PRCM_RCOSC_SCALE_PHASE3_WK_TIMES_SHIFT 8 #define PRCM_RCOSC_SCALE_PHASE3_WK_TIMES_MASK (0x07U << PRCM_RCOSC_SCALE_PHASE3_WK_TIMES_SHIFT) typedef enum { PRCM_RCOSC_SCALE_PHASE3_WK_TIMES_10 = (0x0U << PRCM_RCOSC_SCALE_PHASE3_WK_TIMES_SHIFT), PRCM_RCOSC_SCALE_PHASE3_WK_TIMES_16 = (0x1U << PRCM_RCOSC_SCALE_PHASE3_WK_TIMES_SHIFT), PRCM_RCOSC_SCALE_PHASE3_WK_TIMES_20 = (0x2U << PRCM_RCOSC_SCALE_PHASE3_WK_TIMES_SHIFT), PRCM_RCOSC_SCALE_PHASE3_WK_TIMES_24 = (0x3U << PRCM_RCOSC_SCALE_PHASE3_WK_TIMES_SHIFT), PRCM_RCOSC_SCALE_PHASE3_WK_TIMES_32 = (0x4U << PRCM_RCOSC_SCALE_PHASE3_WK_TIMES_SHIFT), PRCM_RCOSC_SCALE_PHASE3_WK_TIMES_40 = (0x5U << PRCM_RCOSC_SCALE_PHASE3_WK_TIMES_SHIFT), PRCM_RCOSC_SCALE_PHASE3_WK_TIMES_64 = (0x6U << PRCM_RCOSC_SCALE_PHASE3_WK_TIMES_SHIFT), PRCM_RCOSC_SCALE_PHASE3_WK_TIMES_128 = (0x7U << PRCM_RCOSC_SCALE_PHASE3_WK_TIMES_SHIFT), } PRCM_RCOSC_SCALE_PHASE3_WkTimes; #define PRCM_RCOSC_SCALE_PHASE2_WK_TIMES_SHIFT 4 #define PRCM_RCOSC_SCALE_PHASE2_WK_TIMES_MASK (0x07U << PRCM_RCOSC_SCALE_PHASE2_WK_TIMES_SHIFT) typedef enum { PRCM_RCOSC_SCALE_PHASE2_WK_TIMES_2 = (0x0U << PRCM_RCOSC_SCALE_PHASE2_WK_TIMES_SHIFT), PRCM_RCOSC_SCALE_PHASE2_WK_TIMES_4 = (0x1U << PRCM_RCOSC_SCALE_PHASE2_WK_TIMES_SHIFT), PRCM_RCOSC_SCALE_PHASE2_WK_TIMES_6 = (0x2U << PRCM_RCOSC_SCALE_PHASE2_WK_TIMES_SHIFT), PRCM_RCOSC_SCALE_PHASE2_WK_TIMES_8 = (0x3U << PRCM_RCOSC_SCALE_PHASE2_WK_TIMES_SHIFT), PRCM_RCOSC_SCALE_PHASE2_WK_TIMES_10 = (0x4U << PRCM_RCOSC_SCALE_PHASE2_WK_TIMES_SHIFT), PRCM_RCOSC_SCALE_PHASE2_WK_TIMES_12 = (0x5U << PRCM_RCOSC_SCALE_PHASE2_WK_TIMES_SHIFT), PRCM_RCOSC_SCALE_PHASE2_WK_TIMES_14 = (0x6U << PRCM_RCOSC_SCALE_PHASE2_WK_TIMES_SHIFT), PRCM_RCOSC_SCALE_PHASE2_WK_TIMES_16 = (0x7U << PRCM_RCOSC_SCALE_PHASE2_WK_TIMES_SHIFT), } PRCM_RCOSC_SCALE_PHASE2_WkTimes; #define PRCM_RCOSC_NORMAL_WK_TIMES_SEL_SHIFT 1 #define PRCM_RCOSC_NORMAL_WK_TIMES_SEL_MASK (0x01U << PRCM_RCOSC_NORMAL_WK_TIMES_SEL_SHIFT) typedef enum { PRCM_RCOSC_NORMAL_WK_TIMES_SEL_PHASE2 = (0x0U << PRCM_RCOSC_NORMAL_WK_TIMES_SEL_SHIFT), PRCM_RCOSC_NORMAL_WK_TIMES_SEL_PHASE3 = (0x1U << PRCM_RCOSC_NORMAL_WK_TIMES_SEL_SHIFT), } PRCM_RCOSC_NormalWkTimesSel; #define PRCM_RCOSC_WK_MODE_SEL_SHIFT 0 #define PRCM_RCOSC_WK_MODE_SEL_MASK (0x01U << PRCM_RCOSC_WK_MODE_SEL_SHIFT) typedef enum { PRCM_RCOSC_WK_MODE_SEL_SCALE = (0x1U << PRCM_RCOSC_WK_MODE_SEL_SHIFT), PRCM_RCOSC_WK_MODE_SEL_NORMAL = (0x0U << PRCM_RCOSC_WK_MODE_SEL_SHIFT), } PRCM_RCOSC_WkModSel; /* bit field definition of PRCM->BLE_CLK32K_SWITCH0 0x0268 */ #define PRCM_BLE_CLK32K_DIV_SHIFT (16) #define PRCM_BLE_CLK32K_DIV_MASK (0x01FF << PRCM_BLE_CLK32K_DIV_SHIFT) #define PRCM_BLE_CLK32K_DIV_HALFCYCLE_32M (499) /* 32M / 32K / 2 - 1 */ #define PRCM_BLE_CLK32K_DIV_VALUE(val) (((val) << PRCM_BLE_CLK32K_DIV_SHIFT) & PRCM_BLE_CLK32K_DIV_MASK) #define PRCM_BLE_CLK32K_DIV_CLK_EN_BIT HAL_BIT(4) #define PRCM_SYS_CLK32K_RCO_CALIB_SEL_BIT HAL_BIT(3) #define PRCM_BLE_CLK32K_SEL_SHIFT (2) #define PRCM_BLE_CLK32K_SEL_MASK (0x01U << PRCM_BLE_CLK32K_SEL_SHIFT) typedef enum { PRCM_BLE_CLK32K_SEL_RCOSCORLFCLK = (0x0U << PRCM_BLE_CLK32K_SEL_SHIFT), PRCM_BLE_CLK32K_SEL_RCCAL = (0x1U << PRCM_BLE_CLK32K_SEL_SHIFT), } PRCM_BLE_CLK32K_Sel; #define PRCM_BLE_CLK32K_DIV_SRC_SEL_SHIFT (1) #define PRCM_BLE_CLK32K_DIV_SRC_SEL_MASK (0x01U << PRCM_BLE_CLK32K_DIV_SRC_SEL_SHIFT) typedef enum { PRCM_BLE_CLK32K_DIV_SRC_SEL_HFCLK = (0x0U << PRCM_BLE_CLK32K_DIV_SRC_SEL_SHIFT), PRCM_BLE_CLK32K_DIV_SRC_SEL_32M = (0x1U << PRCM_BLE_CLK32K_DIV_SRC_SEL_SHIFT), } PRCM_BLE_CLK32K_DivSrcSel; #define PRCM_BLE_CLK32K_AUTO_SW_EN_BIT HAL_BIT(0) /* bit field definition of PRCM->BLE_CLK32K_SWITCH1 0x026C */ #define PRCM_BLE_CLK32K_SW_OFFSET_DOWN_SHIFT (16) #define PRCM_BLE_CLK32K_SW_OFFSET_DOWN_VMASK (0x07FF) #define PRCM_BLE_CLK32K_SW_OFFSET_ON_SHIFT (0) #define PRCM_BLE_CLK32K_SW_OFFSET_ON_VMASK (0x07FF) #endif /* boot flag definition */ #define PRCM_BOOT_MAGIC 0xFFA55A00 #define PRCM_BOOT_MAGIC_MASK 0xFFFFFF00 #define PRCM_BOOT_VAL_MASK 0xFF #define PRCM_BOOT_VAL_INVALID 0 #define PRCM_BOOT_VAL_WDG_SYS_RST 1 #define PRCM_BOOT_VAL_WDG_CPU_RST 2 #define PRCM_BOOT_VAL_NVIC_CPU_RST 3 #define PRCM_BOOT_VAL_HIBERNATION 4 #define PRCM_BOOT_FLAG(v) (PRCM_BOOT_MAGIC | (v)) #define PRCM_BOOT_FLAG_IS_VALID(f) (((f) & PRCM_BOOT_MAGIC_MASK) == PRCM_BOOT_MAGIC) #define PRCM_BOOT_VAL(f) ((f) & PRCM_BOOT_VAL_MASK) /******************************************************************************/ uint32_t HAL_PRCM_GetTOPLDOVoltage(void); void HAL_PRCM_SetTOPLDOVoltage(PRCM_TOPLDOVolt volt); void HAL_PRCM_SetTOPLDOForceActive(uint8_t active); #if (CONFIG_CHIP_ARCH_VER == 3) uint32_t HAL_PRCM_GetSMPSVoltage(void); void HAL_PRCM_SetSMPSVoltage(PRCM_SMPSVolt volt); void HAL_PRCM_EnableSMPSPwmSel(uint32_t enable); void HAL_PRCM_SetSMPSSwTrim(uint32_t sw_trim); void HAL_PRCM_EnalbeEXTLDOSwMode(uint32_t enable); void HAL_PRCM_SetEXTLDOSwTrim(uint32_t trim); uint32_t HAL_PRCM_GetDIGLDOOffSMPSOn(void); void HAL_PRCM_SetDIGLDOOffSMPSOnActive(uint8_t active); uint32_t HAL_PRCM_GetSYSStandbySMPSOff(void); void HAL_PRCM_SetSYSStandbySMPSOffActive(uint8_t active); uint32_t HAL_PRCM_GetSMPSPwmSel(void); void HAL_PRCM_SetSMPSPwmSelActive(PRCM_SMPSPwmSel sel); uint32_t HAL_PRCM_GetOvrSMPSDetct(void); void HAL_PRCM_SetOvrSMPSDetctActive(uint8_t active); uint32_t HAL_PRCM_GetSMPSDetctValue(void); void HAL_PRCM_SetSMPSDetctValueActive(uint8_t active); uint32_t HAL_PRCM_GetSMPSDetct(void); void HAL_PRCM_SetSMPSDetctActive(uint8_t active); #endif uint32_t HAL_PRCM_GetSysPowerEnableFlags(void); #if (CONFIG_CHIP_ARCH_VER == 2) uint8_t HAL_PRCM_GetLDO1Status(void); void HAL_PRCM_SetLDO1Voltage(PRCM_LDO1Volt volt); void HAL_PRCM_SetLDO1RETVolt(PRCM_LDO1RetVolt volt); void HAL_PRCM_SetLDO1WorkVolt(PRCM_LDO1Volt volt); void HAL_PRCM_SetLDO1Volt(PRCM_LDO1Volt work_volt, PRCM_LDO1RetVolt ret_volt); void HAL_PRCM_SelectEXTLDOVolt(PRCM_EXTLDOVolt volt); #elif (CONFIG_CHIP_ARCH_VER == 3) uint8_t HAL_PRCM_GetDIGLDOStatus(void); void HAL_PRCM_SetDIGLDOVolt(PRCM_DIGLDOVolt work_volt, PRCM_DIGLDORetVolt ret_volt); uint32_t HAL_PRCM_GetEXTLDOVolt(void); void HAL_PRCM_SelectEXTLDOVolt(PRCM_EXTLDOVolt volt); #endif void HAL_PRCM_SetEXTLDOMdoe(PRCM_ExtLDOMode mode); #if (CONFIG_CHIP_ARCH_VER == 3) void HAL_PRCM_SetPLLLdoActive(uint8_t active); #endif void HAL_PRCM_SetPadClkOut(uint8_t enable); void HAL_PRCM_SetPadClkOutSource(PRCM_PadClkOutSource source); void HAL_PRCM_SetPadClkOutFactorM(uint16_t value); PRCM_LFClkSrc HAL_PRCM_GetLFClockType(PRCM_LFClkModule module); void HAL_PRCM_SetLFCLKBaseSource(PRCM_LFCLKBaseSrc src); void HAL_PRCM_SetLFCLKSource(PRCM_LFClkModule module, PRCM_LFClkSrc src); void HAL_PRCM_SetHOSCType(PRCM_HOSCType type); uint32_t HAL_PRCM_GetHOSCType(void); uint32_t HAL_PRCM_GetHFClock(void); uint32_t HAL_PRCM_GetInter32KFreq(void); uint32_t HAL_PRCM_EnableInter32KCalib(void); uint32_t HAL_PRCM_DisableInter32KCalib(void); int HAL_PRCM_IsInter32KCalibEnabled(void); uint32_t HAL_PRCM_GetBaseLFClock(void); uint32_t HAL_PRCM_GetLFClock(PRCM_LFClkModule module); void HAL_PRCM_SetSysPLL(PRCM_SysPLLParam param); void HAL_PRCM_DisableSysPLL(void); void HAL_PRCM_SetROMCycleMode(uint8_t mode); void HAL_PRCM_SetCPUAClk(PRCM_CPUClkSrc src, PRCM_SysClkFactor factor); uint32_t HAL_PRCM_GetCPUAClk(void); void HAL_PRCM_EnableCPUWClk(uint32_t enable); #if (CONFIG_CHIP_ARCH_VER == 2) void HAL_PRCM_SetAudioPLLParam(PRCM_AudPLLParam param); void HAL_PRCM_EnableAudioPLL(void); void HAL_PRCM_DisableAudioPLL(void); #elif (CONFIG_CHIP_ARCH_VER == 3) void HAL_PRCM_EnableAudioCkadcAud(void); void HAL_PRCM_DisableAudioCkadcAud(void); void HAL_PRCM_EnableAudioCkcldAud(void); void HAL_PRCM_DisableAudioCkcldAud(void); void HAL_PRCM_SetAudioCkcldParam(uint32_t n); #endif void HAL_PRCM_SetDevClock(PRCM_DevClkFactor factor); uint32_t HAL_PRCM_GetDevClock(void); #if (CONFIG_CHIP_ARCH_VER == 2) void HAL_PRCM_SetDev2Clock(PRCM_Dev2ClkFactor factor); void HAL_PRCM_EnableDev2Clock(void); void HAL_PRCM_DisableDev2Clock(void); uint32_t HAL_PRCM_GetDev2Clock(void); void HAL_PRCM_SetAudioPLLPatternParam(PRCM_AudPLLPatParam param); void HAL_PRCM_EnableAudioPLLPattern(void); void HAL_PRCM_DisableAudioPLLPattern(void); void HAL_PRCM_EnableHXTALOUT(uint8_t enable); #endif void HAL_PRCM_SetDcxoFreqTrim(uint32_t freq_trim); void HAL_PRCM_ForceSys3Reset(void); void HAL_PRCM_ReleaseSys3Reset(void); int HAL_PRCM_IsSys3Release(void); int HAL_PRCM_IsSys3Alive(void); void HAL_PRCM_SetSys1WakeupPowerFlags(uint32_t flags); uint32_t HAL_PRCM_GetSys1WakeupPowerFlags(void); uint32_t HAL_PRCM_GetSys1SleepPowerFlags(void); void HAL_PRCM_SetSys1SleepPowerFlags(uint32_t flags); uint32_t HAL_PRCM_GetSys1SramSleepPowerFlags(void); void HAL_PRCM_SetSys1SramSleepPowerFlags(uint32_t flags); void HAL_PRCM_SetBANDGAPSTABLE_TIME(uint32_t time); #if (CONFIG_CHIP_ARCH_VER == 2) void HAL_PRCM_SetRTCLDOVoltage(PRCM_RTCLDORetentionVolt retenVolt, PRCM_RTCLDOWorkVolt workVolt); #elif (CONFIG_CHIP_ARCH_VER == 3) void HAL_PRCM_SetRTCLDOVoltage(PRCM_RTCLDOVolt volt); #endif uint32_t HAL_PRCM_GetBANDGAPSTABLE_TIME(void); void HAL_PRCM_SetDCDCSTABLE_TIME(uint32_t time); uint32_t HAL_PRCM_GetDCDCSTABLE_TIME(void); void HAL_PRCM_SetLDOTOPWMSTABLE_TIME(uint32_t time); uint32_t HAL_PRCM_GetLDOTOPWMSTABLE_TIME(void); void HAL_PRCM_SetRFIPLDODIGSTABLE_TIME(uint32_t time); uint32_t HAL_PRCM_GetRFIPLDODIGSTABLE_TIME(void); void HAL_PRCM_SetLDOSTABLE_TIME(uint32_t time); uint32_t HAL_PRCM_GetLDOSTABLE_TIME(void); void HAL_PRCM_SetDCXOSTABLE_TIME(uint32_t time); uint32_t HAL_PRCM_GetDCXOSTABLE_TIME(void); void HAL_PRCM_SetDPLLSTABLE_TIME(uint32_t time); uint32_t HAL_PRCM_GetDPLLSTABLE_TIME(void); uint32_t HAL_PRCM_GetDigSWRefTime(void); #if (CONFIG_CHIP_ARCH_VER == 3) void HAL_PRCM_ReleaseBLEReset(void); void HAL_PRCM_ForceBLEReset(void); uint32_t HAL_PRCM_EnableBLE32MClk(void); uint32_t HAL_PRCM_DisableBLE32MClk(void); uint32_t HAL_PRCM_EnableBLE48MClk(void); uint32_t HAL_PRCM_DisableBLE48MClk(void); void HAL_PRCM_ReleaseRFASReset(void); void HAL_PRCM_ForceRFASReset(void); #endif void HAL_PRCM_SetCPUABootFlag(PRCM_CPUABootFlag flag); uint32_t HAL_PRCM_GetCPUABootFlag(void); void HAL_PRCM_SetCPUABootAddr(uint32_t addr); uint32_t HAL_PRCM_GetCPUABootAddr(void); void HAL_PRCM_SetCPUABootArg(uint32_t arg); uint32_t HAL_PRCM_GetCPUABootArg(void); void HAL_PRCM_SetCPUAPrivateData(uint32_t id, uint32_t data); uint32_t HAL_PRCM_GetCPUAPrivateData(uint32_t id); void HAL_PRCM_SetPrivateTime(uint64_t val); uint64_t HAL_PRCM_GetPrivateTime(void); uint32_t HAL_PRCM_GetWakeupTimerEnable(void); void HAL_PRCM_WakeupTimerEnable(void); void HAL_PRCM_WakeupTimerDisable(void); uint32_t HAL_PRCM_WakeupTimerGetCurrentValue(void); uint32_t HAL_PRCM_GetWakeupTimerPending(void); void HAL_PRCM_ClearWakeupTimerPending(void); void HAL_PRCM_WakeupTimerSetCompareValue(uint32_t val); uint32_t HAL_PRCM_WakeupTimerGetCompareValue(void); void HAL_PRCM_WakeupIOEnable(uint32_t ioMask); void HAL_PRCM_WakeupIODisable(uint32_t ioMask); #if (CONFIG_CHIP_ARCH_VER == 2) void HAL_PRCM_WakeupIOSetRisingEvent(uint32_t ioMask); void HAL_PRCM_WakeupIOSetFallingEvent(uint32_t ioMask); #elif (CONFIG_CHIP_ARCH_VER == 3) void HAL_PRCM_WakeupIOSetRisingEvent(uint32_t ioMask); void HAL_PRCM_WakeupIOSetFallingEvent(uint32_t ioMask); #endif uint32_t HAL_PRCM_WakeupIOGetEventStatus(void); int HAL_PRCM_WakeupIOIsEventDetected(uint32_t ioMask); void HAL_PRCM_WakeupIOClearEventDetected(uint32_t ioMask); void HAL_PRCM_WakeupIOEnableCfgHold(uint32_t ioMask); void HAL_PRCM_WakeupIODisableCfgHold(uint32_t ioMask); void HAL_PRCM_WakeupIOEnableGlobal(void); void HAL_PRCM_WakeupIODisableGlobal(void); void HAL_PRCM_EnableWakeupIOx(uint8_t ioIndex, uint8_t enable); #if (CONFIG_CHIP_ARCH_VER == 2) void HAL_PRCM_SetWakeupIOxDebSrc(uint8_t ioIndex, uint8_t val); void HAL_PRCM_SetWakeupDebClk0(uint8_t val); void HAL_PRCM_SetWakeupDebClk1(uint8_t val); #elif (CONFIG_CHIP_ARCH_VER == 3) void HAL_PRCM_SetWakeupIOxDebSrc(uint8_t ioIndex, uint8_t val); /** * @brief Set Wakeup Debounce CLK0/1 frequence * @param[in] clk0/1 = FCLK / (2^val), FCLK is system LFCLK, 32K or 32.768K */ void HAL_PRCM_SetWakeupDebClk0(uint8_t val); void HAL_PRCM_SetWakeupDebClk1(uint8_t val); #endif /** * @brief Set Wakeup IOx Debounce clock cycles * @param[in] Debounce clock cycles = clkx * ((val + 1) + 16), clkx is DebClk0 or DebClk1 */ void HAL_PRCM_SetWakeupIOxDebounce(uint8_t ioIndex, uint8_t val); int HAL_PRCM_IsFlashSip(void); void HAL_PRCM_SetFlashExt(uint8_t ext); #if (CONFIG_CHIP_ARCH_VER == 2) uint32_t HAL_PRCM_GetFlashSipMode(void); #endif void HAL_PRCM_EnableLDOModeSWSelEnable(uint8_t enable); uint32_t HAL_PRCM_GetResetSource(void); void HAL_PRCM_ClrResetSource(void); void HAL_PRCM_SetWdgNoResetPeriph(uint32_t periphMask, int8_t enable); void HAL_PRCM_SetDigSWRefTime(uint32_t val); void HAL_PRCM_EnableSysLDOLQModeEnable(uint8_t enable); void HAL_PRCM_EnableTOPLDOLQModeEnable(uint8_t enable); void HAL_PRCM_EnableTOPLDODeepsleep(uint8_t enable); void HAL_PRCM_EnableWlanCPUClk(uint8_t enable); void HAL_PRCM_ReleaseWlanCPUReset(void); void HAL_PRCM_ForceWlanCPUReset(void); void HAL_PRCM_WakeUpWlan(uint8_t wakeup); void HAL_PRCM_EnableWlanCPUClkOvrHIF(void); void HAL_PRCM_DisableWlanCPUClkOvrHIF(void); void HAL_PRCM_ReleaseWlanCPUOvrHIF(void); void HAL_PRCM_ResetWlanCPUOvrHIF(void); void HAL_PRCM_EnableWlanWUPOvrHIF(void); void HAL_PRCM_DisableWlanWUPOvrHIF(void); void HAL_PRCM_EnableWlanIRQOvrHIF(void); void HAL_PRCM_DisableWlanIRQOvrHIF(void); #if (CONFIG_CHIP_ARCH_VER == 3) void HAL_PRCM_SetWlanSramShare(PRCM_WLAN_ShareSramType type); void HAL_PRCM_SetBLESramShare(uint32_t en); void HAL_PRCM_EnableLpuart0Clk(void); void HAL_PRCM_DisableLpuart0Clk(void); void HAL_PRCM_SelectLpuart0WakeupIOIn(PRCM_LPUART_WAKEUP_IN_SEL in); void HAL_PRCM_SelectLpuart0ClkSource(PRCM_LPUART_ClkSource sel); void HAL_PRCM_EnableLpuart1Clk(void); void HAL_PRCM_DisableLpuart1Clk(void); void HAL_PRCM_SelectLpuart1WakeupIOIn(PRCM_LPUART_WAKEUP_IN_SEL in); void HAL_PRCM_SelectLpuart1ClkSource(PRCM_LPUART_ClkSource sel); void HAL_PRCM_GPADC_EnableMClock(void); void HAL_PRCM_GPADC_DisableMClock(void); uint32_t HAL_PRCM_GPADC_GetMClock(void); void HAL_PRCM_SelectGpadcClkSource(PRCM_GPADC_MClkSource sel); void HAL_PRCM_SetGpadcClock(PRCM_GPADC_ClkFactorN factorN, uint16_t factorM); void HAL_PRCM_WAKEUP_SRC_EnableClkGating(PRCM_WAKEUP_SRC_BusClkBit periphMask); void HAL_PRCM_WAKEUP_SRC_DisableClkGating(PRCM_WAKEUP_SRC_BusClkBit periphMask); void HAL_PRCM_ReleaseWakeupSrcReset(PRCM_WAKEUP_SRC_RstBit periphMask); void HAL_PRCM_ForceWakeupSrcReset(PRCM_WAKEUP_SRC_RstBit periphMask); uint32_t HAL_PRCM_GetLpuartMClock(void); void HAL_PRCM_SetFlashCryptoNonce(uint8_t *nonce); uint32_t HAL_PRCM_GetBLERstStatus(void); void HAL_PRCM_SetCLK32kDiv(uint32_t en, PRCM_BLE_CLK32K_DivSrcSel sel); void HAL_PRCM_SetCLK32kAutoSw(uint32_t en); void HAL_PRCM_SetRcoCalib(uint32_t en, PRCM_RCOSC_WkModSel mode, PRCM_RCOSC_NormalWkTimesSel sel, uint32_t phase, uint32_t wk_time_en, uint32_t wk_time); void HAL_PRCM_SetRcoscCalStartSrc(PRCM_RcoscCalStartSrc src); PRCM_RcoscCalStartSrc HAL_PRCM_GetRcoscCalStartSrc(void); void HAL_PRCM_SetBLEClk32KSel(PRCM_BLE_CLK32K_Sel sel); PRCM_BLE_CLK32K_Sel HAL_PRCM_GetBLEClk32KSel(void); uint32_t HAL_PRCM_GetRcoscCalSwitchLoseClk(void); void HAL_PRCM_SetCLK32KSwitchRCCal(uint8_t enable); void HAL_PRCM_DisableVddioSipSw(void); void HAL_PRCM_EnableVddioSipSw(void); int HAL_PRCM_IsVddioSipSwEnable(void); void HAL_PRCM_SetBgTrim(uint32_t bg_trim); #endif #ifdef __cplusplus } #endif #endif /* _DRIVER_CHIP_HAL_PRCM_H_ */