48 lines
1.4 KiB
C
48 lines
1.4 KiB
C
/*
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* ===========================================================================================
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*
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* Filename: barrier.h
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*
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* Description: barrier impl. of riscv
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*
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* Version: Melis3.0
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* Create: 2020-07-08 14:35:53
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* Revision: none
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* Compiler: GCC:version 7.2.1 20170904 (release),ARM/embedded-7-branch revision 255204
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*
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* Author: caozilong@allwinnertech.com
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* Organization: BU1-PSW
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* Last Modified: 2020-09-28 11:12:43
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*
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* ===========================================================================================
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*/
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#ifndef _ASM_RISCV_BARRIER_H
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#define _ASM_RISCV_BARRIER_H
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#ifndef __ASSEMBLY__
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#define nop() __asm__ __volatile__ ("nop")
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#define RISCV_FENCE(p, s) \
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__asm__ __volatile__ ("fence " #p "," #s : : : "memory")
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/* These barriers need to enforce ordering on both devices or memory. */
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#define mb() RISCV_FENCE(iorw,iorw)
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#define rmb() RISCV_FENCE(ir,ir)
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#define wmb() RISCV_FENCE(ow,ow)
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/* These barriers do not need to enforce ordering on devices, just memory. */
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#define __smp_mb() RISCV_FENCE(rw,rw)
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#define __smp_rmb() RISCV_FENCE(r,r)
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#define __smp_wmb() RISCV_FENCE(w,w)
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#define dmb(...) mb();
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#define dsb(...) mb();
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#define isb(...) do { __asm__ __volatile__ ("fence.i \n": : : "memory"); } while(0)
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#define barrier() __asm__ __volatile__("": : :"memory")
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#endif
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#endif
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