101 lines
3.5 KiB
C
101 lines
3.5 KiB
C
/*
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* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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*
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* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
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* the the People's Republic of China and other countries.
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* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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*
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* DISCLAIMER
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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* IF YOU NEED TO INTEGRATE THIRD PARTY'S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* IN ALLWINNERS'SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
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* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY'S TECHNOLOGY.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
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* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DMA_SUN20IW3_H__
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#define __DMA_SUN20IW3_H__
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#define SUNXI_DMAC_PBASE (0x03002000ul)
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#define DMA_IRQ_NUM (66) /* DMA 8~15 channel irq non-secure */
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#define NR_MAX_CHAN 16 /* total of channels */
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#define START_CHAN_OFFSET 0
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#define SUNXI_CLK_DMA HAL_CLK_PERIPH_DMA
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#define SUNXI_RST_DMA 0
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#define SUNXI_CLK_MBUS_DMA 0
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/*
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* The source DRQ type and port corresponding relation
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*/
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#define DRQSRC_SRAM 0
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#define DRQSRC_SDRAM 1
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#define DRQSRC_I2S0_RX 3
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#define DRQSRC_I2S1_RX 4
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#define DRQSRC_AUDIO_CODEC 7
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#define DRQSRC_DMIC 8
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#define DRQSRC_GPADC 12
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#define DRQSRC_UART0_RX 14
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#define DRQSRC_UART1_RX 15
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#define DRQSRC_UART2_RX 16
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#define DRQSRC_UART3_RX 17
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#define DRQSRC_SPI0_RX 22
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#define DRQSRC_SPI1_RX 23
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#define DRQSRC_SPI2_RX 24
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#define DRQSRC_SPI3_RX 25
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#define DRQSRC_OTG_EP1 30
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#define DRQSRC_OTG_EP2 31
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#define DRQSRC_OTG_EP3 32
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#define DRQSRC_OTG_EP4 33
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#define DRQSRC_OTG_EP5 34
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#define DRQSRC_TWI0_RX 43
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#define DRQSRC_TWI1_RX 44
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#define DRQSRC_TWI2_RX 45
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#define DRQSRC_TWI3_RX 46
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#define DRQSRC_TWI4_RX 47
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/*
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* The destination DRQ type and port corresponding relation
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*/
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#define DRQDST_SRAM 0
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#define DRQDST_SDRAM 1
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#define DRQDST_I2S0_TX 3
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#define DRQDST_I2S1_TX 4
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#define DRQDST_AUDIO_CODEC 7
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#define DRQDST_UART0_TX 14
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#define DRQDST_UART1_TX 15
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#define DRQDST_UART2_TX 16
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#define DRQDST_UART3_TX 17
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#define DRQDST_SPI0_TX 22
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#define DRQDST_SPI1_TX 23
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#define DRQDST_SPI2_TX 24
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#define DRQDST_SPI3_TX 25
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#define DRQDST_OTG_EP1 30
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#define DRQDST_OTG_EP2 31
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#define DRQDST_OTG_EP3 32
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#define DRQDST_OTG_EP4 33
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#define DRQDST_OTG_EP5 34
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#define DRQDST_TWI0_TX 43
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#define DRQDST_TWI1_TX 44
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#define DRQDST_TWI2_TX 45
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#define DRQDST_TWI3_TX 46
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#define DRQDST_TWI4_TX 47
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#endif /*__DMA_SUN20IW3_H__ */
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