194 lines
6.7 KiB
C
Executable File
194 lines
6.7 KiB
C
Executable File
/*
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* top_reg_i.h
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*
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* Copyright (c) 2017 by Allwinnertech Co., Ltd. http://www.allwinnertech.com
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*
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* Authors: Zhao Wei <zhaowei@allwinnertech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __CSIC__TOP__REG__I__H__
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#define __CSIC__TOP__REG__I__H__
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/*
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* Detail information of registers
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*/
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#define CSIC_TOP_EN_REG_OFF 0X000
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#define CSIC_TOP_EN 0
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#define CSIC_TOP_EN_MASK (0X1 << CSIC_TOP_EN)
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#define CSIC_BIST_MODE_EN 2
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#define CSIC_BIST_MODE_EN_MASK (0X1 << CSIC_BIST_MODE_EN)
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#define CSIC_ISP_BRIDGE_EN 3
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#define CSIC_ISP_BRIDGE_EN_MASK (0X1 << CSIC_ISP_BRIDGE_EN)
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#define CSIC_SRAM_PWDN 8
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#define CSIC_SRAM_PWDN_MASK (0X1 << CSIC_SRAM_PWDN)
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#define CSIC_VER_EN 31
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#define CSIC_VER_EN_MASK (0X1 << CSIC_VER_EN)
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#define CSIC_PTN_GEN_EN_REG_OFF 0X004
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#define CSIC_PTN_GEN_EN 0
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#define CSIC_PTN_GEN_EN_MASK (0X1 << CSIC_PTN_GEN_EN)
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#define CSIC_PTN_GEN_START 4
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#define CSIC_PTN_GEN_START_MASK (0X1 << CSIC_PTN_GEN_START)
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#define CSIC_PTN_GEN_CYCLE 16
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#define CSIC_PTN_GEN_CYCLE_MASK (0XFF << CSIC_PTN_GEN_CYCLE)
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#define CSIC_PTN_CTRL_REG_OFF 0X008
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#define CSIC_PTN_CLK_DIV 8
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#define CSIC_PTN_CLK_DIV_MASK (0X3 << CSIC_PTN_CLK_DIV)
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#define CSIC_PTN_MODE 16
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#define CSIC_PTN_MODE_MASK (0XF << CSIC_PTN_MODE)
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#define CSIC_PTN_DATA_WIDTH 20
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#define CSIC_PTN_DATA_WIDTH_MASK (0X3 << CSIC_PTN_DATA_WIDTH)
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#define CSIC_PTN_PORT_SEL 24
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#define CSIC_PTN_PORT_SEL_MASK (0X7 << CSIC_PTN_PORT_SEL)
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#define CSIC_PTN_LEN_REG_OFF 0X020
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#define CSIC_PTN_ADDR_REG_OFF 0X024
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#define CSIC_PTN_SIZE_REG_OFF 0X028
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#define CSIC_PTN_WIDTH 0
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#define CSIC_PTN_WIDTH_MASK (0X1FFF << CSIC_PTN_WIDTH)
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#define CSIC_PTN_HEIGHT 16
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#define CSIC_PTN_HEIGHT_MASK (0X1FFF << CSIC_PTN_HEIGHT)
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#if defined(CONFIG_ARCH_SUN50IW3P1) || defined(CONFIG_ARCH_SUN50IW6P1)
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#define CSIC_ISP0_IN0_REG_OFF 0X030
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#define CSIC_ISP0_IN1_REG_OFF 0X034
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#define CSIC_ISP0_IN2_REG_OFF 0X038
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#define CSIC_ISP0_IN3_REG_OFF 0X03C
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#define CSIC_ISP1_IN0_REG_OFF 0X040
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#define CSIC_ISP1_IN1_REG_OFF 0X044
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#define CSIC_ISP1_IN2_REG_OFF 0X048
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#define CSIC_ISP1_IN3_REG_OFF 0X04C
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#define CSIC_VIPP0_IN_REG_OFF 0X060
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#define CSIC_VIPP1_IN_REG_OFF 0X064
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#define CSIC_VIPP2_IN_REG_OFF 0X068
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#define CSIC_VIPP3_IN_REG_OFF 0X06C
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#define CSIC_FEATURE_REG_OFF 0X070
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#define CSIC_VER_REG_OFF 0X074
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#else
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#define CSIC_ISP0_IN0_REG_OFF 0X030
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#define CSIC_ISP0_IN1_REG_OFF 0X034
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#define CSIC_ISP0_IN2_REG_OFF 0X038
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#define CSIC_ISP0_IN3_REG_OFF 0X03C
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#define CSIC_ISP1_IN0_REG_OFF 0X040
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#define CSIC_ISP1_IN1_REG_OFF 0X044
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#define CSIC_ISP1_IN2_REG_OFF 0X048
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#define CSIC_ISP1_IN3_REG_OFF 0X04C
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#define CSIC_ISP2_IN0_REG_OFF 0X050
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#define CSIC_ISP2_IN1_REG_OFF 0X054
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#define CSIC_ISP2_IN2_REG_OFF 0X058
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#define CSIC_ISP2_IN3_REG_OFF 0X05C
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#define CSIC_ISP3_IN0_REG_OFF 0X060
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#define CSIC_ISP3_IN1_REG_OFF 0X064
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#define CSIC_ISP3_IN2_REG_OFF 0X068
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#define CSIC_ISP3_IN3_REG_OFF 0X06C
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#define CSIC_VIPP0_IN_REG_OFF 0X0A0
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#define CSIC_VIPP1_IN_REG_OFF 0X0A4
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#define CSIC_VIPP2_IN_REG_OFF 0X0A8
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#define CSIC_VIPP3_IN_REG_OFF 0X0AC
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#define CSIC_VIPP4_IN_REG_OFF 0X0B0
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#define CSIC_VIPP5_IN_REG_OFF 0X0B4
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#define CSIC_VIPP6_IN_REG_OFF 0X0B8
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#define CSIC_VIPP7_IN_REG_OFF 0X0BC
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#if defined CONFIG_ARCH_SUN8IW15P1 || defined CONFIG_ARCH_SUN8IW16P1 || defined CONFIG_ARCH_SUN8IW17P1 || defined CONFIG_ARCH_SUN50IW9P1
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#define CSIC_FEATURE_REG_OFF 0X0F0
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#define CSIC_VER_REG_OFF 0X0F4
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#else
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#define CSIC_MBUS_REQ_MAX 0x0F0
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#define MCSI_MEM_REQ_MAX 0
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#define MCSI_MEM_REQ_MAX_MASK (0X1F << MCSI_MEM_REQ_MAX)
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#define MCSI_MEM_1_REQ_MAX 8
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#define MCSI_MEM_1_REQ_MAX_MASK (0X1F << MCSI_MEM_1_REQ_MAX)
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#define MISP_MEM_REQ_MAX 16
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#define MISP_MEM_REQ_MAX_MASK (0X1F << MISP_MEM_REQ_MAX)
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#define CSIC_FEATURE_REG_OFF 0X1F0
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#define CSIC_VER_REG_OFF 0X1F4
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#endif
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#endif
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#define CSIC_FEATURE_RES0 0
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#define CSIC_FEATURE_RES0_MASK (0XFF << CSIC_FEATURE_RES0)
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#define CSIC_DMA_NUM 8
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#define CSIC_DMA_NUM_MASK (0XF << CSIC_DMA_NUM)
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#define CSIC_VIPP_NUM 12
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#define CSIC_VIPP_NUM_MASK (0XF << CSIC_VIPP_NUM)
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#define CSIC_ISP_NUM 16
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#define CSIC_ISP_NUM_MASK (0XF << CSIC_ISP_NUM)
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#define CSIC_NCSI_NUM 20
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#define CSIC_NCSI_NUM_MASK (0XF << CSIC_NCSI_NUM)
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#define CSIC_MCSI_NUM 24
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#define CSIC_MCSI_NUM_MASK (0XF << CSIC_MCSI_NUM)
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#define CSIC_PARSER_NUM 28
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#define CSIC_PARSER_NUM_MASK (0XF << CSIC_PARSER_NUM)
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#define CSIC_VER_SMALL 0
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#define CSIC_VER_SMALL_MASK (0XFFF << CSIC_VER_SMALL)
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#define CSIC_VER_BIG 12
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#define CSIC_VER_BIG_MASK (0XFFF << CSIC_VER_BIG)
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/*
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*CSIC CCU registers
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*/
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#define CSIC_CCU_MODE_REG_OFF 0x000
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#define CSIC_MCSI_CLK_MODE 0
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#define CSIC_MCSI_CLK_MODE_MASK (0X1 << CSIC_MCSI_CLK_MODE)
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#define CSIC_MCSI_POST_CLK_MODE 1
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#define CSIC_MCSI_POST_CLK_MODE_MASK (0X1 << CSIC_MCSI_POST_CLK_MODE)
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#define CSIC_CCU_CLK_GATING_DISABLE 31
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#define CSIC_CCU_CLK_GATING_DISABLE_MASK (0X1 << CSIC_CCU_CLK_GATING_DISABLE)
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#define CSIC_CCU_PARSER_CLK_EN_REG_OFF 0x004
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#define CSIC_MCSI_PARSER0_CLK_EN 0
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#define CSIC_MCSI_PARSER0_CLK_EN_MASK (0X1 << CSIC_MCSI_PARSER0_CLK_EN)
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#define CSIC_MCSI_PARSER1_CLK_EN 1
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#define CSIC_MCSI_PARSER1_CLK_EN_MASK (0X1 << CSIC_MCSI_PARSER1_CLK_EN)
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#define CSIC_MCSI_COMBO0_CLK_EN 8
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#define CSIC_MCSI_COMBO0_CLK_EN_MASK (0X1 << CSIC_MCSI_COMBO0_CLK_EN)
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#define CSIC_MCSI_MIPI0_CLK_EN 16
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#define CSIC_MCSI_MIPI0_CLK_EN_MASK (0X1 << CSIC_MCSI_MIPI0_CLK_EN)
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#define CSIC_CCU_ISP_CLK_EN_REG_OFF 0x008
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#define CSIC_MISP0_CLK_EN 0
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#define CSIC_MISP0_CLK_EN_MASK (0X1 << CSIC_MISP0_CLK_EN)
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#define CSIC_MISP0_BRIDGE_CLK_EN 4
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#define CSIC_MISP0_BRIDGE_CLK_EN_MASK (0X1 << CSIC_MISP0_BRIDGE_CLK_EN)
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#define CSIC_CCU_POST0_CLK_EN_REG_OFF 0x00c
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#define CSIC_MCSI_BK0_CLK_EN 0
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#define CSIC_MCSI_BK0_CLK_EN_MASK (0X1 << CSIC_MCSI_BK0_CLK_EN)
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#define CSIC_MCSI_BK1_CLK_EN 1
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#define CSIC_MCSI_BK1_CLK_EN_MASK (0X1 << CSIC_MCSI_BK1_CLK_EN)
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#define CSIC_MCSI_BK2_CLK_EN 2
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#define CSIC_MCSI_BK2_CLK_EN_MASK (0X1 << CSIC_MCSI_BK2_CLK_EN)
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#define CSIC_MCSI_BK3_CLK_EN 3
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#define CSIC_MCSI_BK3_CLK_EN_MASK (0X1 << CSIC_MCSI_BK3_CLK_EN)
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#define CSIC_MCSI_VIPP0_CLK_EN 8
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#define CSIC_MCSI_VIPP0_CLK_EN_MASK (0X1 << CSIC_MCSI_VIPP0_CLK_EN)
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#define CSIC_MCSI_VIPP1_CLK_EN 9
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#define CSIC_MCSI_VIPP1_CLK_EN_MASK (0X1 << CSIC_MCSI_VIPP1_CLK_EN)
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#define CSIC_MCSI_VIPP2_CLK_EN 10
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#define CSIC_MCSI_VIPP2_CLK_EN_MASK (0X1 << CSIC_MCSI_VIPP2_CLK_EN)
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#define CSIC_MCSI_VIPP3_CLK_EN 11
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#define CSIC_MCSI_VIPP3_CLK_EN_MASK (0X1 << CSIC_MCSI_VIPP3_CLK_EN)
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#define CSIC_MCSI_POST0_CLK_EN 16
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#define CSIC_MCSI_POST0_CLK_EN_MASK (0X1 << CSIC_MCSI_POST0_CLK_EN)
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#endif /*__CSIC__TOP__REG__I__H__*/
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