1119 lines
35 KiB
C
1119 lines
35 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2008,2010 Freescale Semiconductor, Inc
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* Andy Fleming
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*
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* Based (loosely) on the Linux code
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*/
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#ifndef _MMC_H_
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#define _MMC_H_
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#include <linux/list.h>
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#include <linux/sizes.h>
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#include <linux/compiler.h>
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#include <part.h>
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#include <config.h>
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#include <clk/clk.h>
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#include <linux/err.h>
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#define CONFIG_MMC_SUNXI_USE_DMA
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#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
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#define MMC_SUPPORTS_TUNING
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#endif
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#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
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#define MMC_SUPPORTS_TUNING
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#endif
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/* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
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#define SD_VERSION_SD (1U << 31)
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#define MMC_VERSION_MMC (1U << 30)
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#define MAKE_SDMMC_VERSION(a, b, c) \
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((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
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#define MAKE_SD_VERSION(a, b, c) \
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(SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
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#define MAKE_MMC_VERSION(a, b, c) \
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(MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
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#define EXTRACT_SDMMC_MAJOR_VERSION(x) \
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(((u32)(x) >> 16) & 0xff)
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#define EXTRACT_SDMMC_MINOR_VERSION(x) \
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(((u32)(x) >> 8) & 0xff)
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#define EXTRACT_SDMMC_CHANGE_VERSION(x) \
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((u32)(x) & 0xff)
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#define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
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#define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
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#define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
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#define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
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#define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
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#define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
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#define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
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#define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
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#define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
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#define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
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#define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
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#define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
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#define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
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#define MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0)
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#define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
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#define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
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#define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
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#define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
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#define MMC_CAP(mode) (1 << mode)
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#define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
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#define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52)
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#define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
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#define MMC_MODE_HS200 MMC_CAP(MMC_HS_200)
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#define MMC_MODE_HS400 MMC_CAP(MMC_HS_400)
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#define MMC_MODE_8BIT BIT(30)
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#define MMC_MODE_4BIT BIT(29)
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#define MMC_MODE_1BIT BIT(28)
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#define MMC_MODE_SPI BIT(27)
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#define SD_DATA_4BIT 0x00040000
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#define IS_SD(x) ((x)->version & SD_VERSION_SD)
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#define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
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#define MMC_CMD_MANUAL 1//add by sunxi.not sent stop when read/write multi block,and sent stop when sent cmd12
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#define MMC_DATA_READ 1
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#define MMC_DATA_WRITE 2
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#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
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#define UNUSABLE_ERR -17 /* Unusable Card */
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#define COMM_ERR -18 /* Communications Error */
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#define TIMEOUT -19
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#define IN_PROGRESS -20 /* operation is in progress */
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#define SWITCH_ERR -21 /* Card reports failure to switch mode */
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#define MMC_CMD_GO_IDLE_STATE 0
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#define MMC_CMD_SEND_OP_COND 1
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#define MMC_CMD_ALL_SEND_CID 2
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#define MMC_CMD_SET_RELATIVE_ADDR 3
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#define MMC_CMD_SET_DSR 4
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#define MMC_CMD_SWITCH 6
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#define MMC_CMD_SELECT_CARD 7
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#define MMC_CMD_SEND_EXT_CSD 8
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#define MMC_CMD_SEND_CSD 9
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#define MMC_CMD_SEND_CID 10
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#define MMC_CMD_STOP_TRANSMISSION 12
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#define MMC_CMD_SEND_STATUS 13
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#define MMC_CMD_SET_BLOCKLEN 16
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#define MMC_CMD_READ_SINGLE_BLOCK 17
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#define MMC_CMD_READ_MULTIPLE_BLOCK 18
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#define MMC_CMD_SEND_TUNING_BLOCK 19
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#define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
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#define MMC_CMD_SET_BLOCK_COUNT 23
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#define MMC_CMD_WRITE_SINGLE_BLOCK 24
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#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
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#define MMC_CMD_SET_WRITE_PROT 28
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#define MMC_CMD_CLR_WRITE_PROT 29
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#define MMC_CMD_SEND_WRITE_PROT 30
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#define MMC_CMD_SEND_WRITE_PROT_TYPE 31
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#define MMC_CMD_ERASE_GROUP_START 35
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#define MMC_CMD_ERASE_GROUP_END 36
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#define MMC_CMD_ERASE 38
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#define MMC_CMD_APP_CMD 55
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#define MMC_CMD_SPI_READ_OCR 58
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#define MMC_CMD_SPI_CRC_ON_OFF 59
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#define MMC_CMD_RES_MAN 62
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#define MMC_CMD62_ARG1 0xefac62ec
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#define MMC_CMD62_ARG2 0xcbaea7
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#define SD_CMD_SEND_RELATIVE_ADDR 3
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#define SD_CMD_SWITCH_FUNC 6
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#define SD_CMD_SEND_IF_COND 8
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#define SD_CMD_SWITCH_UHS18V 11
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#define SD_CMD_APP_SET_BUS_WIDTH 6
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#define SD_CMD_APP_SD_STATUS 13
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#define SD_CMD_ERASE_WR_BLK_START 32
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#define SD_CMD_ERASE_WR_BLK_END 33
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#define SD_CMD_APP_SEND_OP_COND 41
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#define SD_CMD_APP_SEND_SCR 51
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static inline bool mmc_is_tuning_cmd(uint cmdidx)
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{
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if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
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(cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
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return true;
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return false;
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}
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/* SCR definitions in different words */
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#define SD_HIGHSPEED_BUSY 0x00020000
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#define SD_HIGHSPEED_SUPPORTED 0x00020000
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#define UHS_SDR12_BUS_SPEED 0
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#define HIGH_SPEED_BUS_SPEED 1
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#define UHS_SDR25_BUS_SPEED 1
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#define UHS_SDR50_BUS_SPEED 2
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#define UHS_SDR104_BUS_SPEED 3
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#define UHS_DDR50_BUS_SPEED 4
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#define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED)
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#define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED)
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#define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED)
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#define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED)
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#define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED)
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#define OCR_BUSY 0x80000000
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#define OCR_HCS 0x40000000
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#define OCR_S18R 0x1000000
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#define OCR_VOLTAGE_MASK 0x007FFF80
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#define OCR_ACCESS_MODE 0x60000000
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#define MMC_ERASE_ARG 0x00000000
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#define MMC_SECURE_ERASE_ARG 0x80000000
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#define MMC_TRIM_ARG 0x00000001
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#define MMC_DISCARD_ARG 0x00000003
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#define MMC_SECURE_TRIM1_ARG 0x80000001
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#define MMC_SECURE_TRIM2_ARG 0x80008000
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#define MMC_STATUS_MASK (~0x0206BF7F)
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#define MMC_STATUS_SWITCH_ERROR (1 << 7)
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#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
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#define MMC_STATUS_CURR_STATE (0xf << 9)
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#define MMC_STATUS_ERROR (1 << 19)
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#define MMC_STATE_PRG (7 << 9)
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#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
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#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
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#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
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#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
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#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
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#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
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#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
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#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
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#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
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#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
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#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
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#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
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#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
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#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
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#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
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#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
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#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
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#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
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#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
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addressed by index which are
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1 in value field */
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#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
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addressed by index, which are
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1 in value field */
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#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
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#define SD_SWITCH_CHECK 0
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#define SD_SWITCH_SWITCH 1
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/*
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* EXT_CSD fields
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*/
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#define EXT_CSD_FFU_STATUS 26 /* RO */
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#define EXT_CSD_MODE_CONFIG 30 /* R/W/E_P */
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#define EXT_CSD_ENH_START_ADDR 136 /* R/W */
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#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
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#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
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#define EXT_CSD_PARTITION_SETTING 155 /* R/W */
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#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
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#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
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#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
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#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
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#define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
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#define EXT_CSD_SANITIZE_START 165 /* W */
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#define EXT_CSD_WR_REL_PARAM 166 /* R */
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#define EXT_CSD_WR_REL_SET 167 /* R/W */
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#define EXT_CSD_RPMB_MULT 168 /* RO */
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#define EXT_CSD_FW_CONFIG 169 /* R/W */
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#define EXT_CSD_USER_WP 171 /* R/W */
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#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
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#define EXT_CSD_BOOT_BUS_WIDTH 177
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#define EXT_CSD_PART_CONF 179 /* R/W */
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#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
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#define EXT_CSD_BUS_WIDTH 183 /* R/W */
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#define EXT_CSD_HS_TIMING 185 /* R/W */
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#define EXT_CSD_REV 192 /* RO */
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#define EXT_CSD_STRUCTURE 194 /* RO */
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#define EXT_CSD_CARD_TYPE 196 /* RO */
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#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
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#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
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#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
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#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
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#define EXT_CSD_BOOT_MULT 226 /* RO */
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#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
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#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
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#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
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#define EXT_CSD_TRIM_MULT 232 /* RO */
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#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */
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#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
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#define EXT_CSD_SUPPORTED_MODES 493 /* RO */
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#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
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/*
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* EXT_CSD field definitions
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*/
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#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
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#define EXT_CSD_CMD_SET_SECURE (1 << 1)
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#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
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#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
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#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
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#define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_26 | \
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+ EXT_CSD_CARD_TYPE_52)
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#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
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#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
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#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
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| EXT_CSD_CARD_TYPE_DDR_1_2V)
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#define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
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/* SDR mode @1.8V I/O */
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#define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
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/* SDR mode @1.2V I/O */
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#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
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EXT_CSD_CARD_TYPE_HS200_1_2V)
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#define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */
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#define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.8V */
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#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
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EXT_CSD_CARD_TYPE_HS400_1_2V)
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/* -- EXT_CSD[171] USER_WP */
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#define MMC_SWITCH_USER_WP_PERM_PSWD_DIS (0x1 << 7)
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#define MMC_SWITCH_USER_WP_CD_PERM_WP_DIS (0x1 << 6)
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#define MMC_SWITCH_USER_WP_US_PERM_WP_DIS (0x1 << 4)
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#define MMC_SWITCH_USER_WP_US_PWR_WP_DIS (0x1 << 3)
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#define MMC_SWITCH_USER_WP_US_PERM_WP_EN (0x1 << 2)
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#define MMC_SWITCH_USER_WP_US_PWR_WP_EN (0x1 << 0)
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/* -- EXT_CSD[183] BUS_WIDTH */
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#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
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#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
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#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
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#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
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#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
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#define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
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/* -- EXT_CSD[185] HS_TIMING */
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#define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
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#define EXT_CSD_TIMING_HS 1 /* HS */
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#define EXT_CSD_TIMING_HS200 2 /* HS200 */
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#define EXT_CSD_TIMING_HS400 3 /* HS400 */
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/* -- EXT_CSD[231] SEC_FEATURE_SUPPORT */
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#define EXT_CSD_SEC_ER_EN (1U << 0)
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#define EXT_CSD_SEC_BD_BLK_EN (1U << 2)
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#define EXT_CSD_SEC_GB_CL_EN (1U << 4)
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#define EXT_CSD_SEC_SANITIZE (1U << 6) /* v4.5 only */
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#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
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#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
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#define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
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#define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
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#define EXT_CSD_BOOT_ACK(x) (x << 6)
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#define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
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#define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
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#define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1)
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#define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7)
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#define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7)
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#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
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#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
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#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
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#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
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#define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
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#define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
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#define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
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#define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
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#define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
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#define R1_ILLEGAL_COMMAND (1 << 22)
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#define R1_APP_CMD (1 << 5)
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#define MMC_RSP_PRESENT (1 << 0)
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#define MMC_RSP_136 (1 << 1) /* 136 bit response */
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#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
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#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
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#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
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#define MMC_RSP_NONE (0)
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#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
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#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
|
|
MMC_RSP_BUSY)
|
|
#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
|
|
#define MMC_RSP_R3 (MMC_RSP_PRESENT)
|
|
#define MMC_RSP_R4 (MMC_RSP_PRESENT)
|
|
#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
|
#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
|
#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
|
|
|
#define MMCPART_NOAVAILABLE (0xff)
|
|
#define PART_ACCESS_MASK (0x7)
|
|
#define PART_SUPPORT (0x1)
|
|
#define ENHNCD_SUPPORT (0x2)
|
|
#define PART_ENH_ATTRIB (0x1f)
|
|
|
|
#define MMC_QUIRK_RETRY_SEND_CID BIT(0)
|
|
#define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1)
|
|
|
|
enum mmc_voltage {
|
|
MMC_SIGNAL_VOLTAGE_000 = 0,
|
|
MMC_SIGNAL_VOLTAGE_120 = 1,
|
|
MMC_SIGNAL_VOLTAGE_180 = 2,
|
|
MMC_SIGNAL_VOLTAGE_330 = 4,
|
|
};
|
|
|
|
#define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
|
|
MMC_SIGNAL_VOLTAGE_180 |\
|
|
MMC_SIGNAL_VOLTAGE_330)
|
|
|
|
/* Maximum block size for MMC */
|
|
#define MMC_MAX_BLOCK_LEN 512
|
|
|
|
/* Maximum dts string for MMC */
|
|
#define MMC_MAX_DTS_STRING_LEN 50
|
|
/* Maximum dts string for MMC */
|
|
#define MMC_MAX_PLL_STRING_LEN 32
|
|
|
|
/* The number of MMC physical partitions. These consist of:
|
|
* boot partitions (2), general purpose partitions (4) in MMC v4.4.
|
|
*/
|
|
#define MMC_NUM_BOOT_PARTITION 2
|
|
#define MMC_PART_RPMB 3 /* RPMB partition number */
|
|
|
|
/* Driver model support */
|
|
|
|
/**
|
|
* struct mmc_uclass_priv - Holds information about a device used by the uclass
|
|
*/
|
|
struct mmc_uclass_priv {
|
|
struct mmc *mmc;
|
|
};
|
|
|
|
/**
|
|
* mmc_get_mmc_dev() - get the MMC struct pointer for a device
|
|
*
|
|
* Provided that the device is already probed and ready for use, this value
|
|
* will be available.
|
|
*
|
|
* @dev: Device
|
|
* @return associated mmc struct pointer if available, else NULL
|
|
*/
|
|
struct mmc *mmc_get_mmc_dev(struct udevice *dev);
|
|
|
|
/* End of driver model support */
|
|
|
|
struct mmc_cid {
|
|
unsigned long psn;
|
|
unsigned short oid;
|
|
unsigned char mid;
|
|
unsigned char prv;
|
|
unsigned char mdt;
|
|
char pnm[7];
|
|
};
|
|
|
|
struct mmc_cmd {
|
|
ushort cmdidx;
|
|
uint resp_type;
|
|
uint cmdarg;
|
|
uint response[4];
|
|
};
|
|
|
|
struct mmc_data {
|
|
union {
|
|
char *dest;
|
|
const char *src; /* src buffers don't get written to */
|
|
};
|
|
uint flags;
|
|
uint blocks;
|
|
uint blocksize;
|
|
};
|
|
|
|
/* forward decl. */
|
|
struct mmc;
|
|
|
|
#if CONFIG_IS_ENABLED(DM_MMC)
|
|
struct dm_mmc_ops {
|
|
/**
|
|
* send_cmd() - Send a command to the MMC device
|
|
*
|
|
* @dev: Device to receive the command
|
|
* @cmd: Command to send
|
|
* @data: Additional data to send/receive
|
|
* @return 0 if OK, -ve on error
|
|
*/
|
|
int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
|
|
struct mmc_data *data);
|
|
|
|
/**
|
|
* set_ios() - Set the I/O speed/width for an MMC device
|
|
*
|
|
* @dev: Device to update
|
|
* @return 0 if OK, -ve on error
|
|
*/
|
|
int (*set_ios)(struct udevice *dev);
|
|
|
|
/**
|
|
* send_init_stream() - send the initialization stream: 74 clock cycles
|
|
* This is used after power up before sending the first command
|
|
*
|
|
* @dev: Device to update
|
|
*/
|
|
void (*send_init_stream)(struct udevice *dev);
|
|
|
|
/**
|
|
* get_cd() - See whether a card is present
|
|
*
|
|
* @dev: Device to check
|
|
* @return 0 if not present, 1 if present, -ve on error
|
|
*/
|
|
int (*get_cd)(struct udevice *dev);
|
|
|
|
/**
|
|
* get_wp() - See whether a card has write-protect enabled
|
|
*
|
|
* @dev: Device to check
|
|
* @return 0 if write-enabled, 1 if write-protected, -ve on error
|
|
*/
|
|
int (*get_wp)(struct udevice *dev);
|
|
|
|
#ifdef MMC_SUPPORTS_TUNING
|
|
/**
|
|
* execute_tuning() - Start the tuning process
|
|
*
|
|
* @dev: Device to start the tuning
|
|
* @opcode: Command opcode to send
|
|
* @return 0 if OK, -ve on error
|
|
*/
|
|
int (*execute_tuning)(struct udevice *dev, uint opcode);
|
|
#endif
|
|
|
|
#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
|
|
/**
|
|
* wait_dat0() - wait until dat0 is in the target state
|
|
* (CLK must be running during the wait)
|
|
*
|
|
* @dev: Device to check
|
|
* @state: target state
|
|
* @timeout: timeout in us
|
|
* @return 0 if dat0 is in the target state, -ve on error
|
|
*/
|
|
int (*wait_dat0)(struct udevice *dev, int state, int timeout);
|
|
#endif
|
|
};
|
|
|
|
#define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
|
|
|
|
int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
|
|
struct mmc_data *data);
|
|
int dm_mmc_set_ios(struct udevice *dev);
|
|
void dm_mmc_send_init_stream(struct udevice *dev);
|
|
int dm_mmc_get_cd(struct udevice *dev);
|
|
int dm_mmc_get_wp(struct udevice *dev);
|
|
int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
|
|
int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout);
|
|
|
|
/* Transition functions for compatibility */
|
|
int mmc_set_ios(struct mmc *mmc);
|
|
void mmc_send_init_stream(struct mmc *mmc);
|
|
int mmc_getcd(struct mmc *mmc);
|
|
int mmc_getwp(struct mmc *mmc);
|
|
int mmc_execute_tuning(struct mmc *mmc, uint opcode);
|
|
int mmc_wait_dat0(struct mmc *mmc, int state, int timeout);
|
|
|
|
#else
|
|
struct mmc_ops {
|
|
int (*send_cmd)(struct mmc *mmc,
|
|
struct mmc_cmd *cmd, struct mmc_data *data);
|
|
int (*set_ios)(struct mmc *mmc);
|
|
int (*init)(struct mmc *mmc);
|
|
int (*getcd)(struct mmc *mmc);
|
|
int (*getwp)(struct mmc *mmc);
|
|
/*
|
|
add these members to impliment sample point auto-adaption
|
|
*/
|
|
int (*decide_retry)(struct mmc *mmc, int err_no, uint reset_count);
|
|
int (*update_sdly)(struct mmc *mmc, uint sdly);
|
|
int (*get_detail_errno)(struct mmc *mmc);
|
|
|
|
int (*update_phase)(struct mmc *mmc);
|
|
};
|
|
#endif
|
|
struct tune_sdly {
|
|
u32 tm4_smx_fx[12];
|
|
};
|
|
|
|
struct boot_mmc_cfg {
|
|
u8 boot0_para;
|
|
u8 boot_odly_50M;
|
|
u8 boot_sdly_50M;
|
|
u8 boot_odly_50M_ddr;
|
|
u8 boot_sdly_50M_ddr;
|
|
u8 boot_hs_f_max;
|
|
u8 res[2];
|
|
};
|
|
|
|
#define SDMMC_PRIV_INFO_ADDR_OFFSET (128)
|
|
struct boot_sdmmc_private_info_t {
|
|
struct tune_sdly tune_sdly;
|
|
struct boot_mmc_cfg boot_mmc_cfg;
|
|
|
|
#define CARD_TYPE_SD 0x8000001
|
|
#define CARD_TYPE_MMC 0x8000000
|
|
#define CARD_TYPE_NULL 0xffffffff
|
|
u32 card_type; /*0xffffffff: invalid; 0x8000000: mmc card; 0x8000001: sd card*/
|
|
|
|
#define EXT_PARA0_ID (0x55000000)
|
|
#define EXT_PARA0_TUNING_SUCCESS_FLAG (1U<<0)
|
|
u32 ext_para0;
|
|
|
|
/**GPIO 1.8V bias setting***/
|
|
#define EXT_PARA1_1V8_GPIO_BIAS 0x1
|
|
#define BOOT0_SUP_HS 0x2
|
|
u32 ext_para1;
|
|
/* ext_para/2/3 reseved for future */
|
|
u32 ext_para2;
|
|
u32 ext_para3;
|
|
};
|
|
|
|
|
|
struct mmc_config {
|
|
const char *name;
|
|
#if !CONFIG_IS_ENABLED(DM_MMC)
|
|
const struct mmc_ops *ops;
|
|
#endif
|
|
struct tune_sdly sdly;
|
|
#define MAX_EXT_FREQ_POINT_NUM (4)
|
|
u32 tm4_tune_ext_freq[MAX_EXT_FREQ_POINT_NUM];
|
|
uint host_no;
|
|
uint host_caps;
|
|
uint voltages;
|
|
uint f_min;
|
|
uint f_max;
|
|
uint b_max;
|
|
unsigned char part_type;
|
|
/* boot0 burn positon */
|
|
#define DRV_PARA_NOT_BURN_USER_PART (1U<<0)
|
|
#define DRV_PARA_BURN_EMMC_BOOT_PART (1U<<1)
|
|
#define DRV_PARA_BURN_FORCE_FLUSH_CACHE (1U<<3)
|
|
uint drv_burn_boot_pos;
|
|
|
|
/* struct mmc/drv_wipe_feature, define for driver secure wipe opeation */
|
|
#define DRV_PARA_DISABLE_SECURE_WIPE (1U<<0)
|
|
#define DRV_PARA_DISABLE_EMMC_SANITIZE (1U<<1)
|
|
#define DRV_PARA_DISABLE_EMMC_SECURE_PURGE (1U<<2)
|
|
#define DRV_PARA_DISABLE_EMMC_TRIM (1U<<3)
|
|
uint drv_wipe_feature;
|
|
|
|
/* struct mmc/drv_erase_feature, define for drvier erase operation */
|
|
#define DRV_PARA_DISABLE_EMMC_ERASE (1U<<0)
|
|
#define DRV_PARA_ENABLE_EMMC_SANITIZE_WHEN_ERASE (1U<<1)
|
|
uint drv_erase_feature;
|
|
|
|
/* struct mmc/drv_wp_feature */
|
|
#define DRV_PARA_ENABLE_EMMC_USER_PART_WP (1U<<0)
|
|
uint drv_wp_feature;
|
|
|
|
/* struct mmc/drv_hce_feature */
|
|
#define DRV_PARA_ENABLE_EMMC_HC_CAP_UNIT (1U<<0)
|
|
uint drv_hc_cap_unit_feature;
|
|
|
|
#define AUTO_SAMPLE_MODE (2)
|
|
#define MAUNAL_SAMPLE_MODE (1)
|
|
uint sample_mode;
|
|
|
|
uint io_is_1v8;
|
|
|
|
uint cal_delay_unit;
|
|
#define BOOT0_PARA_USE_INTERNAL_DEFAULT_TIMING_PARA (1U<<0)
|
|
/* 0: pass through struct sdly; 1: pass through boot_odly/sdly_* */
|
|
#define BOOT0_PARA_USE_EXTERNAL_INPUT_TIMING_PARA (1U<<1)
|
|
u8 boot0_para;
|
|
|
|
u8 boot_odly_50M;
|
|
u8 boot_sdly_50M;
|
|
u8 boot_odly_50M_ddr;
|
|
u8 boot_sdly_50M_ddr;
|
|
u8 boot_hs_f_max;
|
|
|
|
u8 *odly_spd_freq; //[40];
|
|
u8 *sdly_spd_freq; //[40];
|
|
|
|
u8 tm4_timing_window_th;
|
|
u8 tm4_tune_r_cycle;
|
|
u8 tm4_tune_hs200_max_freq;
|
|
u8 tm4_tune_hs400_max_freq;
|
|
u8 tune_limit_kernel_timing;
|
|
u8 res[1];
|
|
|
|
/* bit31: valid; bit23~16: speed mode; bit15~8: freq id; bit7:0 freq value */
|
|
|
|
#define DRV_PARA_DISABLE_MMC_MODE_HS (1 << 0) /* can run at 26MHz -- DS26_SDR12*/
|
|
#define DRV_PARA_DISABLE_MMC_MODE_HS_52MHz (1 << 1) /* can run at 52MHz with SDR mode -- HSSDR52_SDR25 */
|
|
#define DRV_PARA_DISABLE_MMC_MODE_4BIT (1 << 2)
|
|
#define DRV_PARA_DISABLE_MMC_MODE_8BIT (1 << 3)
|
|
#define DRV_PARA_DISABLE_MMC_MODE_SPI (1 << 4)
|
|
#define DRV_PARA_DISABLE_MMC_MODE_HC (1 << 5)
|
|
#define DRV_PARA_DISABLE_MMC_MODE_DDR_52MHz (1 << 6) /* can run at 52Mhz with DDR mode -- HSDDR52_DDR50 */
|
|
#define DRV_PARA_DISABLE_MMC_MODE_HS200 (1 << 7) /* can run at 200/208MHz with SDR mode -- HS200_SDR104*/
|
|
#define DRV_PARA_DISABLE_MMC_MODE_HS400 (1 << 8) /* can run at 200MHz with DDR mode -- HS400 */
|
|
#define DRV_PARA_ENABLE_EMMC_HW_RST (1 << 16) /* support to enable eMMC HW Rst when product */
|
|
u32 host_caps_mask;
|
|
u32 retune_caps_mask;
|
|
|
|
u32 force_boot_tuning;
|
|
|
|
/* enable the flow of field firmware update(FFU) flow */
|
|
u32 enable_ffu;
|
|
/* the byte length of emmc firmware, if it is 0, use the length get from toc0 header. if it is 0xffffffff, invalid len */
|
|
u32 emmc_fw_byte_len;
|
|
/* emmc_fw_ver0[31:0] = ext_csd[257] | ext_csd[256] | ext_csd[255] | ext_csd[254] */
|
|
u32 emmc_fw_ver0;
|
|
/* emmc_fw_ver1[31:0] = ext_csd[261] | ext_csd[260] | ext_csd[259] | ext_csd[258] */
|
|
u32 emmc_fw_ver1;
|
|
u32 emmc_ffu_mid;
|
|
u32 emmc_ffu_spt_fw; /*whether support many FWs*/
|
|
char *emmc_ffu_fw; /*original fw(32G),other FWs please add at the back*/
|
|
char *emmc_ffu_fw1;
|
|
uint emmc_set_block_count;
|
|
/*ext_csd 261:254*/
|
|
u64 ffu_src_fw_version;
|
|
u64 ffu_dest_fw_version;
|
|
|
|
/* 1: boot0 support HS400 or HS200; 0: not support*/
|
|
u8 boot0_sup_1v8;
|
|
struct clk *clk_mmc;
|
|
char clk_mmc_name[MMC_MAX_PLL_STRING_LEN];
|
|
char pll0[MMC_MAX_PLL_STRING_LEN];
|
|
char pll1[MMC_MAX_PLL_STRING_LEN];
|
|
char pll2[MMC_MAX_PLL_STRING_LEN];
|
|
};
|
|
|
|
struct sd_ssr {
|
|
unsigned int au; /* In sectors */
|
|
unsigned int erase_timeout; /* In milliseconds */
|
|
unsigned int erase_offset; /* In milliseconds */
|
|
};
|
|
|
|
enum bus_mode {
|
|
MMC_LEGACY,
|
|
SD_LEGACY,
|
|
MMC_HS,
|
|
SD_HS,
|
|
MMC_HS_52,
|
|
MMC_DDR_52,
|
|
UHS_SDR12,
|
|
UHS_SDR25,
|
|
UHS_SDR50,
|
|
UHS_DDR50,
|
|
UHS_SDR104,
|
|
MMC_HS_200,
|
|
MMC_HS_400,
|
|
MMC_MODES_END
|
|
};
|
|
|
|
const char *mmc_mode_name(enum bus_mode mode);
|
|
void mmc_dump_capabilities(const char *text, uint caps);
|
|
|
|
static inline bool mmc_is_mode_ddr(enum bus_mode mode)
|
|
{
|
|
if ((mode == MMC_DDR_52) || (mode == MMC_HS_400))
|
|
return true;
|
|
#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
|
|
else if (mode == UHS_DDR50)
|
|
return true;
|
|
#endif
|
|
else
|
|
return false;
|
|
}
|
|
|
|
#define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
|
|
MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
|
|
MMC_CAP(UHS_DDR50))
|
|
|
|
static inline bool supports_uhs(uint caps)
|
|
{
|
|
#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
|
|
return (caps & UHS_CAPS) ? true : false;
|
|
#else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
|
|
* with mmc_get_mmc_dev().
|
|
*
|
|
* TODO struct mmc should be in mmc_private but it's hard to fix right now
|
|
*/
|
|
#pragma pack(4)
|
|
struct mmc {
|
|
#if !CONFIG_IS_ENABLED(BLK)
|
|
struct list_head link;
|
|
#endif
|
|
const struct mmc_config *cfg; /* provided configuration */
|
|
uint version;
|
|
void *priv;
|
|
uint has_init;
|
|
int high_capacity;
|
|
bool clk_disable; /* true if the clock can be turned off */
|
|
uint bus_width;
|
|
uint clock;
|
|
enum mmc_voltage signal_voltage;
|
|
uint card_caps;
|
|
uint host_caps;
|
|
uint ocr;
|
|
uint dsr;
|
|
uint dsr_imp;
|
|
uint scr[2];
|
|
uint csd[4];
|
|
uint cid[4];
|
|
ushort rca;
|
|
u8 part_support;
|
|
u8 part_attr;
|
|
u8 wr_rel_set;
|
|
u8 part_config;
|
|
uint tran_speed;
|
|
uint legacy_speed; /* speed for the legacy mode provided by the card */
|
|
uint read_bl_len;
|
|
#if CONFIG_IS_ENABLED(MMC_WRITE)
|
|
uint write_bl_len;
|
|
uint erase_grp_size; /* in 512-byte sectors */
|
|
#endif
|
|
#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
|
|
uint hc_wp_grp_size; /* in 512-byte sectors */
|
|
#endif
|
|
#if CONFIG_IS_ENABLED(MMC_WRITE)
|
|
struct sd_ssr ssr; /* SD status register */
|
|
#endif
|
|
u64 capacity;
|
|
u64 capacity_user;
|
|
u64 capacity_boot;
|
|
u64 capacity_rpmb;
|
|
u64 capacity_gp[4];
|
|
#ifndef CONFIG_SPL_BUILD
|
|
u64 enh_user_start;
|
|
u64 enh_user_size;
|
|
#endif
|
|
#if !CONFIG_IS_ENABLED(BLK)
|
|
struct blk_desc block_dev;
|
|
#endif
|
|
char op_cond_pending; /* 1 if we are waiting on an op_cond command */
|
|
char init_in_progress; /* 1 if we have done mmc_start_init() */
|
|
char preinit; /* start init as early as possible */
|
|
int ddr_mode;
|
|
#if CONFIG_IS_ENABLED(DM_MMC)
|
|
struct udevice *dev; /* Device for this MMC controller */
|
|
#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
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struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/
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struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/
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#endif
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#endif
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uint speed_mode;
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u8 *ext_csd;
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u32 cardtype; /* cardtype read from the MMC */
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enum mmc_voltage current_voltage;
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enum bus_mode selected_mode; /* mode currently used */
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enum bus_mode best_mode; /* best mode is the supported mode with the
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* highest bandwidth. It may not always be the
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* operating mode due to limitations when
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* accessing the boot partitions
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*/
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u32 quirks;
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u32 tuning_end;
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u32 do_tuning;
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u32 msglevel;
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int manual_stop_flag;
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uint erase_timeout; /*default erasetimeout or hc_erase_timeout*/
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uint trim_discard_timeout;
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uint secure_erase_timeout;
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uint secure_trim_timeout;
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//u64 wp_grp_size; /* write protect group size */
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//u64 csd_perm_wp;
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//u64 csd_wp_grp_size;
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uchar secure_feature; // extcsd[231]
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};
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#pragma pack()
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struct mmc_hwpart_conf {
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struct {
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uint enh_start; /* in 512-byte sectors */
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uint enh_size; /* in 512-byte sectors, if 0 no enh area */
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unsigned wr_rel_change : 1;
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unsigned wr_rel_set : 1;
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} user;
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struct {
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uint size; /* in 512-byte sectors */
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unsigned enhanced : 1;
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unsigned wr_rel_change : 1;
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unsigned wr_rel_set : 1;
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} gp_part[4];
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};
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enum mmc_hwpart_conf_mode {
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MMC_HWPART_CONF_CHECK,
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MMC_HWPART_CONF_SET,
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MMC_HWPART_CONF_COMPLETE,
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};
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struct mmc_ext_csd {
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u8 rev;
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u8 erase_group_def;
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u8 sec_feature_support;
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u8 rel_sectors;
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u8 rel_param;
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u8 part_config;
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u8 cache_ctrl;
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u8 rst_n_function;
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u8 max_packed_writes;
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u8 max_packed_reads;
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u8 packed_event_en;
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unsigned int part_time; /* Units: ms */
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unsigned int sa_timeout; /* Units: 100ns */
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unsigned int generic_cmd6_time; /* Units: 10ms */
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unsigned int power_off_longtime; /* Units: ms */
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u8 power_off_notification; /* state */
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unsigned int hs_max_dtr;
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unsigned int hs200_max_dtr;
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#define MMC_HIGH_26_MAX_DTR 26000000
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#define MMC_HIGH_52_MAX_DTR 52000000
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#define MMC_HIGH_DDR_MAX_DTR 52000000
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#define MMC_HS200_MAX_DTR 200000000
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unsigned int sectors;
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unsigned int hc_erase_size; /* In sectors */
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unsigned int hc_erase_timeout; /* In milliseconds */
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unsigned int sec_trim_mult; /* Secure trim multiplier */
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unsigned int sec_erase_mult; /* Secure erase multiplier */
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unsigned int trim_timeout; /* In milliseconds */
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u8 enhanced_area_en; /* enable bit */
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unsigned long long enhanced_area_offset; /* Units: Byte */
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unsigned int enhanced_area_size; /* Units: KB */
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unsigned int cache_size; /* Units: KB */
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u8 hpi_en; /* HPI enablebit */
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u8 hpi; /* HPI support bit */
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unsigned int hpi_cmd; /* cmd used as HPI */
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u8 bkops; /* background support bit */
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u8 bkops_en; /* background enable bit */
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unsigned int data_sector_size; /* 512 bytes or 4KB */
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unsigned int data_tag_unit_size; /* DATA TAG UNIT size */
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unsigned int boot_ro_lock; /* ro lock support */
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u8 boot_ro_lockable;
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u8 raw_exception_status; /* 54 */
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u8 raw_partition_support; /* 160 */
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u8 raw_rpmb_size_mult; /* 168 */
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u8 raw_erased_mem_count; /* 181 */
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u8 raw_ext_csd_structure; /* 194 */
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u8 raw_card_type; /* 196 */
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u8 out_of_int_time; /* 198 */
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u8 raw_pwr_cl_52_195; /* 200 */
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u8 raw_pwr_cl_26_195; /* 201 */
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u8 raw_pwr_cl_52_360; /* 202 */
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u8 raw_pwr_cl_26_360; /* 203 */
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u8 raw_s_a_timeout; /* 217 */
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u8 raw_hc_erase_gap_size; /* 221 */
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u8 raw_erase_timeout_mult; /* 223 */
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u8 raw_hc_erase_grp_size; /* 224 */
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u8 raw_sec_trim_mult; /* 229 */
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u8 raw_sec_erase_mult; /* 230 */
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u8 raw_sec_feature_support;/* 231 */
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u8 raw_trim_mult; /* 232 */
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u8 raw_pwr_cl_200_195; /* 236 */
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u8 raw_pwr_cl_200_360; /* 237 */
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u8 raw_pwr_cl_ddr_52_195; /* 238 */
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u8 raw_pwr_cl_ddr_52_360; /* 239 */
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u8 raw_pwr_cl_ddr_200_360; /* 253 */
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u8 raw_bkops_status; /* 246 */
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u8 raw_sectors[4]; /* 212 - 4 bytes */
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unsigned int feature_support;
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#define MMC_DISCARD_FEATURE BIT(0) /* CMD38 feature */
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};
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struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
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/**
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* mmc_bind() - Set up a new MMC device ready for probing
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*
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* A child block device is bound with the IF_TYPE_MMC interface type. This
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* allows the device to be used with CONFIG_BLK
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*
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* @dev: MMC device to set up
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* @mmc: MMC struct
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* @cfg: MMC configuration
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* @return 0 if OK, -ve on error
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*/
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int mmc_bind(struct udevice *dev, struct mmc *mmc,
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const struct mmc_config *cfg);
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void mmc_destroy(struct mmc *mmc);
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/**
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* mmc_unbind() - Unbind a MMC device's child block device
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*
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* @dev: MMC device
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* @return 0 if OK, -ve on error
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*/
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int mmc_unbind(struct udevice *dev);
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int mmc_initialize(bd_t *bis);
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int mmc_init(struct mmc *mmc);
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int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
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/**
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* mmc_of_parse() - Parse the device tree to get the capabilities of the host
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*
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* @dev: MMC device
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* @cfg: MMC configuration
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* @return 0 if OK, -ve on error
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*/
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int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
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int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
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/**
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* mmc_voltage_to_mv() - Convert a mmc_voltage in mV
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*
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* @voltage: The mmc_voltage to convert
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* @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
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*/
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int mmc_voltage_to_mv(enum mmc_voltage voltage);
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/**
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* mmc_set_clock() - change the bus clock
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* @mmc: MMC struct
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* @clock: bus frequency in Hz
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* @disable: flag indicating if the clock must on or off
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* @return 0 if OK, -ve on error
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*/
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int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
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int mmc_set_bus_width(struct mmc *mmc, uint width);
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#define MMC_CLK_ENABLE false
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#define MMC_CLK_DISABLE true
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struct mmc *find_mmc_device(int dev_num);
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int mmc_set_dev(int dev_num);
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void print_mmc_devices(char separator);
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/**
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* get_mmc_num() - get the total MMC device number
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*
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* @return 0 if there is no MMC device, else the number of devices
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*/
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int get_mmc_num(void);
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int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
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int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
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enum mmc_hwpart_conf_mode mode);
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#if !CONFIG_IS_ENABLED(DM_MMC)
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int mmc_getcd(struct mmc *mmc);
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int board_mmc_getcd(struct mmc *mmc);
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int mmc_getwp(struct mmc *mmc);
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int board_mmc_getwp(struct mmc *mmc);
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#endif
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int mmc_set_dsr(struct mmc *mmc, u16 val);
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/* Function to change the size of boot partition and rpmb partitions */
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int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
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unsigned long rpmbsize);
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/* Function to modify the PARTITION_CONFIG field of EXT_CSD */
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int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
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/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
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int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
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/* Function to modify the RST_n_FUNCTION field of EXT_CSD */
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int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
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/* Functions to read / write the RPMB partition */
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int mmc_rpmb_set_key(struct mmc *mmc, void *key);
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int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
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int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
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unsigned short cnt, unsigned char *key);
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int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
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unsigned short cnt, unsigned char *key);
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#ifdef CONFIG_CMD_BKOPS_ENABLE
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int mmc_set_bkops_enable(struct mmc *mmc);
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#endif
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/**
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* Start device initialization and return immediately; it does not block on
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* polling OCR (operation condition register) status. Then you should call
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* mmc_init, which would block on polling OCR status and complete the device
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* initializatin.
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*
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* @param mmc Pointer to a MMC device struct
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* @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
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*/
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int mmc_start_init(struct mmc *mmc);
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/**
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* Set preinit flag of mmc device.
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*
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* This will cause the device to be pre-inited during mmc_initialize(),
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* which may save boot time if the device is not accessed until later.
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* Some eMMC devices take 200-300ms to init, but unfortunately they
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* must be sent a series of commands to even get them to start preparing
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* for operation.
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*
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* @param mmc Pointer to a MMC device struct
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* @param preinit preinit flag value
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*/
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void mmc_set_preinit(struct mmc *mmc, int preinit);
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#ifdef CONFIG_MMC_SPI
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#define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
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#else
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#define mmc_host_is_spi(mmc) 0
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#endif
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struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
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void board_mmc_power_init(void);
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int board_mmc_init(bd_t *bis);
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int cpu_mmc_init(bd_t *bis);
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int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
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int mmc_get_env_dev(void);
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/* Set block count limit because of 16 bit register limit on some hardware*/
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#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
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#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
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#endif
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/**
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* mmc_get_blk_desc() - Get the block descriptor for an MMC device
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*
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* @mmc: MMC device
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* @return block device if found, else NULL
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*/
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struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
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int mmc_send_manual_stop(struct mmc *mmc);
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int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd);
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int sunxi_need_rty(struct mmc *mmc);
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int sunxi_mmc_tuning_init(void);
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int sunxi_write_tuning(struct mmc *mmc);
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int sunxi_bus_tuning(struct mmc *mmc);
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int sunxi_mmc_tuning_exit(void);
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int sunxi_switch_to_best_bus(struct mmc *mmc);
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int mmc_exit(void);
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void mmc_update_config_for_dragonboard(int card_no);
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void mmc_set_mmcblckx(const char *node_name);
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void mmc_update_config_for_sdly(struct mmc *mmc);
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unsigned int sunxi_select_freq(struct mmc *mmc, int speed_md,
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int freq_index);
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#endif /* _MMC_H_ */
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