618 lines
20 KiB
C
Executable File
618 lines
20 KiB
C
Executable File
/*
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* rawnand.h
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*
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* Copyright (C) 2019 Allwinner.
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*
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* cuizhikui <cuizhikui@allwinnertech.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __RAWNAND_H__
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#define __RAWNAND_H__
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//#include "controller/ndfc_base.h"
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#include "../../aw_nand_type.h"
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#include "../nand_errno.h"
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#define NAND_MAX_ID_LEN 8
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#define NAND_MIN_ID_LEN 4
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#define OOB_BUF_SIZE 32
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#define SUPPORT_SUPER_STANDBY
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#define in_container_of(ptr, type, member) \
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(type *)((char *)(ptr) - (char *) &((type *)0)->member)
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static inline int MIN(int a, int b)
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{
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return ((a) > (b) ? (b) : (a));
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}
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static inline int MAX(int a, int b)
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{
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return ((a) > (b) ? (a) : (b));
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}
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struct nand_chip_info;
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struct _nand_info;
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typedef enum _nand_if_type {
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SDR = 0,
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ONFI_DDR = 0x2,
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ONFI_DDR2 = 0x12,
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TOG_DDR = 0x3,
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TOG_DDR2 = 0x13,
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} nand_if_type;
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enum NDFC_ENCODE {
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BCH = 0,
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LDPC,
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};
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enum DDR_INFO_NO_PARAS {
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DDR_INFO_PARAS0_DEF = 0,
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DDR_INFO_PARAS1_DRV_2 = 1,
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};
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/*
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*struct nand_chips_ops {
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* int (*nand_chips_init)(struct nand_chip_info *chip);
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* void (*nand_chips_cleanup)(struct nand_chip_info *chip);
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* int (*nand_chips_standby)(struct nand_chip_info *chip);
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* int (*nand_chips_resume)(struct nand_chip_info *chip);
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*};
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*/
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/**
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* struct nand_operation_instr:
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* @read_instr: read page instr serial eg. 00h[0]-addr-30h[1]
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* @multi_plane_read_instr: read page multi plane instr serial eg. 00h-addr-32h
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* a complete read page multi plane instr serial is:
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* 00h[0]-addr-32h[1]--00h[2]-addr-30h[3]
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* @write_instr: program page instr serial eg. 80h[0]-addr-10h[1]
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* @multi_plane_write_instr: write page multi plane instr serial eg.
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* a complete program page multi plane instr serial is:
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* 80h[0]-addr-11h[1]--80h[2]-addr-10h[3]
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* @copy_back_read_instr: copy back read instr serial eg. 00h[0]-addr-35h[1]
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* @copy_back_multi_plane_read_instr_instr[4]:
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* a complete copy back read page multi plane instr serial is:
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* 00h[0]-addr-32h[1]--00h[2]-addr-35h[3]
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* @copy_back_write_instr: copy back program page instr serial eg. 85h[0]-addr-10h[1]
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* @copy_back_multi_plane_write_instr_instr[4]: write page multi plane instr serial eg.
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* a complete copy back read page multi plane instr serial is:
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* 85h[0]-addr-11h[1]--85h[2]-addr-10h[3]
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* @read_status_instr: read die status command eg. 70h, for universal operation
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* @read_status_enhanced_instr: read die statu command eg. 78h, for multi
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* plane operation
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* @read_inter_bnk0_status_instr: inter-leave bank0 operation read status,
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* eg. f1h
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* @read_inter_bnk1_status_instr: inter-leave bank1 operation read status,
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* eg. f2h
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*/
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struct nand_operation_instr {
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unsigned char read_instr[2];
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unsigned char multi_plane_read_instr[4];
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unsigned char write_instr[2];
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unsigned char multi_plane_write_instr[4];
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unsigned char copy_back_read_instr[2];
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unsigned char copy_back_multi_plane_read_instr[4];
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unsigned char copy_back_write_instr[2];
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unsigned char copy_back_multi_plane_write_instr[4];
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unsigned char read_status_instr;
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unsigned char read_status_enhanced_instr;
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unsigned char read_inter_bnk0_status_instr;
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unsigned char read_inter_bnk1_status_instr;
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};
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/**
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* nand_phy_op_par: nand flash operation parameter
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* @inst: operation command
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*/
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struct nand_phy_op_par {
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struct nand_operation_instr instr;
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};
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/**
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* ndfc_init_ddr_info
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*
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*/
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struct ndfc_init_ddr_info {
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unsigned int en_dqs_c;
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unsigned int en_re_c;
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unsigned int odt;
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unsigned int en_ext_verf;
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unsigned int dout_re_warmup_cycle;
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unsigned int din_dqs_warmup_cycle;
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unsigned int output_driver_strength;
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unsigned int rb_pull_down_strength;
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};
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/*
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* Different manufacturers nand flash readretry is different
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* slc nand flash chose NAND_READRETRY_NO
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* generical mlc nand flash wanted to used readretry
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*/
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enum nand_readretry_type {
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NAND_READRETRY_NO = 0,
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NAND_READRETRY_HYNIX_16NM,
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NAND_READRETRY_HYNIX_20NM,
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NAND_READRETRY_HYNIX_26NM,
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NAND_READRETRY_MICRON,
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NAND_READRETRY_SAMSUNG,
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NAND_READRETRY_TOSHIBA,
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NAND_READRETRY_SANDISK,
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NAND_READRETRY_SANDISK_A19,
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};
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/**
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* bad block flag position
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*/
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typedef enum {
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FIRST_PAGE = 0,
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FIRST_TWO_PAGES,
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LAST_PAGE,
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LAST_TWO_PAGES,
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} bad_position_t;
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/**
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* _nand_physic_op_par:
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* @chip: chip no. begin with 0
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* @block: block no in chip. begin with 0
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* @page: page no. in one block. begin with 0
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* @sect_bitmap: req data len in sector. minimum is 2 or 4(one ecc block size,
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* reference ndfc spec)
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* @sdata: spare data buffer
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* @seln: req spare data len
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*
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*/
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struct _nand_physic_op_par {
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unsigned int chip;
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unsigned int block;
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unsigned int page;
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unsigned int sect_bitmap;
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unsigned char *mdata;
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unsigned char *sdata;
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unsigned int slen;
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};
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/**
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* onfi_cfg_t:
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* @support_ddr2_specific_cfg:
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* nand flash support to set ddr2 specific feature according to ONFI 3.0
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* @support_change_onfi_timing_mode:
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* nand flash support to change timing mode according to ONFI 3.0
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* @support_io_driver_strength:
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* nand flash support to set io driver strength according to ONFI 2.x/3.0
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* @support_rb_pull_down_strength:
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* nand flash support to set io RB strength according to ONFI 2.x/3.0
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*/
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typedef struct {
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u8 support_ddr2_specific_cfg;
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u8 support_change_onfi_timing_mode;
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u8 support_io_driver_strength;
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u8 support_rb_pull_down_strength ;
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} onfi_cfg_t;
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/**
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* toggle_cfg_t:
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* @support_specific_setting:
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* nand flash support to set ddr2 specific feature according to Toggle DDR2
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* @support_io_driver_strength_setting:
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* nand flash support to set io driver strength according to Toggle DDR1/DDR2
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* @support_vendor_specific_setting:
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* nand flash support to set vendor's specific configuration to change interface
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*/
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typedef struct {
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u8 support_specific_setting;
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u8 support_io_driver_strength_setting;
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u8 support_vendor_specific_setting;
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} toggle_cfg_t;
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typedef struct {
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onfi_cfg_t onfi_cfg;
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toggle_cfg_t toggle_cfg;
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} itf_cfg_t;
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/**
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* nand_chip_info:
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* @id: the chip identity
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* @nctri_chip_no: the chip num in nctri(channel)
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* @ blk_cnt_per_chip: the count of blocks in one chip
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* @sector_cnt_per_page: the count of sectors in one single physic page,
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* one sector is 0.5k
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* @page_cnt_per_blk:the count of physic pages in one physic block
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* @page_offset_for_next_blk: the count of physic pages in one physic block
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* @randomizer: is open randomizer flag
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* @ecc_mode: the Ecc Mode for the nand flash chip, 0: bch-16, 1:bch-28, 2:bch_32
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* @interface_type: 0x0: sdr; 0x2: nvddr; 0x3: tgddr; 0x12: nvddr2; 0x13: tgddr2
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* @frequency: the parameter of the hardware access clock, based on 'MHz':
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* @timing_mode: current timing mode
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* @support_onfi_sync_reset: nand flash support onfi's sync reset
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* @support_toggle_only: nand flash support toggle interface only,
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* and do not support switch between legacy and toggle
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* @ecc_sector: sector size, 512 or 1024
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* @random_cmd2_send_flag: special nand cmd for some nand in batch cmd, only for write
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* @random_addr_num: random col addr num in batch cmd
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* @nand_real_page_size: real physic page size
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* @opt_phy_op_par: the parameters for some optional operation
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* @info: device information in id table
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*/
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struct nand_chip_info {
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struct nand_chip_info *nsi_next;
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struct nand_chip_info *nctri_next;
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char id[8];
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unsigned int chip_no;
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unsigned int nctri_chip_no;
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unsigned int blk_cnt_per_chip;
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unsigned int sector_cnt_per_page;
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unsigned int page_cnt_per_blk;
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unsigned int page_offset_for_next_blk;
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unsigned int randomizer;
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unsigned int read_retry;
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unsigned char readretry_value[128];
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unsigned int retry_count;
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unsigned int lsb_page_type;
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unsigned int ecc_mode;
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unsigned int max_erase_times;
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unsigned int driver_no;
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unsigned int interface_type;
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unsigned int frequency;
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unsigned int timing_mode;
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unsigned int support_onfi_sync_reset;
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unsigned int support_toggle_only;
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bad_position_t bad_block_flag_position;
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unsigned int multi_plane_block_offset;
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unsigned int page_addr_bytes;
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unsigned int sdata_bytes_per_page;
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unsigned int ecc_sector;
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unsigned int random_cmd2_send_flag;
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unsigned int random_addr_num;
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unsigned int nand_real_page_size;
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unsigned int sharedpage_pairedwrite;
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unsigned int sharedpage_offset;
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itf_cfg_t itf_cfg;
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struct nand_super_chip_info *nsci;
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struct nand_controller_info *nctri;
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struct sunxi_nand_flash_device *npi;
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struct nand_phy_op_par *opt_phy_op_par;
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struct nfc_init_ddr_info *nfc_init_ddr_info;
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struct nand_dev_ops *dev_ops;
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int (*nand_physic_erase_block)(struct _nand_physic_op_par *npo);
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int (*nand_physic_read_page)(struct _nand_physic_op_par *npo);
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int (*nand_physic_write_page)(struct _nand_physic_op_par *npo);
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int (*nand_physic_bad_block_check)(struct _nand_physic_op_par *npo);
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int (*nand_physic_bad_block_mark)(struct _nand_physic_op_par *npo);
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int (*nand_read_boot0_page)(struct nand_chip_info *nci, struct _nand_physic_op_par *npo);
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int (*nand_write_boot0_page)(struct nand_chip_info *nci, struct _nand_physic_op_par *npo);
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int (*nand_read_boot0_one)(unsigned char *buf, unsigned int len, unsigned int counter);
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int (*nand_write_boot0_one)(unsigned char *buf, unsigned int len, unsigned int counter);
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int (*is_lsb_page)(__u32 page_num);
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};
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/*
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* define the nand flash chip information
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* @sector_cnt_per_super_page: the count of sectors in one single physic page, one sector is 0.5k
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* @page_cnt_per_super_blk: the count of super pages in one super block
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* @page_offset_for_next_super_blk: the count of siper pages in one super block
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* @spare_bytes: oob size
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* @two_plane: nsci is support two plane operation flag
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* @vertical_interleave: nsci is support vertical_interleave flag
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* @dual_channel: nsci is support dual channel flag
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* @nci_first: first nci belong to this super chip
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* @v_intl_nci_1: first nci in interleave operation
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* @v_intl_nci_2: second nci in interleave operation
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* @d_channel_nci_1: first nci in dual_channel operation
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* @d_channel_nci_2: second nci in dual_channel operation
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*/
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struct nand_super_chip_info {
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struct nand_super_chip_info *nssi_next;
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unsigned int chip_no;
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unsigned int blk_cnt_per_super_chip;
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unsigned int sector_cnt_per_super_page;
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unsigned int page_cnt_per_super_blk;
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unsigned int page_offset_for_next_super_blk;
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unsigned int spare_bytes;
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unsigned int channel_num;
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unsigned int two_plane;
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unsigned int vertical_interleave;
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unsigned int dual_channel;
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unsigned int driver_no;
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struct nand_chip_info *nci_first;
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struct nand_chip_info *v_intl_nci_1;
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struct nand_chip_info *v_intl_nci_2;
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struct nand_chip_info *d_channel_nci_1;
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struct nand_chip_info *d_channel_nci_2;
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int (*nand_physic_erase_super_block)(struct _nand_physic_op_par *npo);
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int (*nand_physic_read_super_page)(struct _nand_physic_op_par *npo);
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int (*nand_physic_write_super_page)(struct _nand_physic_op_par *npo);
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int (*nand_physic_super_bad_block_check)(struct _nand_physic_op_par *npo);
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int (*nand_physic_super_bad_block_mark)(struct _nand_physic_op_par *npo);
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};
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/* rawnand_storage_info_t
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* define the nand flash storage system information
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* @ChipCnt: the count of the total nand flash chips are currently connecting on the CE pin
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* @ChipConnectInfo: chip connect information, bit == 1 means there is a chip connecting on the CE pin
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* @RbConnectInfo: the connect information of the all rb chips are connected
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* @RbConnectMode: the rb connect mode
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* @BankCntPerChip: the count of the banks in one nand chip, multiple banks can support Inter-Leave
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* @DieCntPerChip: the count of the dies in one nand chip, block management is based on Die
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* @PlaneCntPerDie: the count of planes in one die, multiple planes can support multi-plane operation
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* @SectorCntPerPage: the count of sectors in one single physic page, one sector is 0.5k
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* @PageCntPerPhyBlk: the count of physic pages in one physic block
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* @BlkCntPerDie: the count of the physic blocks in one die, include valid block and invalid block
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* @OperationOpt: the mask of the operation types which current nand flash can support support
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* @FrequencePar: the parameter of the hardware access clock, based on 'MHz'
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* @EccMode: the Ecc Mode for the nand flash chip, 0: bch-16, 1:bch-28, 2:bch_32
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* @NandChipId[8]: the nand chip id of current connecting nand chip
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* @ValidBlkRatio: the ratio of the valid physical blocks, based on 1024
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* @ReadRetryType: the read retry type
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* @DDRType: interface type (SDR/ONFI DDR/TOGGLE DDR)
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* @random_cmd2_send_flag: special nand cmd for some nand in batch cmd, only for write
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* @random_addr_num: random col addr num in batch cmd
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* @nand_real_page_size: real physic page size
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* @OptPhyOpPar: the parameters for some optional operation
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*/
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typedef struct rawnand_storage_info {
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unsigned int ChannelCnt;
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unsigned int ChipCnt;
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unsigned int ChipConnectInfo;
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unsigned int RbCnt;
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unsigned int RbConnectInfo;
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unsigned int RbConnectMode;
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unsigned int BankCntPerChip;
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unsigned int DieCntPerChip;
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unsigned int PlaneCntPerDie;
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unsigned int SectorCntPerPage;
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unsigned int PageCntPerPhyBlk;
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unsigned int BlkCntPerDie;
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unsigned int OperationOpt;
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unsigned int FrequencePar;
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unsigned int EccMode;
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unsigned char NandChipId[8];
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unsigned int ValidBlkRatio;
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unsigned int ReadRetryType;
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unsigned int DDRType;
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unsigned int random_cmd2_send_flag;
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unsigned int random_addr_num;
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unsigned int nand_real_page_size;
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struct nand_phy_op_par OptPhyOpPar;
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} rawnand_storage_info_t;
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/*
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* _nand_storage_info:
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* define the nand flash storage system information
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* @chip_cnt: the count of chip
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*/
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struct _nand_storage_info {
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unsigned int chip_cnt;
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unsigned int block_nums;
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struct nand_chip_info *nci;
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};
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/*
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* _nand_super_storage_inf:
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* define the nand flash storage system information
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*/
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struct _nand_super_storage_info {
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unsigned int super_chip_cnt;
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unsigned int super_block_nums;
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unsigned int support_two_plane;
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unsigned int support_v_interleave;
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unsigned int support_dual_channel;
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struct nand_super_chip_info *nsci;
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unsigned int plane_cnt;
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};
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struct onfi_ops_t {
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int (*ddr2_cfg) (struct nand_chip_info *nci);
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int (*driver_strength) (struct nand_chip_info *nci);
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int (*rb_strength) (struct nand_chip_info *nci);
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int (*timing_mode)(struct nand_chip_info *nci, nand_if_type if_type, u32 timing_mode);
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};
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struct toggle_ops_t {
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/*set to DDR / DDR2*/
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int (*specific_setting) (struct nand_chip_info *nci);
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int (*driver_strength) (struct nand_chip_info *nci);
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/*switch to sdr or ddr*/
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int (*vendor_specific_setting) (struct nand_chip_info *nci);
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};
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struct itf_ops_t {
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struct onfi_ops_t onfi;
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struct toggle_ops_t toggle;
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};
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/**
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* sunxi_nand_flash_device nand flash device id structure
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* @name: a human-readable name of the NAND chip
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* @mfr: manufacturer ID (the first byte of nand_id[])
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* @dev_id: device ID (the sencond byte of nand_id[])
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* @nand_id: the ID number of the nand flash chip
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* @die_cnt_per_chip: the count of the die in one nand flash chip
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* @sect_cnt_per_page: the count of the sectors in one single physical page
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* @page_cnt_per_blk: the count of the pages in one single physical block
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* @blk_cnt_per_die: the count fo the physical blocks in one nand flash die
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* @operation_opt: the bitmap that marks which optional operation that the nand flash can support
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* @valid_blk_ratio: no use
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* @access_freq : the access frequence of the nand flash chip, based on mhz
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* @ecc_mode: the ecc mode for the nand flash chip, 0: bch-16, 1:bch-28, 2:bch_28 3:32 4:40 5:48 6:56 7:60 8:64 9:72
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* @read_retry_type : relate to readretry function
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* @ddr_type: 0:sdr 1:null 2:onfi nvddr1 3:toggle ddr1 0x12: onfi ddr2 0x13: toggle ddr2
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* @ddr_opt: some ddr interface param config option
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* @bad_block_flag_position: manufacture bad block mark flag
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* @multi_plane_block_offset: abut plane block offset
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* @cmd_set_no : the flash operation command set number
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* @ddr_info_no: ddr interface init information struct no.
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* @selected_write_boot0_no : boot0 interface choose
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* @selected_readretry_no : read retry interface choose
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* @id_number : drive no
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* @access_high_freq : maximum frequerence, keep same with access_freq.
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* @max_blk_erase_times : maximum erasure times
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* @random_cmd2_send_flag: special nand cmd for some nand in batch cmd,only for write, no use, not reflected in id table
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* @random_addr_num: random col addr num in batch cmd, no use, not reflected in id table
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* @nand_real_page_size: real physic page size, no use ,not reflected in id table
|
|
*/
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struct sunxi_nand_flash_device {
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char *name;
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|
union {
|
|
struct {
|
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u8 mfr_id;
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u8 dev_id;
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|
};
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u8 id[NAND_MAX_ID_LEN];
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};
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unsigned int die_cnt_per_chip;
|
|
unsigned int sect_cnt_per_page;
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unsigned int page_cnt_per_blk;
|
|
unsigned int blk_cnt_per_die;
|
|
unsigned long long operation_opt;
|
|
unsigned int valid_blk_ratio;
|
|
unsigned int access_freq;
|
|
unsigned int ecc_mode;
|
|
unsigned int read_retry_type;
|
|
unsigned int ddr_type;
|
|
unsigned int ddr_opt;
|
|
bad_position_t bad_block_flag_position;
|
|
unsigned int multi_plane_block_offset;
|
|
unsigned int cmd_set_no;
|
|
unsigned int ddr_info_no;
|
|
unsigned int selected_write_boot0_no;
|
|
enum nand_readretry_type selected_readretry_no;
|
|
unsigned int id_number;
|
|
unsigned int max_blk_erase_times;
|
|
unsigned int access_high_freq;
|
|
unsigned int random_cmd2_send_flag;
|
|
unsigned int random_addr_num;
|
|
unsigned int nand_real_page_size;
|
|
unsigned int sharedpage_offset;
|
|
};
|
|
|
|
/**
|
|
* nfc_init_ddr_info: ddr interface init's parameter
|
|
*/
|
|
struct nfc_init_ddr_info {
|
|
unsigned int en_dqs_c;
|
|
unsigned int en_re_c;
|
|
unsigned int odt;
|
|
unsigned int en_ext_verf;
|
|
unsigned int dout_re_warmup_cycle;
|
|
unsigned int din_dqs_warmup_cycle;
|
|
unsigned int output_driver_strength;
|
|
unsigned int rb_pull_down_strength;
|
|
};
|
|
|
|
/*
|
|
* define physical parameter to flash 128bytes
|
|
*/
|
|
#define MAGIC_DATA_FOR_PERMANENT_DATA (0xa5a5a5a5)
|
|
struct _nand_permanent_data {
|
|
unsigned int magic_data;
|
|
unsigned int support_two_plane;
|
|
unsigned int support_vertical_interleave;
|
|
unsigned int support_dual_channel;
|
|
unsigned int reserved[64 - 4];
|
|
};
|
|
|
|
/*
|
|
* _nand_temp_buf:
|
|
* define physical temp buf
|
|
*/
|
|
struct _nand_temp_buf {
|
|
|
|
#define NUM_16K_BUF 2
|
|
#define NUM_32K_BUF 4
|
|
#define NUM_64K_BUF 1
|
|
#define NUM_NEW_BUF 4
|
|
|
|
unsigned int used_16k[NUM_16K_BUF];
|
|
unsigned int used_16k_flag[NUM_16K_BUF];
|
|
unsigned char *nand_temp_buf16k[NUM_16K_BUF];
|
|
|
|
unsigned int used_32k[NUM_32K_BUF];
|
|
unsigned int used_32k_flag[NUM_32K_BUF];
|
|
unsigned char *nand_temp_buf32k[NUM_32K_BUF];
|
|
|
|
unsigned int used_64k[NUM_64K_BUF];
|
|
unsigned int used_64k_flag[NUM_64K_BUF];
|
|
unsigned char *nand_temp_buf64k[NUM_64K_BUF];
|
|
|
|
unsigned int used_new[NUM_NEW_BUF];
|
|
unsigned int used_new_flag[NUM_NEW_BUF];
|
|
unsigned char *nand_new_buf[NUM_NEW_BUF];
|
|
};
|
|
|
|
#ifndef NULL
|
|
#define NULL (0)
|
|
#endif
|
|
#if 0
|
|
struct nand_id_tbl_info_ops {
|
|
char *(*get_name)(struct nand_chip_info *chip);
|
|
void (*get_id)(struct nand_chip_info *chip, unsigned char *id, int cnt);
|
|
unsigned int (*get_die_cnt)(struct nand_chip_info *chip);
|
|
unsigned int (*get_page_size)(struct nand_chip_info *chip,
|
|
enum sizetype type);
|
|
unsigned int (*get_block_size)(struct nand_chip_info *chip,
|
|
enum sizetype type);
|
|
unsigned int (*get_die_size)(struct nand_chip_info *chip,
|
|
enum sizetype type);
|
|
unsigned long long (*get_opt)(struct nand_chip_info chip);
|
|
unsigned int (*get_freq)(struct nand_chip_info chip);
|
|
unsigned int (*get_ecc_mode)(struct nand_chip_info chip);
|
|
unsigned int (*get_readretry_type)(struct nand_chip_info chip);
|
|
unsigned int (*get_ddr_type)(struct nand_chip_info chip);
|
|
unsigned int (*get_id_number)(struct nand_chip_info chip);
|
|
unsigned int (*get_max_erase_times)(struct nand_chip_info chip);
|
|
unsigned int (*get_access_high_freq)(struct nand_chip_info chip);
|
|
};
|
|
#endif
|
|
extern struct itf_ops_t sansumg_itf_ops;
|
|
extern struct itf_ops_t sandisk_itf_ops;
|
|
extern struct itf_ops_t toshiba_itf_ops;
|
|
extern struct itf_ops_t hynix_itf_ops;
|
|
extern struct itf_ops_t micron_itf_ops;
|
|
extern struct itf_ops_t intel_itf_ops;
|
|
|
|
void rawnand_update_timings_ift_ops(int mfr_type);
|
|
int rawnand_async_to_onfi_ddr_or_ddr2_set(struct nand_chip_info *nci, nand_if_type ddr_type);
|
|
int rawnand_onfi_ddr_or_ddr2_to_async_set(struct nand_chip_info *nci, nand_if_type ddr_type,
|
|
nand_if_type pre_ddr_type);
|
|
int rawnand_toggle_ddr_or_ddr2_to_async_set(struct nand_chip_info *nci, nand_if_type ddr_type,
|
|
nand_if_type pre_ddr_type);
|
|
int rawnand_async_to_toggle_ddr_or_ddr2_set(struct nand_chip_info *nci, nand_if_type ddr_type);
|
|
int rawnand_toggle_ddr2_to_toggle_ddr_set(struct nand_chip_info *nci);
|
|
int rawnand_itf_unchanged_set(struct nand_chip_info *nci, nand_if_type ddr_type,
|
|
nand_if_type pre_ddr_type);
|
|
|
|
int rawnand_chips_init(struct nand_chip_info *nci);
|
|
void rawnand_chip_special_init(enum nand_readretry_type type);
|
|
void rawnand_chip_special_exit(enum nand_readretry_type type);
|
|
int rawnand_sp_chips_init(struct nand_super_chip_info *nsci);
|
|
void rawnand_chips_cleanup(struct nand_chip_info *chip);
|
|
int rawnand_chips_super_standby(struct nand_chip_info *chip);
|
|
int rawnand_chips_super_resume(struct nand_chip_info *chip);
|
|
int rawnand_chips_normal_standby(struct nand_chip_info *chip);
|
|
int rawnand_chips_normal_resume(struct nand_chip_info *chip);
|
|
#endif /*RAWNAND_H*/
|