99 lines
2.8 KiB
C
99 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0*/
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#ifndef __NAND_LIB_CFG_H__
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#define __NAND_LIB_CFG_H__
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#include "../../aw_nand_type.h"
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/*
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* define in nand_boot.h
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*#define NAND_BOOT0_PAGE_CNT_PER_COPY 64
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*#define NAND_BOOT0_PAGE_CNT_PER_COPY_2 128
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*#define NAND_BOOT0_PAGE_CNT_PER_COPY_4 256 //A50 boot0 size >= 128K
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*/
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/*boot0 size refer to brom, need consistent with brom configuration*/
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#if defined(CONFIG_ARCH_SUN8IW18) || defined(CONFIG_ARCH_SUN50IW11)
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#define NAND_BOOT0_PAGE_CNT_PER_COPY NAND_BOOT0_PAGE_CNT_PER_COPY_4
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#else
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#define NAND_BOOT0_PAGE_CNT_PER_COPY NAND_BOOT0_PAGE_CNT_PER_COPY_2
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#endif
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struct nand_cfg {
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unsigned int phy_interface_cfg;
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unsigned int phy_support_two_plane;
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unsigned int phy_nand_support_vertical_interleave;
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unsigned int phy_support_dual_channel;
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unsigned int phy_wait_rb_before;
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unsigned int phy_wait_rb_mode;
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unsigned int phy_wait_dma_mode;
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};
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extern struct nand_cfg *g_phy_cfg;
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#define PHY_ONLY_TOG_AND_SDR 1
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#define PHY_WAIT_RB_BEFORE 1
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#define PHY_WAIT_RB_INTERRUPT 1
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#if defined(CONFIG_ARCH_SUN8IW18)
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#define PHY_WAIT_DMA_INTERRUPT 0 //((wait_dma_int == 1) ? 1 : 0)
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#else
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#define PHY_WAIT_DMA_INTERRUPT 1 //((wait_dma_int == 1) ? 1 : 0)
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#endif
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#define SUPPORT_UPDATE_EXTERNAL_ACCESS_FREQ (1)
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#define SUPPORT_CHANGE_ONFI_TIMING_MODE (1)
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#define SUPPORT_SCAN_EDO_FOR_SDR_NAND (0)
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#define GOOD_DDR_EDO_DELAY_CHAIN_TH (7)
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#define MAX_SECTORS_PER_PAGE_FOR_TWO_PLANE (32)
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/****************************************************************************
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*Single channel needs to be affixed to the same kind of flashdddd
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*Dual channel needs to be affixed to the same number and type of flash
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*
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*Single channel
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*1.support two-plane
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*2.support vertical_interleave
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*3.if superpage>32k two-plane not supported
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*4.vertical_interleave chip pairing with different rb in the channel
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*
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*Dual channel
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*1.support two-plane
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*2.support dual_channel
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*3.support vertical_interleave
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*4.if superpage>32k two-plane not supported
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*5.dual_channel chip pairing with same chip number between the channel
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86.vertical_interleave chip pairing with different rb in the channel
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*****************************************************************************/
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#define PHY_SUPPORT_TWO_PLANE 1
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#define PHY_SUPPORT_VERTICAL_INTERLEAVE 1
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#define PHY_SUPPORT_DUAL_CHANNEL 1
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//#define NAND_VERSION 0x0223
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//#define NAND_DRV_DATE 0x20150312
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#define SUPPORT_UPDATE_EXTERNAL_ACCESS_FREQ (1)
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#define SUPPORT_CHANGE_ONFI_TIMING_MODE (1)
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#define SUPPORT_SCAN_EDO_FOR_SDR_NAND (0)
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#define GOOD_DDR_EDO_DELAY_CHAIN_TH (7)
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#define MAX_SECTORS_PER_PAGE_FOR_TWO_PLANE (32)
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int nand_cfg_interface(void);
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int nand_wait_rb_before(void);
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int nand_wait_rb_mode(void);
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int nand_wait_dma_mode(void);
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int nand_support_two_plane(void);
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int nand_support_vertical_interleave(void);
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int nand_support_dual_channel(void);
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#endif /*NAND_LIB_CFG_H*/
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