357 lines
13 KiB
C
Executable File
357 lines
13 KiB
C
Executable File
/*
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* Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "pm/pm.h"
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#include "board_common.h"
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#include "board.h"
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#include "driver/chip/psram/psram.h"
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#include "driver/chip/hal_util.h"
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#include "driver/chip/hal_rcosc_cali.h"
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HAL_Status board_pinmux_cfg(HAL_BoardIoctlReq req,
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const GPIO_PinMuxParam *pinmux, uint32_t count)
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{
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switch (req) {
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case HAL_BIR_PINMUX_INIT:
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HAL_GPIO_PinMuxConfig(pinmux, count);
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break;
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case HAL_BIR_PINMUX_DEINIT:
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HAL_GPIO_PinMuxDeConfig(pinmux, count);
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break;
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#ifdef CONFIG_PM
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case HAL_BIR_PINMUX_SUSPEND:
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{
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GPIO_PinMuxParam *_pinmux = HAL_Malloc(sizeof(GPIO_PinMuxParam) * count);
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uint32_t _count = 0;
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if (!_pinmux) {
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printf("malloc faild!\n");
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return HAL_INVALID;
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}
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HAL_GPIO_PinMuxDeConfig(pinmux, count);
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for (int i = 0; i < count; i++) {
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if (pinmux[i].config.pull != GPIO_PULL_NONE) {
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HAL_Memcpy(&_pinmux[_count], &pinmux[i], sizeof(GPIO_PinMuxParam));
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_pinmux[_count].config.mode = GPIOx_Pn_F0_INPUT;
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_count++;
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}
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}
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HAL_GPIO_PinMuxConfig(_pinmux, _count);
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HAL_Free(_pinmux);
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break;
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}
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case HAL_BIR_PINMUX_RESUME:
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{
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GPIO_PinMuxParam *_pinmux = HAL_Malloc(sizeof(GPIO_PinMuxParam) * count);
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uint32_t _count = 0;
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if (!_pinmux) {
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printf("malloc faild!\n");
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return HAL_INVALID;
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}
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for (int i = 0; i < count; i++) {
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if (pinmux[i].config.pull != GPIO_PULL_NONE) {
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HAL_Memcpy(&_pinmux[_count], &pinmux[i], sizeof(GPIO_PinMuxParam));
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_count++;
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}
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}
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HAL_GPIO_PinMuxDeConfig(_pinmux, _count);
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HAL_GPIO_PinMuxConfig(pinmux, count);
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HAL_Free(_pinmux);
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break;
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}
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#endif
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default:
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return HAL_INVALID;
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}
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return HAL_OK;
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}
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#ifndef CONFIG_BOOTLOADER
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#ifdef CONFIG_PM
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static int lfclk_suspend(struct soc_device *dev, enum suspend_state_t state)
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{
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switch (state) {
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case PM_MODE_SLEEP:
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break;
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case PM_MODE_STANDBY:
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break;
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case PM_MODE_HIBERNATION:
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#if (defined(BOARD_LOSC_EXTERNAL) && BOARD_LOSC_EXTERNAL)
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#else
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/* Disable inter 32K calibration before enter standby, hibernation,
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* poweroff, etc. to avoid wrong RTC time counting.
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*/
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#if (CONFIG_CHIP_ARCH_VER == 2)
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if (state == PM_MODE_STANDBY) {
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uint16_t u16RrefTime;
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u16RrefTime = 10 * HAL_GetHFClock() / HAL_GetLFClock(PRCM_LFCLK_MODULE_SYS) + 0x200;
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HAL_PRCM_SetDigSWRefTime(u16RrefTime);
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}
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HAL_PRCM_DisableInter32KCalib();
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#elif (CONFIG_CHIP_ARCH_VER == 3)
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{
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RCOCALI_ConfigParam configParm = {
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.mode = PRCM_RCOSC_WK_MODE_SEL_SCALE,
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.phase2_times = PRCM_RCOSC_SCALE_PHASE2_WK_TIMES_4,
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.phase3_times = PRCM_RCOSC_SCALE_PHASE3_WK_TIMES_128,
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.phase1_num = 1,
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.phase2_num = 1,
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.wup_time = 7680,
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};
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HAL_RcoscCali_Stop();
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HAL_RcoscCali_Config(&configParm);
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HAL_RcoscCali_Start();
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}
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#endif
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#endif
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break;
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default:
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break;
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}
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return 0;
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}
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static int lfclk_resume(struct soc_device *dev, enum suspend_state_t state)
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{
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switch (state) {
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case PM_MODE_SLEEP:
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break;
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case PM_MODE_STANDBY:
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#if (defined(BOARD_LOSC_EXTERNAL) && BOARD_LOSC_EXTERNAL)
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#else
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#if (CONFIG_CHIP_ARCH_VER == 2)
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HAL_PRCM_EnableInter32KCalib();
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#endif
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#endif
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break;
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case PM_MODE_HIBERNATION:
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break;
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default:
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break;
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}
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return 0;
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}
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static const struct soc_device_driver lfclk_drv = {
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.name = "lfclk",
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.suspend_noirq = lfclk_suspend,
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.resume_noirq = lfclk_resume,
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};
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static struct soc_device lfclk_dev = {
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.name = "lfclk",
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.driver = &lfclk_drv,
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};
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#endif
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static void lfclk_init(void)
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{
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if (HAL_GET_BIT(PRCM->BLE_CLK32K_SWITCH0, PRCM_SYS_CLK32K_RCO_CALIB_SEL_BIT) == 0) {
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#if (defined(BOARD_LOSC_EXTERNAL) && BOARD_LOSC_EXTERNAL)
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HAL_PRCM_SetLFCLKBaseSource(PRCM_LFCLK_BASE_SRC_EXT32K);
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HAL_PRCM_DisableInter32KCalib();
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HAL_PRCM_SetLFCLKSource(PRCM_LFCLK_MODULE_SYS, PRCM_LFCLK_SRC_LOSC);
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HAL_PRCM_SetLFCLKSource(PRCM_LFCLK_MODULE_WKTIMER, PRCM_LFCLK_SRC_LOSC);
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HAL_PRCM_SetLFCLKSource(PRCM_LFCLK_MODULE_WLAN, PRCM_LFCLK_SRC_LOSC);
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HAL_PRCM_SetLFCLKSource(PRCM_LFCLK_MODULE_BLE, PRCM_LFCLK_SRC_LOSC);
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HAL_PRCM_SetLFCLKSource(PRCM_LFCLK_MODULE_RTC, PRCM_LFCLK_SRC_LOSC);
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HAL_RcoscCali_DeInit();
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#else
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#if (CONFIG_CHIP_ARCH_VER == 2)
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HAL_PRCM_SetLFCLKBaseSource(PRCM_LFCLK_BASE_SRC_INTER32K);
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HAL_PRCM_EnableInter32KCalib();
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#elif (CONFIG_CHIP_ARCH_VER == 3)
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HAL_PRCM_SetLFCLKBaseSource(PRCM_LFCLK_BASE_SRC_INTER32K); /* should set again for release LOSC pin */
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HAL_PRCM_DisableInter32KCalib();
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static RCOCALI_InitParam initParam;
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initParam.cnt_n = 8192;
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initParam.out_clk = 32000;
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HAL_RcoscCali_Init(&initParam);
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RCOCALI_ConfigParam configParm = {
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.mode = PRCM_RCOSC_WK_MODE_SEL_SCALE,
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.phase2_times = PRCM_RCOSC_SCALE_PHASE2_WK_TIMES_4,
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.phase3_times = PRCM_RCOSC_SCALE_PHASE3_WK_TIMES_24,
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.phase1_num = 1,
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.phase2_num = 1,
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.wup_time = 640,
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};
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HAL_RcoscCali_Config(&configParm);
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HAL_PRCM_SetRcoscCalStartSrc(PRCM_RCOSC_CAL_START_APPANDWLANSLEEP);
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HAL_RcoscCali_Start();
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HAL_PRCM_SetLFCLKSource(PRCM_LFCLK_MODULE_SYS, PRCM_LFCLK_SRC_RCCAL);
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HAL_PRCM_SetLFCLKSource(PRCM_LFCLK_MODULE_WKTIMER, PRCM_LFCLK_SRC_RCCAL);
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HAL_PRCM_SetLFCLKSource(PRCM_LFCLK_MODULE_WLAN, PRCM_LFCLK_SRC_RCCAL);
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HAL_PRCM_SetLFCLKSource(PRCM_LFCLK_MODULE_BLE, PRCM_LFCLK_SRC_RCCAL);
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HAL_PRCM_SetLFCLKSource(PRCM_LFCLK_MODULE_RTC, PRCM_LFCLK_SRC_RCCAL);
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#endif /* CONFIG_CHIP_ARCH_VER */
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#endif
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}
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#ifdef CONFIG_PM
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pm_register_ops(&lfclk_dev);
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#endif
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}
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#endif
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void board_chip_clock_init(void)
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{
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#ifdef CONFIG_HOSC_TYPE_24M
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HAL_PRCM_SetHOSCType(PRCM_HOSC_TYPE_24M);
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HAL_PRCM_SetSysPLL(PRCM_SYS_PLL_PARAM_HOSC24M);
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#elif (defined CONFIG_HOSC_TYPE_26M)
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HAL_PRCM_SetHOSCType(PRCM_HOSC_TYPE_26M);
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HAL_PRCM_SetSysPLL(PRCM_SYS_PLL_PARAM_HOSC26M);
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#elif (defined CONFIG_HOSC_TYPE_32M)
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HAL_PRCM_SetHOSCType(PRCM_HOSC_TYPE_32M);
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HAL_PRCM_SetSysPLL(PRCM_SYS_PLL_PARAM_HOSC32M);
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#elif (defined CONFIG_HOSC_TYPE_40M)
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HAL_PRCM_SetHOSCType(PRCM_HOSC_TYPE_40M);
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HAL_PRCM_SetSysPLL(PRCM_SYS_PLL_PARAM_HOSC40M);
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#elif (defined CONFIG_HOSC_TYPE_52M)
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HAL_PRCM_SetHOSCType(PRCM_HOSC_TYPE_52M);
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HAL_PRCM_SetSysPLL(PRCM_SYS_PLL_PARAM_HOSC52M);
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#else
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#error "Invalid HOSC value!"
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#endif
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#ifndef CONFIG_BOOTLOADER
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lfclk_init();
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#endif
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HAL_PRCM_SetCPUAClk(BOARD_CPU_CLK_SRC, BOARD_CPU_CLK_FACTOR);
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HAL_PRCM_SetDevClock(BOARD_DEV_CLK_FACTOR);
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HAL_CCM_BusSetClock(BOARD_AHB2_CLK_DIV, BOARD_APB_CLK_SRC, BOARD_APB_CLK_DIV);
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#ifdef CONFIG_PSRAM
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#if (CONFIG_CHIP_ARCH_VER == 2)
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HAL_PRCM_SetDev2Clock(BOARD_DEV2_CLK_FACTOR);
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HAL_PRCM_EnableDev2Clock();
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#endif
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#endif
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#if (CONFIG_CHIP_ARCH_VER > 1)
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HAL_CCM_BusSetAPBSClock(BOARD_APBS_CLK_SRC, BOARD_APBS_CLK_FACTOR);
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#endif
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}
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static GPIO_PinMuxParam g_pinmux_flashc_sip[] = {
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{ GPIO_PORT_B, GPIO_PIN_8, { GPIOB_P8_F2_FLASH_WP, GPIO_DRIVING_LEVEL_3, GPIO_PULL_UP } },
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{ GPIO_PORT_B, GPIO_PIN_9, { GPIOB_P9_F2_FLASH_HOLD, GPIO_DRIVING_LEVEL_3, GPIO_PULL_UP } },
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{ GPIO_PORT_B, GPIO_PIN_10, { GPIOB_P10_F2_FLASH_MOSI, GPIO_DRIVING_LEVEL_3, GPIO_PULL_NONE } },
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{ GPIO_PORT_B, GPIO_PIN_11, { GPIOB_P11_F2_FLASH_MISO, GPIO_DRIVING_LEVEL_3, GPIO_PULL_NONE } },
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{ GPIO_PORT_B, GPIO_PIN_12, { GPIOB_P12_F2_FLASH_CS1, GPIO_DRIVING_LEVEL_3, GPIO_PULL_UP } },
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{ GPIO_PORT_B, GPIO_PIN_13, { GPIOB_P13_F2_FLASH_CLK, GPIO_DRIVING_LEVEL_3, GPIO_PULL_NONE } },
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};
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#ifdef CONFIG_PSRAM
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#if (CONFIG_CHIP_ARCH_VER == 2)
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static GPIO_PinMuxParam g_pinmux_psram_sip[] = {
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#if (defined CONFIG_PSRAM_CHIP_SQPI)
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{ GPIO_PORT_C, GPIO_PIN_4, { GPIOC_P4_F4_PSRAM_SIO3, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_5, { GPIOC_P5_F4_PSRAM_CLK, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_7, { GPIOC_P7_F4_PSRAM_CE, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_9, { GPIOC_P9_F4_PSRAM_SIO1, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_10, { GPIOC_P10_F4_PSRAM_SIO2, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_11, { GPIOC_P11_F4_PSRAM_SIO0, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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#elif (defined CONFIG_PSRAM_CHIP_OPI32)
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{ GPIO_PORT_C, GPIO_PIN_0, { GPIOC_P0_F2_PSRAM_DM, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_1, { GPIOC_P1_F2_PSRAM_DQ0, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_2, { GPIOC_P2_F2_PSRAM_DQ1, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_3, { GPIOC_P3_F2_PSRAM_DQ2, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_4, { GPIOC_P4_F2_PSRAM_DQ3, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_5, { GPIOC_P5_F2_PSRAM_CE, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_6, { GPIOC_P6_F2_PSRAM_CLK_N, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_7, { GPIOC_P7_F2_PSRAM_CLK, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_8, { GPIOC_P8_F2_PSRAM_DQ4, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_9, { GPIOC_P9_F2_PSRAM_DQ5, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_10, { GPIOC_P10_F2_PSRAM_DQ6, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_11, { GPIOC_P11_F2_PSRAM_DQ7, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_12, { GPIOC_P12_F2_PSRAM_DQS, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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#elif (defined CONFIG_PSRAM_CHIP_OPI64)
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{ GPIO_PORT_C, GPIO_PIN_0, { GPIOC_P0_F3_PSRAM_DQS, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_1, { GPIOC_P1_F3_PSRAM_DQ7, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_2, { GPIOC_P2_F3_PSRAM_DQ6, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_3, { GPIOC_P3_F3_PSRAM_DQ5, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_4, { GPIOC_P4_F3_PSRAM_DQ4, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_5, { GPIOC_P5_F3_PSRAM_CLK, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_7, { GPIOC_P7_F3_PSRAM_CE, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_8, { GPIOC_P8_F3_PSRAM_DQ3, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_9, { GPIOC_P9_F3_PSRAM_DQ2, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_10, { GPIOC_P10_F3_PSRAM_DQ1, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_C, GPIO_PIN_11, { GPIOC_P11_F3_PSRAM_DQ0, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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#endif
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};
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#elif (CONFIG_CHIP_ARCH_VER == 3)
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static const GPIO_PinMuxParam g_pinmux_psram_sip[] = {
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{ GPIO_PORT_B, GPIO_PIN_8, { GPIOB_P8_F2_FLASH_WP, GPIO_DRIVING_LEVEL_1, GPIO_PULL_UP } },
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{ GPIO_PORT_B, GPIO_PIN_9, { GPIOB_P9_F2_FLASH_HOLD, GPIO_DRIVING_LEVEL_1, GPIO_PULL_UP } },
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{ GPIO_PORT_B, GPIO_PIN_10, { GPIOB_P10_F2_FLASH_MOSI, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_B, GPIO_PIN_11, { GPIOB_P11_F2_FLASH_MISO, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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{ GPIO_PORT_B, GPIO_PIN_12, { GPIOB_P12_F2_FLASH_CS1, GPIO_DRIVING_LEVEL_1, GPIO_PULL_UP } },
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{ GPIO_PORT_B, GPIO_PIN_13, { GPIOB_P13_F2_FLASH_CLK, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE } },
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};
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#endif /*CONFIG_CONFIG_CHIP_ARCH_VER */
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#endif /* CONFIG_PSRAM */
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HAL_Status board_get_flashc_sip_pinmux_cfg(const GPIO_PinMuxParam **param,
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uint32_t *count)
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{
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if (HAL_PRCM_IsFlashSip()) {
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*param = g_pinmux_flashc_sip;
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*count = HAL_ARRAY_SIZE(g_pinmux_flashc_sip);
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return HAL_OK;
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} else {
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return HAL_ERROR;
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}
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}
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#ifdef CONFIG_PSRAM
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HAL_Status board_get_psram_sip_pinmux_cfg(const GPIO_PinMuxParam **param,
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uint32_t *count)
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{
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if (0) {
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//if (HAL_PRCM_IsPsramSip()) {
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*param = g_pinmux_psram_sip;
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*count = HAL_ARRAY_SIZE(g_pinmux_psram_sip);
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return HAL_OK;
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} else {
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return HAL_ERROR;
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}
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}
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#endif
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