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sdk-hwV1.3/lichee/linux-4.9/arch/arm/boot/dts/sun8iw21p1.dtsi

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/*
* Allwinner Technology CO., Ltd. sun8iw19p1 platform
*
* modify base on juno.dts
*/
/* kernel used */
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include "sun8iw21p1-clk.dtsi"
#include "sun8iw21p1-pinctrl.dtsi"
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/power/v853-power.h>
/ {
model = "sun8iw21";
compatible = "allwinner,sun8iw21p1";
interrupt-parent = <&wakeupgen>;
#address-cells = <2>;
#size-cells = <2>;
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
optee_reserve {
reg = <0 0x41980000 0 0x00019000>;
status = "okay";
};
/*
npu_reserve {
reg = <0 0x42000000 0 0x12C00000>;
no-map;
status = "okay";
};
*/
};
aliases {
pwm = &pwm;
pwm0 = &pwm0;
pwm1 = &pwm1;
pwm2 = &pwm2;
pwm3 = &pwm3;
pwm4 = &pwm4;
pwm5 = &pwm5;
pwm6 = &pwm6;
pwm7 = &pwm7;
pwm8 = &pwm8;
pwm9 = &pwm9;
pwm10 = &pwm10;
pwm11 = &pwm11;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
spi3 = &spi3;
spif0 = &spif0;
disp = &disp;
lcd0 = &lcd0;
mmc0 = &sdc0;
mmc2 = &sdc2;
twi0 = &twi0;
twi1 = &twi1;
twi2 = &twi2;
twi3 = &twi3;
twi4 = &twi4;
gmac0 = &gmac0;
};
chosen {
bootargs = "earlyprintk=sunxi-uart,0x02500000 loglevel=8 initcall_debug=0 console=ttyS0 init=/init";
linux,initrd-start = <0x0 0x0>;
linux,initrd-end = <0x0 0x0>;
};
cpus {
enable-method = "allwinner,sun8iw21p1";
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
enable-method = "psci";
vf_tbl_sel = <0>;
clocks = <&clk_pll_cpu>;
clock-frequency = <1008000000>;
clock-latency = <2000000>;
/* if divide bin <&cpu_opp_l_table0 &cpu_opp_l_table1> */
operating-points-v2 = <&cpu_opp_l_table0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
cooling-min-level = <5>;
cooling-max-level = <0>;
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <142>;
};
idle-states {
entry-method = "arm,psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <45>;
exit-latency-us = <90>;
min-residency-us = <3000>;
local-timer-stop;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x1010000>;
entry-latency-us = <55>;
exit-latency-us = <570>;
min-residency-us = <17000>;
local-timer-stop;
};
SYS_SLEEP_0: sys-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x2010000>;
entry-latency-us = <0xffffffff>;
exit-latency-us = <0xffffffff>;
min-residency-us = <0xffffffff>;
local-timer-stop;
};
};
};
cpu_opp_l_table0: opp_l_table0 {
/* compatible = "operating-points-v2"; */
compatible = "allwinner,sun50i-operating-points";
nvmem-cells = <&cpubin_efuse>;
nvmem-cell-names = "bin";
opp-shared;
/* compatible = "allwinner,opp_l_table0"; */
opp@408000000-92 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <920000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x42B>;
};
opp@408000000-96 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <960000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0xA54>;
};
opp@408000000-100 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x80>;
};
opp@408000000-105 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <1050000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x100>;
};
opp@600000000-92 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <920000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x42B>;
};
opp@600000000-96 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <960000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0xA54>;
};
opp@600000000-100 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x80>;
};
opp@600000000-105 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1050000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x100>;
};
opp@720000000-92 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <920000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x42B>;
};
opp@720000000-96 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <960000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0xA54>;
};
opp@720000000-100 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x80>;
};
opp@720000000-105 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <1050000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x100>;
};
opp@900000000-92 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <920000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x42B>;
};
opp@900000000-96 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <960000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0xA54>;
};
opp@900000000-100 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x80>;
};
opp@900000000-105 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <1050000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x100>;
};
opp@1008000000-96 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <960000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0xE54>;
};
opp@1008000000-100 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x80>;
};
opp@1008000000-105 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1050000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x100>;
};
opp@1104000000-100 {
opp-hz = /bits/ 64 <1104000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0xC80>;
};
opp@1104000000-105 {
opp-hz = /bits/ 64 <1104000000>;
opp-microvolt = <1050000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x100>;
};
opp@1200000000-100 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x80>;
};
opp@1200000000-105 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1050000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x100>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
e907_rproc: e907_rproc@0 {
compatible = "allwinner,sun8iw21p1-e907-rproc";
clock-frequency = <600000000>;
clocks = <&clk_pll_periph0600m>, <&clk_e907>, <&clk_e907_axi>,
<&clk_e907_gate>, <&clk_msgbox1>;
clock-names = "pll", "clk", "axi", "gate", "mbox";
reg = <0x0 0x06010204 0x0 0x04>;
reg-names = "riscv-addr";
device_name = "e907_rproc@0";
mboxes = <&msgbox 0>;
mbox-names = "mbox-chan";
core-name = "allwinner,riscv-e907";
firmware-name = "melis-elf";
status = "disabled";
};
ion {
compatible = "allwinner,sunxi-ion";
/*
*types list here:
ION_HEAP_TYPE_SYSTEM = 0,
ION_HEAP_TYPE_SYSTEM_CONTIG = 1,
ION_HEAP_TYPE_CARVEOUT = 2,
ION_HEAP_TYPE_CHUNK = 3,
ION_HEAP_TYPE_DMA = 4,
ION_HEAP_TYPE_SECURE = 6,
**/
heap_sys_user@0{
compatible = "allwinner,sys_user";
heap-name = "sys_user";
heap-id = <0x0>;
heap-base = <0x0>;
heap-size = <0x0>;
heap-type = "ion_system";
};
heap_cma@0{
compatible = "allwinner,cma";
heap-name = "cma";
heap-id = <0x4>;
heap-base = <0x0>;
heap-size = <0x0>;
heap-type = "ion_cma";
};
};
memory@40000000 {
device_type = "memory";
reg = <0x00000000 0x40000000 0x00000000 0x20000000>;
};
gic: interrupt-controller@03020000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
device_type = "gic";
interrupt-controller;
reg = <0x0 0x03021000 0 0x1000>, /* GIC Dist */
<0x0 0x03022000 0 0x2000>, /* GIC CPU */
<0x0 0x03024000 0 0x2000>, /* GIC VCPU Control */
<0x0 0x03026000 0 0x2000>; /* GIC VCPU */
interrupts = <GIC_PPI 9 0xf04>; /* GIC Maintenence IRQ */
interrupt-parent = <&gic>;
};
nmi_intc: intc-nmi@07010320 {
compatible = "allwinner,sun8i-nmi";
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0x07010320 0 0xc>;
pad-control-v2 = <0x07090230>;
pad-control-offset = <30>;
pad-control-en = <0>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
};
wakeupgen: interrupt-controller@0 {
compatible = "allwinner,sunxi-wakeupgen";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
};
sram_ctrl {
device_type = "sram_ctrl";
compatible = "allwinner,sram_ctrl";
reg = <0x0 0x03000000 0x0 0x100>;
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, /* Secure Phys IRQ */
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, /* Non-secure Phys IRQ */
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, /* Virt IRQ */
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; /* Hyp IRQ */
clock-frequency = <24000000>;
arm,cpu-registers-not-fw-configured;
interrupt-parent = <&gic>;
arm,no-tick-in-suspend;
};
ths: ths@02009400 {
compatible = "allwinner,sun8iw21p1-ths";
reg = <0x0 0x02009400 0x0 0x400>;
clocks = <&clk_ths>;
clock-names = "bus";
nvmem-cells = <&ths_calib>;
nvmem-cell-names = "calibration";
#thermal-sensor-cells = <1>;
};
thermal-zones {
cpu_thermal_zone {
polling-delay-passive = <500>;
polling-delay = <1000>;
thermal-sensors = <&ths 2>;
sustainable-power = <68>;
cpu_trips: trips {
cpu_threshold: trip-point@0 {
temperature = <70000>;
type = "passive";
hysteresis = <0>;
};
cpu_target: trip-point@1 {
temperature = <90000>;
type = "passive";
hysteresis = <0>;
};
cpu_crit: cpu_crit@0 {
temperature = <110000>;
type = "critical";
hysteresis = <0>;
};
};
cooling-maps {
map0 {
trip = <&cpu_target>;
cooling-device = <&cpu0
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
};
npu_thermal_zone {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&ths 0>;
};
ve_thermal_zone {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&ths 1>;
};
};
pmu: power-management@ff000000 {
compatible = "allwinner,v853-pmu", "syscon", "simple-mfd";
reg = <0x0 0x07001000 0x0 0x400>;
pd: power-controller {
compatible = "allwinner,v853-power-controller";
clocks = <&clk_cpurppu>;
clock-names = "ppu";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* These power domains are grouped by VD_LOGIC */
pd_e907@V853_PD_E907 {
reg = <V853_PD_E907>;
};
pd_npu@V853_PD_NPU {
reg = <V853_PD_NPU>;
};
pd_ve@V853_PD_VE {
reg = <V853_PD_VE>;
};
};
};
soc: soc@03000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
device_type = "soc";
isp_boot0_gpio:isp_boot0_gpio@0 {
device_type = "isp_boot0_gpio";
/* port:0x3--D 0xFF--no use
* pin:0x5--5
* mul_sel:0x1
* pull:0xffffffff -- default
* drv_level:0xffffffff
* data:0x0
*/
camera0_cut0 = <0x54 0x3 0x12 0x1 0x0 0x1 0x0>;
camera0_cut1 = <0x54 0x3 0x8 0x1 0x0 0x1 0x0>;
camera0_led = <0x54 0xFF 0xFF 0x1 0x0 0x1 0x0>;
camera1_cut0 = <0x54 0x3 0x12 0x1 0x0 0x1 0x0>;
camera1_cut1 = <0x54 0x3 0x8 0x1 0x0 0x1 0x0>;
camera1_led = <0x54 0xFF 0xFF 0x1 0x0 0x1 0x0>;
};
soc_timer0: timer@02050000 {
compatible = "allwinner,sun4i-a10-timer";
device_type = "soc_timer";
reg = <0x0 0x02050000 0x0 0x90>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
/* On FPGA, timer can only use the losc.
* On IC, timer should use the hosc.
*/
clocks = <&clk_hosc>, <&clk_losc>;
};
wdt: watchdog@20500a0 {
compatible = "allwinner,sun8i-wdt";
reg = <0x0 0x020500a0 0x0 0x20>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
};
dump_reg:dump_reg@20000 {
compatible = "allwinner,sunxi-dump-reg";
reg = <0x0 0x000020000 0x0 0x0004>;
};
hwspinlock: hwspinlock@3005000 {
compatible = "allwinner,sunxi-hwspinlock";
reg = <0x0 0x3005000 0x0 0x1000>;
#hwlock-cells = <1>;
clocks = <&clk_spinlock>;
num-locks = <32>;
status = "okay";
};
uart0: uart@2500000 {
compatible = "allwinner,sun8i-uart";
device_type = "uart0";
reg = <0x0 0x02500000 0x0 0x400>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart0>;
sunxi,uart-fifosize = <64>;
uart0_port = <0>;
uart0_type = <2>;
status = "disabled";
};
uart1: uart@2500400 {
compatible = "allwinner,sun8i-uart";
device_type = "uart1";
reg = <0x0 0x02500400 0x0 0x400>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart1>;
sunxi,uart-fifosize = <128>;
uart1_port = <1>;
uart1_type = <4>;
status = "disabled";
};
uart2: uart@2500800 {
compatible = "allwinner,sun8i-uart";
device_type = "uart2";
reg = <0x0 0x02500800 0x0 0x400>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart2>;
sunxi,uart-fifosize = <128>;
uart2_port = <2>;
uart2_type = <4>;
status = "disabled";
};
uart3: uart@2500c00 {
compatible = "allwinner,sun8i-uart";
device_type = "uart3";
reg = <0x0 0x02500c00 0x0 0x400>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart3>;
sunxi,uart-fifosize = <128>;
uart3_port = <3>;
uart3_type = <4>;
status = "disabled";
};
npu: npu@03050000 {
compatible = "allwinner,npu";
reg = <0x0 0x03050000 0x0 0x1000>;
device_type = "npu";
dev_name = "npu";
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_npu>,
<&clk_pll_npux4>;
clock-frequency = <504000000>;
interrupt-names = "npu";
iommus = <&mmu_aw 6 1>;
status = "okay";
power-domains = <&pd V853_PD_NPU>;
};
pinctrl_test: pinctrl-test@0 {
compatible = "allwinner,sun8i-pinctrl-test";
device_type = "pinctrl-test";
interrupt-parent = <&pio>;
interrupts = <PA 2 IRQ_TYPE_LEVEL_HIGH>; /* bank offset type */
pinctrl-names = "default";
pinctrl-0 = <&test_pins_active>;
test-gpios = <&pio PA 3 1 2 2 1>;
status = "okay";
};
rt-media@01c0e000 {
compatible = "allwinner,rt-media";
};
ve: ve@01c0e000 {
compatible = "allwinner,sunxi-cedar-ve";
reg = <0x0 0x01c0e000 0x0 0x1000>,/*ve*/
<0x0 0x03000000 0x0 0x10>, /*sys_cfg*/
<0x0 0x02001000 0x0 0x800>, /*ccmu*/
<0x0 0x05830000 0x0 0x1000>,/*csi*/
<0x0 0x03006200 0x0 0x4>;/*ve ic markid*/
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_periph0400m>, <&clk_ve>;
iommus = <&mmu_aw 0 1>;
power-domains = <&pd V853_PD_VE>;
};
mmu_aw: iommu@02010000 {
compatible = "allwinner,sunxi-iommu";
reg = <0x0 0x02010000 0x0 0x400>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "iommu-irq";
clocks = <&clk_iommu>;
clock-names = "iommu";
iova-base = <0x48400000>;
/*clock-frequency = <24000000>; */
#iommu-cells = <2>;
status = "okay";
};
mbus0: mbus-controller@0x3102000 {
compatible = "allwinner,sun8i-mbus";
reg = <0x0 0x03102000 0x0 0x1000>;
#mbus-cells = <1>;
};
cryptoengine: ce@03040000 {
compatible = "allwinner,sunxi-ce";
device_name = "ce";
reg = <0x0 0x03040000 0x0 0xa0>,
<0x0 0x03040800 0x0 0xa0>; /* Unused */
interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 53 IRQ_TYPE_EDGE_RISING>; /* Unused */
clocks = <&clk_ce>, <&clk_pll_periph0400m>;
};
spi0: spi@04025000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-spi";
device_type = "spi0";
reg = <0x0 0x04025000 0x0 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_periph0300m>, <&clk_spi0>;
status = "disabled";
};
spi1: spi@04026000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-spi";
device_type = "spi-dbi";
reg = <0x0 0x04026000 0x0 0x1000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_periph0300m>, <&clk_spi1>;
status = "disabled";
};
spi2: spi@04027000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-spi";
device_type = "spi2";
reg = <0x0 0x04027000 0x0 0x1000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_periph0300m>, <&clk_spi2>;
status = "disabled";
};
spi3: spi@04028000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-spi";
device_type = "spi3";
reg = <0x0 0x04028000 0x0 0x1000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_periph0300m>, <&clk_spi3>;
status = "disabled";
};
spif0: spif@04f00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-spif";
device_type = "spif";
reg = <0x0 0x04f00000 0x0 0x1000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_periph0400m>, <&clk_spif>;
clock-names = "pclk", "mclk";
status = "disabled";
};
msgbox: msgbox@3003000 {
compatible = "allwinner,sunxi-msgbox";
#mbox-cells = <1>;
reg = <0x0 0x03003000 0x0 0x1000>,
<0x0 0x06020000 0x0 0x1000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_msgbox0>;
clock-names = "msgbox0";
local_id = <0>;
status = "disabled";
};
twi0: twi@0x02502000{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-twi";
device_type = "twi0";
reg = <0x0 0x02502000 0x0 0x400>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi0>;
dmas = <&dma0 43>, <&dma0 43>;
dma-name = "tx", "rx";
status = "disabled";
};
twi1: twi@0x02502400{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-twi";
device_type = "twi1";
reg = <0x0 0x02502400 0x0 0x400>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi1>;
dmas = <&dma0 44>, <&dma0 44>;
dma-name = "tx", "rx";
status = "disabled";
};
twi2: twi@0x02502800{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun50i-twi";
device_type = "twi2";
reg = <0x0 0x02502800 0x0 0x400>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma0 45>, <&dma0 45>;
dma-name = "tx", "rx";
clocks = <&clk_twi2>;
status = "disabled";
};
twi3: twi@0x02502c00{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-twi";
device_type = "twi3";
reg = <0x0 0x02502c00 0x0 0x400>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma0 46>, <&dma0 46>;
dma-name = "tx", "rx";
clocks = <&clk_twi3>;
status = "disabled";
};
twi4: twi@0x02503000{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-twi";
device_type = "twi4";
reg = <0x0 0x02503000 0x0 0x400>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi4>;
dmas = <&dma0 47>, <&dma0 47>;
dma-name = "tx", "rx";
status = "disabled";
};
dma0: dma-controller@03002000 {
compatible = "allwinner,sun8i-dma";
reg = <0x0 0x03002000 0x0 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
};
pwm: pwm@2000c00 {
compatible = "allwinner,sunxi-pwm";
reg = <0x0 0x02000c00 0x0 0x3f0>;
clocks = <&clk_pwm>;
pwm-number = <12>;
pwm-base = <0>;
pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>,
<&pwm4>, <&pwm5>, <&pwm6>, <&pwm7>, <&pwm8>, <&pwm9>,
<&pwm10>, <&pwm11>;
};
pwm0: pwm0@2000c10 {
compatible = "allwinner,sunxi-pwm0";
reg = <0x0 0x02000c10 0x0 0x4>;
reg_base = <0x02000c00>;
};
pwm1: pwm1@2000c11 {
compatible = "allwinner,sunxi-pwm1";
reg = <0x0 0x02000c11 0x0 0x4>;
reg_base = <0x02000c00>;
};
pwm2: pwm2@2000c12 {
compatible = "allwinner,sunxi-pwm2";
reg = <0x0 0x02000c12 0x0 0x4>;
reg_base = <0x02000c00>;
};
pwm3: pwm3@2000c13 {
compatible = "allwinner,sunxi-pwm3";
reg = <0x0 0x02000c13 0x0 0x4>;
reg_base = <0x02000c00>;
};
pwm4: pwm4@2000c14 {
compatible = "allwinner,sunxi-pwm4";
reg = <0x0 0x02000c14 0x0 0x4>;
reg_base = <0x02000c00>;
};
pwm5: pwm5@2000c15 {
compatible = "allwinner,sunxi-pwm5";
reg = <0x0 0x02000c15 0x0 0x4>;
reg_base = <0x02000c00>;
};
pwm6: pwm6@2000c16 {
compatible = "allwinner,sunxi-pwm6";
reg = <0x0 0x02000c16 0x0 0x4>;
reg_base = <0x02000c00>;
};
pwm7: pwm7@2000c17 {
compatible = "allwinner,sunxi-pwm7";
reg = <0x0 0x02000c17 0x0 0x4>;
reg_base = <0x02000c00>;
};
pwm8: pwm8@2000c18 {
compatible = "allwinner,sunxi-pwm8";
reg = <0x0 0x02000c18 0x0 0x4>;
reg_base = <0x02000c00>;
};
pwm9: pwm9@2000c19 {
compatible = "allwinner,sunxi-pwm9";
reg = <0x0 0x02000c19 0x0 0x4>;
reg_base = <0x02000c00>;
};
pwm10: pwm10@2000c1a {
compatible = "allwinner,sunxi-pwm10";
reg = <0x0 0x02000c1a 0x0 0x4>;
reg_base = <0x02000c00>;
};
pwm11: pwm11@2000c1b {
compatible = "allwinner,sunxi-pwm11";
reg = <0x0 0x02000c1b 0x0 0x4>;
reg_base = <0x02000c00>;
};
sid@3006000 {
compatible = "allwinner,sun8iw21p1-sid", "allwinner,sunxi-sid";
reg = <0x0 0x03006000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ths_calib: calib@14 {
reg = <0x14 8>;
};
cpubin_efuse: bin@18 {
reg = <0x18 4>;
};
};
chipid: sunxi-chipid@03006200 {
compatible = "allwinner,sunxi-chipid";
device_type = "chipid";
reg = <0x0 0x03006200 0 0xC0>;
};
gpadc:gpadc@2009000 {
compatible = "allwinner,sunxi-gpadc";
reg = <0x0 0x02009000 0x0 0x400>;
interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
clocks = <&clk_gpadc>;
status = "disabled";
};
sdc2: sdmmc@4022000 {
compatible = "allwinner,sunxi-mmc-v4p6x";
device_type = "sdc2";
reg = <0x0 0x04022000 0x0 0x1000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_hosc>,
<&clk_pll_periph0600m>,
<&clk_sdmmc2_mod>,
<&clk_sdmmc2_bus>,
<&clk_sdmmc2_rst>;
clock-names = "osc24m","pll_periph","mmc","ahb","rst";
pinctrl-names = "default","sleep";
pinctrl-0 = <&sdc2_pins_a &sdc2_pins_c>;
pinctrl-1 = <&sdc2_pins_b>;
bus-width = <8>;
req-page-count = <2>;
cap-mmc-highspeed;
cap-cmd23;
mmc-cache-ctrl;
non-removable;
/*max-frequency = <200000000>;*/
max-frequency = <50000000>;
cap-erase;
mmc-high-capacity-erase-size;
no-sdio;
no-sd;
/*-- speed mode --*/
/*sm0: DS26_SDR12*/
/*sm1: HSSDR52_SDR25*/
/*sm2: HSDDR52_DDR50*/
/*sm3: HS200_SDR104*/
/*sm4: HS400*/
/*-- frequency point --*/
/*f0: CLK_400K*/
/*f1: CLK_25M*/
/*f2: CLK_50M*/
/*f3: CLK_100M*/
/*f4: CLK_150M*/
/*f5: CLK_200M*/
sdc_tm4_sm0_freq0 = <0>;
sdc_tm4_sm0_freq1 = <0>;
sdc_tm4_sm1_freq0 = <0x00000000>;
sdc_tm4_sm1_freq1 = <0>;
sdc_tm4_sm2_freq0 = <0x00000000>;
sdc_tm4_sm2_freq1 = <0>;
sdc_tm4_sm3_freq0 = <0x05000000>;
sdc_tm4_sm3_freq1 = <0x00000005>;
sdc_tm4_sm4_freq0 = <0x00050000>;
sdc_tm4_sm4_freq1 = <0x00000004>;
sdc_tm4_sm4_freq0_cmd = <0>;
sdc_tm4_sm4_freq1_cmd = <0>;
ctl-spec-caps = <0x308>;
/*vmmc-supply = <&reg_3p3v>;*/
/*vqmc-supply = <&reg_3p3v>;*/
/*vdmc-supply = <&reg_3p3v>;*/
/*vmmc = "vcc-card";*/
/*vqmc = "";*/
/*vdmc = "";*/
/*sunxi-power-save-mode;*/
status = "disabled";
};
sdc0: sdmmc@4020000 {
compatible = "allwinner,sunxi-mmc-v5p3x";
device_type = "sdc0";
reg = <0x0 0x04020000 0x0 0x1000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_hosc>,
<&clk_pll_periph0300m>,
<&clk_sdmmc0_mod>,
<&clk_sdmmc0_bus>,
<&clk_sdmmc0_rst>;
clock-names = "osc24m","pll_periph","mmc","ahb","rst";
pinctrl-names = "default","sleep","uart_jtag";
pinctrl-0 = <&sdc0_pins_a>;
pinctrl-1 = <&sdc0_pins_b>;
pinctrl-2 = <&sdc0_pins_c>;
max-frequency = <50000000>;
bus-width = <4>;
ctl-spec-caps = <0x8>;
/*non-removable;*/
/*broken-cd;*/
/*cd-inverted*/
/*cd-gpios = <&pio PF 6 GPIO_ACTIVE_LOW>;*/
/* vmmc-supply = <&reg_3p3v>;*/
/* vqmc-supply = <&reg_3p3v>;*/
/* vdmc-supply = <&reg_3p3v>;*/
/*vmmc = "vcc-card";*/
/*vqmc = "";*/
/*vdmc = "";*/
cap-sd-highspeed;
cap-wait-while-busy;
no-sdio;
no-mmc;
/*sd-uhs-sdr50;*/
/*sd-uhs-ddr50;*/
/*cap-sdio-irq;*/
/*keep-power-in-suspend;*/
/*ignore-pm-notify;*/
/*sunxi-power-save-mode;*/
/*sunxi-dly-400k = <1 0 0 0>; */
/*sunxi-dly-26M = <1 0 0 0>;*/
/*sunxi-dly-52M = <1 0 0 0>;*/
/*sunxi-dly-52M-ddr4 = <1 0 0 0>;*/
/*sunxi-dly-52M-ddr8 = <1 0 0 0>;*/
/*sunxi-dly-104M = <1 0 0 0>;*/
sunxi-dly-208M = <1 1 0 0 0 0>;
/*sunxi-dly-104M-ddr = <1 0 0 0>;*/
/*sunxi-dly-208M-ddr = <1 0 0 0>;*/
status = "disabled";
};
sdc1: sdmmc@04021000 {
compatible = "allwinner,sunxi-mmc-v5p3x";
device_type = "sdc1";
reg = <0x0 0x04021000 0x0 0x1000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_hosc>,
<&clk_pll_periph0300m>,
<&clk_sdmmc1_mod>,
<&clk_sdmmc1_bus>,
<&clk_sdmmc1_rst>;
clock-names = "osc24m","pll_periph","mmc","ahb","rst";
pinctrl-names = "default","sleep";
pinctrl-0 = <&sdc1_pins_a>;
pinctrl-1 = <&sdc1_pins_b>;
max-frequency = <50000000>;
bus-width = <4>;
ctl-spec-caps = <0x8>;
/*broken-cd;*/
/*cd-inverted*/
/*cd-gpios = <&pio PG 6 6 1 2 0>;*/
/* vmmc-supply = <&reg_3p3v>;*/
/* vqmc-supply = <&reg_3p3v>;*/
/* vdmc-supply = <&reg_3p3v>;*/
/*vmmc = "vcc-card";*/
/*vqmc = "";*/
/*vdmc = "";*/
/*sd-uhs-sdr50;*/
/*sd-uhs-ddr50;*/
/*sd-uhs-sdr104;*/
cap-sd-highspeed;
cap-mmc-highspeed;
cap-wait-while-busy;
/*cap-sdio-irq;*/
/*keep-power-in-suspend;*/
/*ignore-pm-notify;*/
/*sunxi-power-save-mode;*/
/*sunxi-dly-400k = <1 0 0 0 0>; */
/*sunxi-dly-26M = <1 0 0 0 0>;*/
/*sunxi-dly-52M = <1 0 0 0 0>;*/
sunxi-dly-52M-ddr4 = <1 0 0 0 2>;
/*sunxi-dly-52M-ddr8 = <1 0 0 0 0>;*/
sunxi-dly-104M = <1 0 0 0 1>;
/*sunxi-dly-208M = <1 1 0 0 0>;*/
sunxi-dly-208M = <1 1 0 0 0 0>;
/*sunxi-dly-104M-ddr = <1 0 0 0 0>;*/
/*sunxi-dly-208M-ddr = <1 0 0 0 0>;*/
status = "disabled";
};
g2d: g2d@05410000 {
compatible = "allwinner,sunxi-g2d";
reg = <0x0 0x05410000 0x0 0xbffff>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_g2d>;
iommus = <&mmu_aw 3 1>;
status = "okay";
};
disp: disp@05000000 {
compatible = "allwinner,sunxi-disp";
reg = <0x0 0x05000000 0x0 0x00300000>,/*de*/
<0x0 0x05460000 0x0 0xfff>,/*disp top*/
<0x0 0x05461000 0x0 0x07fc>,/*tcon0*/
<0x0 0x05450000 0x0 0x10fc>;/*dsi*/
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;/* for dsi */
clocks = <&clk_de>,<&clk_dpss_top>,<&clk_tcon_lcd>,
<&clk_mipi_dsi>;
iommus = <&mmu_aw 2 0>;
boot_disp = <0>;
fb_base = <0>;
status = "okay";
};
lcd0: lcd0@05461000 {
compatible = "allwinner,sunxi-lcd0";
pinctrl-names = "active","sleep";
status = "okay";
};
usbc0:usbc0@0 {
device_type = "usbc0";
compatible = "allwinner,sunxi-otg-manager";
usb_port_type = <2>;
usb_detect_type = <1>;
usb_id_gpio;
usb_det_vbus_gpio;
usb_drv_vbus_gpio;
usb_host_init_state = <0>;
usb_regulator_io = "nocare";
usb_wakeup_suspend = <0>;
usb_luns = <3>;
usb_serial_unique = <0>;
usb_serial_number = "20080411";
rndis_wceis = <1>;
/* wakeup-source; */
status = "okay";
};
udc:udc-controller@0x4100000 {
compatible = "allwinner,sunxi-udc";
reg = <0x0 0x04100000 0x0 0x1000>,
<0x0 0x00000000 0x0 0x100>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy0>, <&clk_usbotg>;
status = "okay";
};
ehci0:ehci0-controller@0x4101000 {
compatible = "allwinner,sunxi-ehci0";
reg = <0x0 0x04101000 0x0 0xFFF>,
<0x0 0x00000000 0x0 0x100>,
<0x0 0x04100000 0x0 0x1000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy0>, <&clk_usbehci0>;
hci_ctrl_no = <0>;
status = "okay";
};
ohci0:ohci0-controller@0x4101400 {
compatible = "allwinner,sunxi-ohci0";
reg = <0x0 0x04101000 0x0 0xFFF>,
<0x0 0x00000000 0x0 0x100>,
<0x0 0x04100000 0x0 0x1000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy0>, <&clk_usbohci0>, <&clk_usbohci0_12m>,
<&clk_osc48m>, <&clk_hosc>, <&clk_losc>;
hci_ctrl_no = <0>;
status = "okay";
};
rtc: rtc@7090000 {
compatible = "allwinner,sunxi-rtc";
device_type = "rtc";
auto_switch;
wakeup-source;
reg = <0x0 0x07090000 0x0 0x1a0>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
gpr_offset = <0x100>;
gpr_len = <8>;
gpr_cur_pos = <6>;
};
codec_has:codec_has@0x02030000 {
#sound-dai-cells = <0>;
compatible = "has,has-snd-codec";
reg = <0x0 0x02030000 0x0 0x34C>;
clocks = <&clk_pll_audio>,
<&clk_codec_dac>,
<&clk_codec_adc>;
status = "disabled";
};
/* audio dirver module -> audio codec */
codec:codec@0x02030000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sunxi-snd-codec";
reg = <0x0 0x02030000 0x0 0x34C>;
clocks = <&clk_pll_audio>,
<&clk_codec_dac>,
<&clk_codec_adc>;
status = "disabled";
};
codec_plat:codec_plat {
#sound-dai-cells = <0>;
compatible = "allwinner,sunxi-snd-plat-aaudio";
playback-cma = <128>;
capture-cma = <128>;
tx-fifo-size = <128>;
rx-fifo-size = <128>;
dac-txdata = <0x02030020>;
adc-txdata = <0x02030040>;
status = "disabled";
};
codec_mach:codec_mach {
compatible = "allwinner,sunxi-snd-mach";
soundcard-mach,name = "audiocodec";
soundcard-mach,pin-switches = "MIC1", "MIC2", "LINEIN",
"LINEOUT", "SPK";
soundcard-mach,routing = "MIC1_PIN", "MIC1",
"MIC2_PIN", "MIC2",
"LINEINL_PIN", "LINEIN",
"LINEINR_PIN", "LINEIN",
"LINEOUT", "LINEOUTL_PIN",
"SPK", "LINEOUTL_PIN";
status = "disabled";
soundcard-mach,cpu {
sound-dai = <&codec_plat>;
};
soundcard-mach,codec {
/* pll freq = 24.576M or 22.5792M * pll-fs */
soundcard-mach,pll-fs = <1>;
sound-dai = <&codec>;
};
};
/* audio dirver module -> DMIC */
dmic_plat:dmic_plat@0x02031000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sunxi-snd-plat-dmic";
reg = <0x0 0x02031000 0x0 0x50>;
clocks = <&clk_pll_audio>, <&clk_dmic>;
capture-cma = <128>;
rx_fifo-size = <128>;
status = "disabled";
};
dmic_mach:dmic_mach{
compatible = "allwinner,sunxi-snd-mach";
soundcard-mach,name = "snddmic";
soundcard-mach,capture-only;
status = "disabled";
soundcard-mach,cpu {
sound-dai = <&dmic_plat>;
};
soundcard-mach,codec {
};
};
/* audio dirver module -> I2S/PCM */
daudio0_plat:daudio0_plat@0x02032000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sunxi-snd-plat-daudio";
reg = <0x0 0x02032000 0x0 0x7c>;
clocks = <&clk_pll_audio>, <&clk_i2s0>;
playback-cma = <128>;
capture-cma = <128>;
tx-fifo-size = <128>;
rx-fifo-size = <128>;
status = "disabled";
};
daudio0_mach:daudio0_mach{
compatible = "allwinner,sunxi-snd-mach";
soundcard-mach,format = "i2s";
soundcard-mach,name = "snddaudio0";
status = "disabled";
soundcard-mach,cpu {
sound-dai = <&daudio0_plat>;
};
soundcard-mach,codec {
};
};
daudio1_plat:daudio1_plat@0x02033000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sunxi-snd-plat-daudio";
reg = <0x0 0x02033000 0x0 0x7c>;
clocks = <&clk_pll_audio>, <&clk_i2s1>;
playback-cma = <128>;
capture-cma = <128>;
tx-fifo-size = <128>;
rx-fifo-size = <128>;
status = "disabled";
};
daudio1_mach:daudio1_mach{
compatible = "allwinner,sunxi-snd-mach";
soundcard-mach,format = "i2s";
soundcard-mach,name = "snddaudio1";
status = "disabled";
soundcard-mach,cpu {
sound-dai = <&daudio1_plat>;
};
soundcard-mach,codec {
};
};
/* audio dirver module -> END */
wiegand:wiegand@0x02020000 {
compatible = "allwinner,sunxi-wiegand";
reg = <0x0 0x02020000 0x0 0x200>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_wiegand>,<&clk_apb0>;
clock-names = "pclk", "wclk";
status = "disabled";
};
gmac0: eth@4500000 {
compatible = "allwinner,sunxi-gmac";
reg = <0x0 0x04500000 0x0 0x10000>,
<0x0 0x03000030 0x0 0x4>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gmacirq";
clocks = <&clk_gmac>, <&clk_gmac_25m>;
clock-names = "gmac", "ephy";
device_type = "gmac0";
gmac-power0;
gmac-power1;
gmac-power2;
status = "okay";
};
vind0:vind@0 {
compatible = "allwinner,sunxi-vin-media", "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
device_id = <0>;
vind0_clk = <300000000>;
reg = <0x0 0x05800800 0x0 0x200>,
<0x0 0x05800000 0x0 0x800>,
<0x0 0x05810000 0x0 0x100>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_csi_top>, <&clk_pll_csix4>,
<&clk_csi_master0>, <&clk_hosc>, <&clk_pll_csix4>,
<&clk_csi_master1>, <&clk_hosc>, <&clk_pll_csix4>,
<&clk_csi_master2>, <&clk_hosc>, <&clk_pll_csix4>,
<&clk_isp>,
<&clk_pll_periph0300m>, <&clk_pll_periph0400m>;
pinctrl-names = "mclk0-default","mclk0-sleep",
"mclk1-default","mclk1-sleep",
"mclk2-default","mclk2-sleep";
pinctrl-0 = <&csi_mclk0_pins_a>;
pinctrl-1 = <&csi_mclk0_pins_b>;
pinctrl-2 = <&csi_mclk1_pins_a>;
pinctrl-3 = <&csi_mclk1_pins_b>;
pinctrl-4 = <&csi_mclk2_pins_a>;
pinctrl-5 = <&csi_mclk2_pins_b>;
status = "okay";
csi0:csi@0 {
device_type = "csi0";
compatible = "allwinner,sunxi-csi";
reg = <0x0 0x05820000 0x0 0x1000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
device_id = <0>;
status = "okay";
};
csi1:csi@1 {
device_type = "csi1";
compatible = "allwinner,sunxi-csi";
reg = <0x0 0x05821000 0x0 0x1000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
device_id = <1>;
status = "okay";
};
csi2:csi@2 {
device_type = "csi2";
compatible = "allwinner,sunxi-csi";
reg = <0x0 0x05822000 0x0 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&ncsi_pins_a>;
pinctrl-1 = <&ncsi_pins_b>;
device_id = <2>;
status = "okay";
};
mipi0:mipi@0 {
compatible = "allwinner,sunxi-mipi";
reg = <0x0 0x05810100 0x0 0x100>,
<0x0 0x05811000 0x0 0x400>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "mipi0-default","mipi0-sleep",
"mipi1-4lane-default","mipi1-4lane-sleep";
pinctrl-0 = <&mipia_pins_a>;
pinctrl-1 = <&mipia_pins_b>;
pinctrl-2 = <&mipib_4lane_pins_a>;
pinctrl-3 = <&mipib_4lane_pins_b>;
device_id = <0>;
status = "okay";
};
mipi1:mipi@1 {
compatible = "allwinner,sunxi-mipi";
reg = <0x0 0x05810200 0x0 0x100>,
<0x0 0x05811400 0x0 0x400>;
pinctrl-names = "mipi1-default","mipi1-sleep";
pinctrl-0 = <&mipib_pins_a>;
pinctrl-1 = <&mipib_pins_b>;
device_id = <1>;
status = "okay";
};
tdm0:tdm@0 {
compatible = "allwinner,sunxi-tdm";
reg = <0x0 0x05908000 0x0 0x340>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
device_id = <0>;
work_mode = <0>;
iommus = <&mmu_aw 4 1>;
status = "okay";
};
isp00:isp@0 {
compatible = "allwinner,sunxi-isp";
reg = <0x0 0x05900000 0x0 0x1300>,
<0x0 0x03000000 0x0 0x10>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
work_mode = <0>;
device_id = <0>;
iommus = <&mmu_aw 4 1>;
status = "okay";
};
isp01:isp@1 {
compatible = "allwinner,sunxi-isp";
reg = <0x0 0x058ffffc 0x0 0x1304>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
work_mode = <0xff>;
device_id = <1>;
iommus = <&mmu_aw 4 1>;
status = "okay";
};
isp02:isp@2 {
compatible = "allwinner,sunxi-isp";
reg = <0x0 0x058ffff8 0x0 0x1308>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
work_mode = <0xff>;
device_id = <2>;
iommus = <&mmu_aw 4 1>;
status = "okay";
};
isp03:isp@3 {
compatible = "allwinner,sunxi-isp";
reg = <0x0 0x058ffff4 0x0 0x130c>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
work_mode = <0xff>;
device_id = <3>;
iommus = <&mmu_aw 4 1>;
status = "okay";
};
isp10:isp@4 {
compatible = "allwinner,sunxi-isp";
device_id = <4>;
iommus = <&mmu_aw 4 1>;
status = "okay";
};
scaler00:scaler@0 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x05910000 0x0 0x400>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
work_mode = <0>;
device_id = <0>;
iommus = <&mmu_aw 1 1>;
status = "okay";
};
scaler01:scaler@1 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x0590fffc 0x0 0x404>;
work_mode = <0xff>;
device_id = <1>;
iommus = <&mmu_aw 1 1>;
status = "okay";
};
scaler02:scaler@2 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x0590fff8 0x0 0x408>;
work_mode = <0xff>;
device_id = <2>;
iommus = <&mmu_aw 1 1>;
status = "okay";
};
scaler03:scaler@3 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x0590fff4 0x0 0x40c>;
work_mode = <0xff>;
device_id = <3>;
iommus = <&mmu_aw 1 1>;
status = "okay";
};
scaler10:scaler@4 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x05910400 0x0 0x400>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
work_mode = <0>;
device_id = <4>;
iommus = <&mmu_aw 1 1>;
status = "okay";
};
scaler11:scaler@5 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x059103fc 0x0 0x404>;
work_mode = <0xff>;
device_id = <5>;
iommus = <&mmu_aw 1 1>;
status = "okay";
};
scaler12:scaler@6 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x059103f8 0x0 0x408>;
work_mode = <0xff>;
device_id = <6>;
iommus = <&mmu_aw 1 1>;
status = "okay";
};
scaler13:scaler@7 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x059103f4 0x0 0x40c>;
work_mode = <0xff>;
device_id = <7>;
iommus = <&mmu_aw 1 1>;
status = "okay";
};
scaler20:scaler@8 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x05910800 0x0 0x400>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
work_mode = <0>;
device_id = <8>;
iommus = <&mmu_aw 1 1>;
status = "okay";
};
scaler21:scaler@9 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x059107fc 0x0 0x404>;
work_mode = <0xff>;
device_id = <9>;
iommus = <&mmu_aw 1 1>;
status = "okay";
};
scaler22:scaler@10 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x059107f8 0x0 0x408>;
work_mode = <0xff>;
device_id = <10>;
iommus = <&mmu_aw 1 1>;
status = "okay";
};
scaler23:scaler@11 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x059107f4 0x0 0x40c>;
work_mode = <0xff>;
device_id = <11>;
iommus = <&mmu_aw 1 1>;
status = "okay";
};
scaler30:scaler@12 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x05910c00 0x0 0x400>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
work_mode = <0>;
device_id = <12>;
iommus = <&mmu_aw 1 1>;
status = "okay";
};
scaler31:scaler@13 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x05910bfc 0x0 0x404>;
work_mode = <0xff>;
device_id = <13>;
iommus = <&mmu_aw 1 1>;
status = "okay";
};
scaler32:scaler@14 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x05910bf8 0x0 0x408>;
work_mode = <0xff>;
device_id = <14>;
iommus = <&mmu_aw 1 1>;
status = "okay";
};
scaler33:scaler@15 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x05910bf4 0x0 0x40c>;
work_mode = <0xff>;
device_id = <15>;
iommus = <&mmu_aw 1 1>;
status = "okay";
};
actuator0:actuator@0 {
device_type = "actuator0";
compatible = "allwinner,sunxi-actuator";
actuator0_name = "ad5820_act";
actuator0_slave = <0x18>;
actuator0_af_pwdn = <>;
actuator0_afvdd = "afvcc-csi";
actuator0_afvdd_vol = <2800000>;
status = "disabled";
};
flash0:flash@0 {
device_type = "flash0";
compatible = "allwinner,sunxi-flash";
flash0_type = <2>;
flash0_en = <>;
flash0_mode = <>;
flash0_flvdd = "";
flash0_flvdd_vol = <>;
device_id = <0>;
status = "disabled";
};
sensor0:sensor@0 {
device_type = "sensor0";
compatible = "allwinner,sunxi-sensor";
sensor0_mname = "gc2053_mipi";
sensor0_twi_cci_id = <1>;
sensor0_twi_addr = <0x6e>;
sensor0_mclk_id = <0>;
sensor0_pos = "rear";
sensor0_isp_used = <1>;
sensor0_fmt = <1>;
sensor0_stby_mode = <0>;
sensor0_vflip = <0>;
sensor0_hflip = <0>;
sensor0_iovdd-supply = <>;
sensor0_iovdd_vol = <1800000>;
sensor0_avdd-supply = <>;
sensor0_avdd_vol = <2800000>;
sensor0_dvdd-supply = <>;
sensor0_dvdd_vol = <1200000>;
sensor0_power_en = <>;
sensor0_reset = <>;
sensor0_pwdn = <>;
sensor0_sm_hs = <>;
sensor0_sm_vs = <>;
flash_handle = <&flash0>;
act_handle = <&actuator0>;
device_id = <0>;
status = "okay";
};
sensor1:sensor@1 {
device_type = "sensor1";
compatible = "allwinner,sunxi-sensor";
sensor1_mname = "ov5647";
sensor1_twi_cci_id = <1>;
sensor1_twi_addr = <0x6c>;
sensor1_mclk_id = <3>;
sensor1_pos = "front";
sensor1_isp_used = <0>;
sensor1_fmt = <0>;
sensor1_stby_mode = <0>;
sensor1_vflip = <0>;
sensor1_hflip = <0>;
sensor1_iovdd-supply = <>;
sensor1_iovdd_vol = <1800000>;
sensor1_avdd-supply = <>;
sensor1_avdd_vol = <2800000>;
sensor1_dvdd-supply = <>;
sensor1_dvdd_vol = <1200000>;
sensor1_power_en = <>;
sensor1_reset = <>;
sensor1_pwdn = <>;
sensor1_sm_hs = <>;
sensor1_sm_vs = <>;
flash_handle = <>;
act_handle = <>;
device_id = <1>;
status = "okay";
};
vinc00:vinc@0 {
device_type = "vinc0";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x05830000 0x0 0x1000>;
interrupts = <GIC_SPI 95 4>;
vinc0_csi_sel = <0>;
vinc0_mipi_sel = <0>;
vinc0_isp_sel = <0>;
vinc0_isp_tx_ch = <0>;
vinc0_tdm_rx_sel = <0>;
vinc0_rear_sensor_sel = <0>;
vinc0_front_sensor_sel = <0>;
vinc0_sensor_list = <0>;
device_id = <0>;
work_mode = <0x0>;
iommus = <&mmu_aw 1 1>;
status = "okay";
};
vinc01:vinc@1 {
device_type = "vinc1";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x0582fffc 0x0 0x1004>;
vinc1_csi_sel = <2>;
vinc1_mipi_sel = <0xff>;
vinc1_isp_sel = <1>;
vinc1_isp_tx_ch = <1>;
vinc1_tdm_rx_sel = <1>;
vinc1_rear_sensor_sel = <0>;
vinc1_front_sensor_sel = <0>;
vinc1_sensor_list = <0>;
device_id = <1>;
work_mode = <0xff>;
iommus = <&mmu_aw 1 1>;
status = "disabled";
};
vinc02:vinc@2 {
device_type = "vinc2";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x0582fff8 0x0 0x1008>;
vinc2_csi_sel = <2>;
vinc2_mipi_sel = <0xff>;
vinc2_isp_sel = <2>;
vinc2_isp_tx_ch = <2>;
vinc2_tdm_rx_sel = <2>;
vinc2_rear_sensor_sel = <0>;
vinc2_front_sensor_sel = <0>;
vinc2_sensor_list = <0>;
device_id = <2>;
work_mode = <0xff>;
iommus = <&mmu_aw 1 1>;
status = "disabled";
};
vinc03:vinc@3 {
device_type = "vinc3";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x0582fff4 0x0 0x100c>;
vinc3_csi_sel = <0>;
vinc3_mipi_sel = <0xff>;
vinc3_isp_sel = <0>;
vinc3_isp_tx_ch = <0>;
vinc3_tdm_rx_sel = <0>;
vinc3_rear_sensor_sel = <1>;
vinc3_front_sensor_sel = <1>;
vinc3_sensor_list = <0>;
device_id = <3>;
work_mode = <0xff>;
iommus = <&mmu_aw 1 1>;
status = "disabled";
};
vinc10:vinc@4 {
device_type = "vinc4";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x05831000 0x0 0x1000>;
interrupts = <GIC_SPI 96 4>;
vinc4_csi_sel = <0>;
vinc4_mipi_sel = <0xff>;
vinc4_isp_sel = <0>;
vinc4_isp_tx_ch = <0>;
vinc4_tdm_rx_sel = <0>;
vinc4_rear_sensor_sel = <1>;
vinc4_front_sensor_sel = <1>;
vinc4_sensor_list = <0>;
device_id = <4>;
work_mode = <0x0>;
iommus = <&mmu_aw 1 1>;
status = "disabled";
};
vinc11:vinc@5 {
device_type = "vinc5";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x05830ffc 0x0 0x1004>;
vinc5_csi_sel = <2>;
vinc5_mipi_sel = <0xff>;
vinc5_isp_sel = <1>;
vinc5_isp_tx_ch = <1>;
vinc5_tdm_rx_sel = <1>;
vinc5_rear_sensor_sel = <0>;
vinc5_front_sensor_sel = <0>;
vinc5_sensor_list = <0>;
device_id = <5>;
work_mode = <0xff>;
iommus = <&mmu_aw 1 1>;
status = "disabled";
};
vinc12:vinc@6 {
device_type = "vinc6";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x05830ff8 0x0 0x1008>;
vinc6_csi_sel = <2>;
vinc6_mipi_sel = <0xff>;
vinc6_isp_sel = <0>;
vinc6_isp_tx_ch = <0>;
vinc6_tdm_rx_sel = <0>;
vinc6_rear_sensor_sel = <0>;
vinc6_front_sensor_sel = <0>;
vinc6_sensor_list = <0>;
device_id = <6>;
work_mode = <0xff>;
iommus = <&mmu_aw 1 1>;
status = "disabled";
};
vinc13:vinc@7 {
device_type = "vinc7";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x05830ff4 0x0 0x100c>;
vinc7_csi_sel = <2>;
vinc7_mipi_sel = <0xff>;
vinc7_isp_sel = <0>;
vinc7_isp_tx_ch = <0>;
vinc7_tdm_rx_sel = <0>;
vinc7_rear_sensor_sel = <0>;
vinc7_front_sensor_sel = <0>;
vinc7_sensor_list = <0>;
device_id = <7>;
work_mode = <0xff>;
iommus = <&mmu_aw 1 1>;
status = "disabled";
};
vinc20:vinc@8 {
device_type = "vinc8";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x05832000 0x0 0x1000>;
interrupts = <GIC_SPI 97 4>;
vinc8_csi_sel = <2>;
vinc8_mipi_sel = <0xff>;
vinc8_isp_sel = <4>;
vinc8_isp_tx_ch = <3>;
vinc8_tdm_rx_sel = <3>;
vinc8_rear_sensor_sel = <0>;
vinc8_front_sensor_sel = <0>;
vinc8_sensor_list = <0>;
device_id = <8>;
work_mode = <0x0>;
iommus = <&mmu_aw 1 1>;
status = "disabled";
};
vinc21:vinc@9 {
device_type = "vinc9";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x05831ffc 0x0 0x1004>;
vinc9_csi_sel = <2>;
vinc9_mipi_sel = <0xff>;
vinc9_isp_sel = <0>;
vinc9_isp_tx_ch = <0>;
vinc9_tdm_rx_sel = <0>;
vinc9_rear_sensor_sel = <0>;
vinc9_front_sensor_sel = <0>;
vinc9_sensor_list = <0>;
device_id = <9>;
work_mode = <0xff>;
iommus = <&mmu_aw 1 1>;
status = "disabled";
};
vinc22:vinc@10 {
device_type = "vinc10";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x05831ff8 0x0 0x1008>;
vinc10_csi_sel = <2>;
vinc10_mipi_sel = <0xff>;
vinc10_isp_sel = <0>;
vinc10_isp_tx_ch = <0>;
vinc10_tdm_rx_sel = <0>;
vinc10_rear_sensor_sel = <0>;
vinc10_front_sensor_sel = <0>;
vinc10_sensor_list = <0>;
device_id = <10>;
work_mode = <0xff>;
iommus = <&mmu_aw 1 1>;
status = "disabled";
};
vinc23:vinc@11 {
device_type = "vinc11";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x05831ff4 0x0 0x100c>;
vinc11_csi_sel = <2>;
vinc11_mipi_sel = <0xff>;
vinc11_isp_sel = <0>;
vinc11_isp_tx_ch = <0>;
vinc11_tdm_rx_sel = <0>;
vinc11_rear_sensor_sel = <0>;
vinc11_front_sensor_sel = <0>;
vinc11_sensor_list = <0>;
device_id = <11>;
work_mode = <0xff>;
iommus = <&mmu_aw 1 1>;
status = "disabled";
};
vinc30:vinc@12 {
device_type = "vinc12";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x05833000 0x0 0x1000>;
interrupts = <GIC_SPI 98 4>;
vinc12_csi_sel = <2>;
vinc12_mipi_sel = <0xff>;
vinc12_isp_sel = <0>;
vinc12_isp_tx_ch = <0>;
vinc12_tdm_rx_sel = <0>;
vinc12_rear_sensor_sel = <0>;
vinc12_front_sensor_sel = <0>;
vinc12_sensor_list = <0>;
device_id = <12>;
work_mode = <0x0>;
iommus = <&mmu_aw 1 1>;
status = "disabled";
};
vinc31:vinc@13 {
device_type = "vinc13";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x05832ffc 0x0 0x1004>;
vinc13_csi_sel = <2>;
vinc13_mipi_sel = <0xff>;
vinc13_isp_sel = <0>;
vinc13_isp_tx_ch = <0>;
vinc13_tdm_rx_sel = <0>;
vinc13_rear_sensor_sel = <0>;
vinc13_front_sensor_sel = <0>;
vinc13_sensor_list = <0>;
device_id = <13>;
work_mode = <0xff>;
iommus = <&mmu_aw 1 1>;
status = "disabled";
};
vinc32:vinc@14 {
device_type = "vinc14";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x05832ff8 0x0 0x1008>;
vinc14_csi_sel = <2>;
vinc14_mipi_sel = <0xff>;
vinc14_isp_sel = <0>;
vinc14_isp_tx_ch = <0>;
vinc14_tdm_rx_sel = <0>;
vinc14_rear_sensor_sel = <0>;
vinc14_front_sensor_sel = <0>;
vinc14_sensor_list = <0>;
device_id = <14>;
work_mode = <0xff>;
iommus = <&mmu_aw 1 1>;
status = "disabled";
};
vinc33:vinc@15 {
device_type = "vinc15";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x05832ff4 0x0 0x100c>;
vinc15_csi_sel = <2>;
vinc15_mipi_sel = <0xff>;
vinc15_isp_sel = <0>;
vinc15_isp_tx_ch = <0>;
vinc15_tdm_rx_sel = <0>;
vinc15_rear_sensor_sel = <0>;
vinc15_front_sensor_sel = <0>;
vinc15_sensor_list = <0>;
device_id = <15>;
work_mode = <0xff>;
iommus = <&mmu_aw 1 1>;
status = "disabled";
};
};
e907_standby: e907_standby@0 {
compatible = "allwinner,sunxi-e907-standby";
firmware = "riscv.fex";
mboxes = <&msgbox 1>;
mbox-names = "mbox-chan";
power-domains = <&pd V853_PD_E907>;
status = "disabled";
};
};
};
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