461 lines
11 KiB
C
Executable File
461 lines
11 KiB
C
Executable File
/* sound\soc\sunxi\snd_sun8iw21_codec.h
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* (C) Copyright 2021-2025
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Dby <dby@allwinnertech.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef __SND_HAS_SUN8IW21_CODEC_H
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#define __SND_HAS_SUN8IW21_CODEC_H
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#define SUNXI_DAC_DPC 0x00
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#define SUNXI_DAC_VOL_CTRL 0x04
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#define SUNXI_DAC_FIFOC 0x10
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#define SUNXI_DAC_FIFOS 0x14
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#define SUNXI_DAC_TXDATA 0X20
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#define SUNXI_DAC_CNT 0x24
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#define SUNXI_DAC_DG 0x28
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#define SUNXI_ADC_FIFOC 0x30
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#define SUNXI_ADC_VOL_CTRL 0x34
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#define SUNXI_ADC_FIFOS 0x38
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#define SUNXI_ADC_RXDATA 0x40
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#define SUNXI_ADC_CNT 0x44
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#define SUNXI_ADC_DG 0x4C
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#define SUNXI_ADC_DIG_CTRL 0x50
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#define SUNXI_VRA1SPEEDUP_DOWN_CTRL 0x54
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#define SUNXI_DAC_DAP_CTL 0xF0
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#define SUNXI_ADC_DAP_CTL 0xF8
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#define SUNXI_DAC_DRC_HHPFC 0x100
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#define SUNXI_DAC_DRC_LHPFC 0x104
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#define SUNXI_DAC_DRC_CTRL 0x108
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#define SUNXI_DAC_DRC_LPFHAT 0x10C
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#define SUNXI_DAC_DRC_LPFLAT 0x110
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#define SUNXI_DAC_DRC_RPFHAT 0x114
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#define SUNXI_DAC_DRC_RPFLAT 0x118
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#define SUNXI_DAC_DRC_LPFHRT 0x11C
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#define SUNXI_DAC_DRC_LPFLRT 0x120
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#define SUNXI_DAC_DRC_RPFHRT 0x124
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#define SUNXI_DAC_DRC_RPFLRT 0x128
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#define SUNXI_DAC_DRC_LRMSHAT 0x12C
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#define SUNXI_DAC_DRC_LRMSLAT 0x130
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#define SUNXI_DAC_DRC_RRMSHAT 0x134
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#define SUNXI_DAC_DRC_RRMSLAT 0x138
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#define SUNXI_DAC_DRC_HCT 0x13C
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#define SUNXI_DAC_DRC_LCT 0x140
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#define SUNXI_DAC_DRC_HKC 0x144
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#define SUNXI_DAC_DRC_LKC 0x148
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#define SUNXI_DAC_DRC_HOPC 0x14C
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#define SUNXI_DAC_DRC_LOPC 0x150
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#define SUNXI_DAC_DRC_HLT 0x154
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#define SUNXI_DAC_DRC_LLT 0x158
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#define SUNXI_DAC_DRC_HKI 0x15C
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#define SUNXI_DAC_DRC_LKI 0x160
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#define SUNXI_DAC_DRC_HOPL 0x164
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#define SUNXI_DAC_DRC_LOPL 0x168
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#define SUNXI_DAC_DRC_HET 0x16C
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#define SUNXI_DAC_DRC_LET 0x170
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#define SUNXI_DAC_DRC_HKE 0x174
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#define SUNXI_DAC_DRC_LKE 0x178
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#define SUNXI_DAC_DRC_HOPE 0x17C
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#define SUNXI_DAC_DRC_LOPE 0x180
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#define SUNXI_DAC_DRC_HKN 0x184
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#define SUNXI_DAC_DRC_LKN 0x188
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#define SUNXI_DAC_DRC_SFHAT 0x18C
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#define SUNXI_DAC_DRC_SFLAT 0x190
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#define SUNXI_DAC_DRC_SFHRT 0x194
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#define SUNXI_DAC_DRC_SFLRT 0x198
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#define SUNXI_DAC_DRC_MXGHS 0x19C
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#define SUNXI_DAC_DRC_MXGLS 0x1A0
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#define SUNXI_DAC_DRC_MNGHS 0x1A4
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#define SUNXI_DAC_DRC_MNGLS 0x1A8
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#define SUNXI_DAC_DRC_EPSHC 0x1AC
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#define SUNXI_DAC_DRC_EPSLC 0x1B0
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#define SUNXI_DAC_DRC_OPT 0x1B4
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#define SUNXI_DAC_DRC_HPFHGAIN 0x1B8
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#define SUNXI_DAC_DRC_HPFLGAIN 0x1BC
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#define SUNXI_ADC_DRC_HHPFC 0x200
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#define SUNXI_ADC_DRC_LHPFC 0x204
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#define SUNXI_ADC_DRC_CTRL 0x208
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#define SUNXI_ADC_DRC_LPFHAT 0x20C
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#define SUNXI_ADC_DRC_LPFLAT 0x210
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#define SUNXI_ADC_DRC_RPFHAT 0x214
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#define SUNXI_ADC_DRC_RPFLAT 0x218
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#define SUNXI_ADC_DRC_LPFHRT 0x21C
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#define SUNXI_ADC_DRC_LPFLRT 0x220
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#define SUNXI_ADC_DRC_RPFHRT 0x224
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#define SUNXI_ADC_DRC_RPFLRT 0x228
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#define SUNXI_ADC_DRC_LRMSHAT 0x22C
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#define SUNXI_ADC_DRC_LRMSLAT 0x230
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#define SUNXI_ADC_DRC_HCT 0x23C
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#define SUNXI_ADC_DRC_LCT 0x240
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#define SUNXI_ADC_DRC_HKC 0x244
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#define SUNXI_ADC_DRC_LKC 0x248
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#define SUNXI_ADC_DRC_HOPC 0x24C
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#define SUNXI_ADC_DRC_LOPC 0x250
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#define SUNXI_ADC_DRC_HLT 0x254
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#define SUNXI_ADC_DRC_LLT 0x258
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#define SUNXI_ADC_DRC_HKI 0x25C
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#define SUNXI_ADC_DRC_LKI 0x260
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#define SUNXI_ADC_DRC_HOPL 0x264
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#define SUNXI_ADC_DRC_LOPL 0x268
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#define SUNXI_ADC_DRC_HET 0x26C
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#define SUNXI_ADC_DRC_LET 0x270
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#define SUNXI_ADC_DRC_HKE 0x274
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#define SUNXI_ADC_DRC_LKE 0x278
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#define SUNXI_ADC_DRC_HOPE 0x27C
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#define SUNXI_ADC_DRC_LOPE 0x280
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#define SUNXI_ADC_DRC_HKN 0x284
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#define SUNXI_ADC_DRC_LKN 0x288
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#define SUNXI_ADC_DRC_SFHAT 0x28C
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#define SUNXI_ADC_DRC_SFLAT 0x290
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#define SUNXI_ADC_DRC_SFHRT 0x294
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#define SUNXI_ADC_DRC_SFLRT 0x298
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#define SUNXI_ADC_DRC_MXGHS 0x29C
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#define SUNXI_ADC_DRC_MXGLS 0x2A0
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#define SUNXI_ADC_DRC_MNGHS 0x2A4
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#define SUNXI_ADC_DRC_MNGLS 0x2A8
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#define SUNXI_ADC_DRC_EPSHC 0x2AC
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#define SUNXI_ADC_DRC_EPSLC 0x2B0
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#define SUNXI_ADC_DRC_OPT 0x2B4
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#define SUNXI_ADC_DRC_HPFHGAIN 0x2B8
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#define SUNXI_ADC_DRC_HPFLGAIN 0x2BC
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#define SUNXI_AC_VERSION 0x2C0
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/* Analog register */
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#define SUNXI_ADC1_REG 0x300
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#define SUNXI_ADC2_REG 0x304
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#define SUNXI_DAC_REG 0x310
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#define SUNXI_MICBIAS_REG 0x318
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#define SUNXI_RAMP_REG 0x31C /* only set bit[1] at init */
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#define SUNXI_BIAS_REG 0x320
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#define SUNXI_POWER_REG 0x348
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#define SUNXI_ADC_CUR_REG 0x34C
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#define SUNXI_CODEC_REG_MAX SUNXI_ADC_CUR_REG
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/* SUNXI_DAC_DPC:0x00 */
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#define EN_DAC 31
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#define MODQU 25
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#define DWA_EN 24
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#define HPF_EN 18
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#define DVOL 12
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#define DAC_HUB_EN 0
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/* SUNXI_DAC_VOL_CTRL:0x04 */
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#define DAC_VOL_SEL 16
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#define DAC_VOL_L 8
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#define DAC_VOL_R 0
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/* SUNXI_DAC_FIFOC:0x10 */
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#define DAC_FS 29
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#define FIR_VER 28
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#define SEND_LASAT 26
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#define FIFO_MODE 24
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#define DAC_DRQ_CLR_CNT 21
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#define TX_TRIG_LEVEL 8
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#define DAC_MONO_EN 6
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#define TX_SAMPLE_BITS 5
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#define DAC_DRQ_EN 4
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#define DAC_IRQ_EN 3
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#define FIFO_UNDERRUN_IRQ_EN 2
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#define FIFO_OVERRUN_IRQ_EN 1
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#define FIFO_FLUSH 0
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/* SUNXI_DAC_FIFOS:0x14 */
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#define TX_EMPTY 23
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#define DAC_TXE_CNT 8
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#define DAC_TXE_INT 3
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#define DAC_TXU_INT 2
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#define DAC_TXO_INT 1
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/* SUNXI_DAC_DG:0x28 */
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#define DAC_MODU_SEL 11
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#define DAC_PATTERN_SEL 9
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#define DAC_CODEC_CLK_SEL 8
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#define DAC_SWP 6
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#define ADDA_LOOP_MODE 0
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/* SUNXI_ADC_FIFOC:0x30 */
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#define ADC_FS 29
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#define EN_AD 28
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#define ADCFDT 26
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#define ADCDFEN 25
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#define RX_FIFO_MODE 24
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#define RX_SYNC_EN_START 21
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#define RX_SYNC_EN 20
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#define RX_SAMPLE_BITS 16
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#define RX_FIFO_TRG_LEVEL 4
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#define ADC_DRQ_EN 3
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#define ADC_IRQ_EN 2
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#define ADC_OVERRUN_IRQ_EN 1
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#define ADC_FIFO_FLUSH 0
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/* SUNXI_ADC_VOL_CTRL:0x34 */
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#define ADC2_VOL 8
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#define ADC1_VOL 0
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/* SUNXI_ADC_FIFOS:0x38 */
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#define RXA 23
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#define ADC_RXA_CNT 8
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#define ADC_RXA_INT 3
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#define ADC_RXO_INT 1
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/* SUNXI_ADC_DG:0x4C */
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#define AD_SWP1 24
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/* SUNXI_ADC_DIG_CTRL:0x50 */
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#define ADC1_2_VOL_EN 16
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#define ADC2_CHANNEL_EN 1
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#define ADC1_CHANNEL_EN 0
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#define ADC_CHANNEL_EN 0
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/* SUNXI_VRA1SPEEDUP_DOWN_CTRL:0x54 */
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#define VRA1SPEEDUP_DOWN_STATE 4
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#define VRA1SPEEDUP_DOWN_CTRL 1
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#define VRA1SPEEDUP_DOWN_RST_CTRL 0
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/* SUNXI_DAC_DAP_CTL:0xf0 */
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#define DDAP_EN 31
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#define DDAP_DRC_EN 29
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#define DDAP_HPF_EN 28
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/* SUNXI_ADC_DAP_CTL:0xf8 */
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#define ADC_DAP0_EN 31
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#define ADC_DRC0_EN 29
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#define ADC_HPF0_EN 28
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#define ADC_DAP1_EN 27
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#define ADC_DRC1_EN 25
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#define ADC_HPF1_EN 24
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/* SUNXI_DAC_DRC_HHPFC: 0x100*/
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#define DAC_HHPF_CONF 0
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/* SUNXI_DAC_DRC_LHPFC: 0x104*/
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#define DAC_LHPF_CONF 0
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/* SUNXI_DAC_DRC_CTRL: 0x108*/
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#define DAC_DRC_DELAY_OUT_STATE 15
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#define DAC_DRC_SIGNAL_DELAY 8
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#define DAC_DRC_DELAY_BUF_EN 7
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#define DAC_DRC_GAIN_MAX_EN 6
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#define DAC_DRC_GAIN_MIN_EN 5
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#define DAC_DRC_NOISE_DET_EN 4
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#define DAC_DRC_SIGNAL_SEL 3
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#define DAC_DRC_DELAY_EN 2
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#define DAC_DRC_LT_EN 1
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#define DAC_DRC_ET_EN 0
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/* SUNXI_ADC_DRC_HHPFC: 0x200*/
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#define ADC_HHPF_CONF 0
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/* SUNXI_ADC_DRC_LHPFC: 0x204*/
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#define ADC_LHPF_CONF 0
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/* SUNXI_ADC_DRC_CTRL: 0x208*/
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#define ADC_DRC_DELAY_OUT_STATE 15
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#define ADC_DRC_SIGNAL_DELAY 8
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#define ADC_DRC_DELAY_BUF_EN 7
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#define ADC_DRC_GAIN_MAX_EN 6
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#define ADC_DRC_GAIN_MIN_EN 5
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#define ADC_DRC_NOISE_DET_EN 4
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#define ADC_DRC_SIGNAL_SEL 3
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#define ADC_DRC_DELAY_EN 2
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#define ADC_DRC_LT_EN 1
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#define ADC_DRC_ER_EN 0
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/* SUNXI_DAC_DRC_HHPFC: 0x100*/
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#define DAC_HHPF_CONF 0
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/* SUNXI_DAC_DRC_LHPFC: 0x104*/
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#define DAC_LHPF_CONF 0
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/* SUNXI_ADC_DRC_HHPFC: 0x200*/
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#define ADC_HHPF_CONF 0
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/* SUNXI_ADC_DRC_LHPFC: 0x204*/
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#define ADC_LHPF_CONF 0
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/* SUNXI_ADC1_REG : 0x300 */
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#define ADC1_EN 31
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#define MIC1_PGA_EN 30
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#define ADC1_DITHER_CTRL 29
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#define MIC1_SIN_EN 28
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#define FMINLEN 27
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#define FMINLG 26
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#define ADC1_DSM_DITHER_LVL 24
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#define LINEINLEN 23
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#define LINEINLG 22
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#define ADC1_IOPBUFFER 20
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#define ADC1_PGA_CTRL_RCM 18
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#define ADC1_PGA_IN_VCM_CTRL 16
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#define ADC1_2_CURRENT_SEL 14
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#define ADC1_SINGLE_NOISE_CTL 13
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#define ADC1_PGA_GAIN_CTRL 8
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#define ADC1_IOPAAF 6
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#define ADC1_IOPSDM1 4
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#define ADC1_IOPSDM2 2
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#define ADC1_IOPMIC 0
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/* SUNXI_ADC2_REG : 0x304 */
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#define ADC2_EN 31
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#define MIC2_PGA_EN 30
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#define ADC2_DITHER_CTRL 29
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#define MIC2_SIN_EN 28
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#define FMINREN 27
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#define FMINRG 26
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#define ADC2_DSM_DITHER_LVL 24
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#define LINEINREN 23
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#define LINEINRG 22
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#define ADC2_IOPBUFFER 20
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#define ADC2_PGA_CTRL_RCM 18
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#define ADC2_PGA_IN_VCM_CTRL 16
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#define ADC2_SINGLE_NOISE_CTL 13
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#define ADC2_PGA_GAIN_CTRL 8
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#define ADC2_IOPAAF 6
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#define ADC2_IOPSDM1 4
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#define ADC2_IOPSDM2 2
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#define ADC2_IOPMIC 0
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/* SUNXI_DAC_REG : 0x310 */
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#define P_CURRENT_TEST_SELECT 24
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#define N_CURRENT_TEST_SELECT 22
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#define VRA2_IOPVRS 20
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#define ILINEOUTAMPS 18
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#define IOPDACS 16
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#define DACLEN 15
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#define LINEOUTLEN 13
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#define DACLMUTE 12
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#define VRA2_OPVR_OI_CTRL 7
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#define LINEOUTLDIFFEN 6
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#define LINEOUT_VOL 0
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/* SUNXI_MICBIAS_REG : 0x318 */
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#define MMICBIASEN 7
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#define MBIASSEL 5
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#define MMICBIAS_CHOP_EN 4
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#define MMICBIAS_CHOP_CLK_SEL 2
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/* SUNXI_RAMP_REG : 0x31C */
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#define RMC_EN 1
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/* SUNXI_BIAS_REG : 0x320 */
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#define AC_BIASDATA 0
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/* SUNXI_POWER_REG :0x348 */
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#define ALDO_EN 31
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#define VAR1SPEEDUP_DOWN_FURTHER_CTRL 29
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#define BG_BUFFER_DISABLE 15
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#define ALDO_OUTPUT_VOLTAGE 12
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#define BG_ROUGH_TRIM 8
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#define BG_FINE_TRIM 0
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/* SUNXI_ADC_CUR_REG :0x34C */
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#define ADC2_IOPMIC2 12
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#define ADC2_OP_MIC1_CUR 10
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#define ADC2_OP_MIC2_CUR 8
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#define ADC1_IOPMIC2 4
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#define ADC1_OP_MIC1_CUR 2
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#define ADC1_OP_MIC2_CUR 0
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struct sunxi_has_clk {
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struct clk *pllaudio;
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struct clk *dacclk;
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struct clk *adcclk;
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};
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struct sunxi_regulator {
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bool external_avcc;
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unsigned int avcc_vol;
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struct regulator *avcc;
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};
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struct sunxi_has_dts {
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unsigned int lineout_vol;
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unsigned int mic1gain;
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unsigned int mic2gain;
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unsigned int adc_dtime;
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bool lineout_single; /* true: single mode; false: differ mode */
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bool mic1_single;
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bool mic2_single;
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/* tx_hub */
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bool tx_hub_en;
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/* components func -> rx sync */
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bool rx_sync_en; /* read from dts */
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bool rx_sync_ctl;
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int rx_sync_id;
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// rx_sync_domain_t rx_sync_domain;
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};
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struct sunxi_dap {
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unsigned int dap_enable;
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struct mutex mutex;
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};
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// struct sunxi_codec_runtime {
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// /* input: micin and linein have common parts, need manage */
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// unsigned int mic1gain;
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// unsigned int mic2gain;
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// bool mic1_single;
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// bool mic2_single;
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// unsigned int lineinlgain;
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// unsigned int lineinrgain;
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// bool mic1_run;
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// bool mic2_run;
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// bool linein_run;
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// struct mutex input_mutex;
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// /* output: only lineout, unneed manage. */
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// };
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// enum SUNXI_kCONTROL_SHIFT {
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// KCONTROL_SHIFT_MIC1_GAIN = 0,
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// KCONTROL_SHIFT_MIC2_GAIN,
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// KCONTROL_SHIFT_LINEINL_GAIN,
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// KCONTROL_SHIFT_LINEINR_GAIN,
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// };
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// enum SUNXI_WIDGET_SHIFT {
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// WIDGET_SHIFT_ADC1 = 0,
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// WIDGET_SHIFT_ADC2,
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// WIDGET_SHIFT_MIC1_INPUT_SELECT,
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// WIDGET_SHIFT_MIC2_INPUT_SELECT,
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// WIDGET_SHIFT_MIC1_GAIN,
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// WIDGET_SHIFT_MIC2_GAIN,
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// WIDGET_SHIFT_LINEINL_GAIN,
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// WIDGET_SHIFT_LINEINR_GAIN,
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// };
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// struct sunxi_codec {
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// struct platform_device *pdev;
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// struct sunxi_has_mem mem;
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// struct sunxi_clk clk;
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// struct sunxi_regulator rglt;
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// // struct sunxi_dts dts;
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// struct sunxi_dap dac_dap;
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// struct sunxi_dap adc_dap;
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// unsigned int pa_pin_max;
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// struct pa_config *pa_config;
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// struct sunxi_codec_runtime runtime;
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// };
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#endif /* __SND_HAS_SUN8IW21_CODEC_H */
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