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sdk-hwV1.3/lichee/linux-4.9/arch/arm64/boot/dts/sunxi/sun50iw11p1.dtsi

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/*
* Allwinner Technology CO., Ltd. sun50iw11p1 platform
*
* modify base on juno.dts
*/
/*secure used 8M: SHM 2M: ATF 1M: OS 1M: TA 4M*/
/memreserve/ 0x41800000 0x00800000;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include "sun50iw11p1-clk.dtsi"
#include "sun50iw11p1-pinctrl.dtsi"
#include <dt-bindings/thermal/thermal.h>
/ {
model = "sun50iw11";
compatible = "arm,sun50iw11p1";
interrupt-parent = <&wakeupgen>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
ir0 = &s_cir0;
ir1 = &ir1;
twi0 = &twi0;
twi1 = &twi1;
twi2 = &twi2;
spi0 = &spi0;
spi1 = &spi1;
ledc = &ledc;
gmac0 = &gmac0;
global_timer0 = &soc_timer0;
mmc0 = &sdc0;
nand0 =&nand0;
pwm = &pwm;
pwm0 = &pwm0;
pwm1 = &pwm1;
pwm2 = &pwm2;
pwm3 = &pwm3;
pwm4 = &pwm4;
pwm5 = &pwm5;
pwm6 = &pwm6;
pwm7 = &pwm7;
pwm8 = &pwm8;
pwm9 = &pwm9;
pwm10 = &s_pwm0;
pwm11 = &s_pwm1;
pwm12 = &s_pwm2;
pwm13 = &s_pwm3;
pwm14 = &s_pwm4;
pwm15 = &s_pwm5;
lcdfb = &lcdfb;
lcd_fb0 = &lcd_fb0;
share_space0 = &share_space0;
share_space1 = &share_space1;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
dsp0@100000 {
no-map;
reg = <0x0 0x100000 0x0 0x1d0000>;
};
dsp1@42000000 {
no-map;
reg = <0x0 0x42000000 0x0 0x100000>;
};
dsp0_share_space@42100000 {
no-map;
reg = <0x0 0x42100000 0x0 0x10000>;
};
dsp1_share_space@42110000 {
no-map;
reg = <0x0 0x42110000 0x0 0x10000>;
};
};
chosen {
bootargs = "earlyprintk=sunxi-uart,0x02500000 loglevel=8 initcall_debug=1 console=ttyS0 init=/init";
linux,initrd-start = <0x0 0x0>;
linux,initrd-end = <0x0 0x0>;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&clk_pll_cpu>;
clock-latency = <2000000>;
clock-frequency = <1320000000>;
dynamic-power-coefficient = <202>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
#cooling-cells = <2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&clk_pll_cpu>;
clock-frequency = <1320000000>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
#cooling-cells = <2>;
};
idle-states {
entry-method = "arm,psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <46>;
exit-latency-us = <59>;
min-residency-us = <3570>;
local-timer-stop;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x1010000>;
entry-latency-us = <47>;
exit-latency-us = <74>;
min-residency-us = <5000>;
local-timer-stop;
};
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
n_brom {
compatible = "allwinner,n-brom";
reg = <0x0 0x0 0x0 0xa000>;
};
s_brom {
compatible = "allwinner,s-brom";
reg = <0x0 0x0 0x0 0x10000>;
};
sram_ctrl {
device_type = "sram_ctrl";
compatible = "allwinner,sram_ctrl";
reg = <0x0 0x03000000 0x0 0x100>;
};
sram_a1 {
compatible = "allwinner,sram_a1";
reg = <0x0 0x00020000 0x0 0x8000>;
};
sram_a2 {
compatible = "allwinner,sram_a2";
reg = <0x0 0x00100000 0x0 0x14000>;
};
prcm {
compatible = "allwinner,prcm";
reg = <0x0 0x01f01400 0x0 0x400>;
};
s_cpuscfg {
compatible = "allwinner,s_cpuscfg";
reg = <0x0 0x01f01c00 0x0 0x400>;
};
ion {
compatible = "allwinner,sunxi-ion";
/*types is list here:
ION_HEAP_TYPE_SYSTEM = 0,
ION_HEAP_TYPE_SYSTEM_CONTIG = 1,
ION_HEAP_TYPE_CARVEOUT = 2,
ION_HEAP_TYPE_CHUNK = 3,
ION_HEAP_TYPE_DMA = 4,
ION_HEAP_TYPE_SECURE = 6,
**/
heap_sys_user@0{
compatible = "allwinner,sys_user";
heap-name = "sys_user";
heap-id = <0x0>;
heap-base = <0x0>;
heap-size = <0x0>;
heap-type = "ion_system";
};
heap_cma@0{
compatible = "allwinner,cma";
heap-name = "cma";
heap-id = <0x4>;
heap-base = <0x0>;
heap-size = <0x0>;
heap-type = "ion_cma";
};
heap_secure@0{
compatible = "allwinner,secure";
heap-name = "secure";
heap-id = <0x6>;
heap-base = <0x0>;
heap-size = <0x0>;
heap-type = "ion_secure";
};
};
dram: dram {
compatible = "allwinner,dram";
/* clocks = <&clk_pll_ddr>; */
clock-names = "pll_ddr";
dram_clk = <672>;
dram_type = <3>;
dram_zq = <0x003F3FDD>;
dram_odt_en = <1>;
dram_para1 = <0x10f41000>;
dram_para2 = <0x00001200>;
dram_mr0 = <0x1A50>;
dram_mr1 = <0x40>;
dram_mr2 = <0x10>;
dram_mr3 = <0>;
dram_tpr0 = <0x04E214EA>;
dram_tpr1 = <0x004214AD>;
dram_tpr2 = <0x10A75030>;
dram_tpr3 = <0>;
dram_tpr4 = <0>;
dram_tpr5 = <0>;
dram_tpr6 = <0>;
dram_tpr7 = <0>;
dram_tpr8 = <0>;
dram_tpr9 = <0>;
dram_tpr10 = <0>;
dram_tpr11 = <0>;
dram_tpr12 = <168>;
dram_tpr13 = <0x823>;
};
memory@40000000 {
device_type = "memory";
reg = <0x00000000 0x40000000 0x00000000 0x20000000>;
};
gic: interrupt-controller@03020000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
device_type = "gic";
interrupt-controller;
reg = <0x0 0x03021000 0 0x1000>, /* GIC Dist */
<0x0 0x03022000 0 0x2000>, /* GIC CPU */
<0x0 0x03024000 0 0x2000>, /* GIC VCPU Control */
<0x0 0x03026000 0 0x2000>; /* GIC VCPU */
interrupts = <GIC_PPI 9 0xf04>; /* GIC Maintenence IRQ */
interrupt-parent = <&gic>;
};
wakeupgen: interrupt-controller@0 {
compatible = "allwinner,sunxi-wakeupgen";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
};
nmi: nmi@07010320 {
compatible = "allwinner,sun8i-nmi";
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0x07010320 0 0xc>;
pad-control-v1 = <0x07000208>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&s_nmi_pins_a>;
};
sid: sunxi-sid@03006000 {
compatible = "allwinner,sunxi-sid";
device_type = "sid";
reg = <0x0 0x03006000 0 0x1000>;
};
sunxi-sid-ng@03006000 {
compatible = "allwinner,sun50iw11p1-sid";
reg = <0x0 0x03006000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ths_calib: calib@14 {
reg = <0x14 4>;
};
vf_table: vf-table@20 {
reg = <0x20 2>;
};
};
chipid: sunxi-chipid@03006200 {
compatible = "allwinner,sunxi-chipid";
device_type = "chipid";
reg = <0x0 0x03006200 0 0x0200>;
};
timer_arch {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <24000000>;
interrupt-parent = <&gic>;
arm,no-tick-in-suspend;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_SPI 140 4>,
<GIC_SPI 141 4>,
<GIC_SPI 142 4>,
<GIC_SPI 143 4>;
};
dramfreq {
compatible = "allwinner,sunxi-dramfreq";
reg = <0x0 0x04002000 0x0 0x1000>,
<0x0 0x04003000 0x0 0x3000>,
<0x0 0x03001000 0x0 0x1000>;
interrupts = <GIC_SPI 33 0x4>;
/* clocks = <&clk_pll_ddr>; */
status = "okay";
};
aipu@0x03050000 {
compatible = "armchina,zhouyiv1aipu";
reg = <0x0 0x03050000 0x0 0x1000>;
device_type = "aipu";
/*host-aipu-offset = <0x80000000>;*/
/*fpga-freq = <0x0000000F>;*/
cma-reserved-bytes = <0x2600000>;/* 38M CMA*/
/*memory-region=<&aipu_reserved>;*/
clocks = <&clk_pll_periph0x2>,
<&clk_aipu>,
<&clk_aipu_slv>,
<&clk_pll_periph0800m>;
interrupts = <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>;
status = "okay";
};
uboot: uboot {
};
soc: soc@03000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
device_type = "soc";
share_space0: share_space@0x42100000 {
compatible = "allwinner,sun50iw11p1-dsp-share-space";
#address-cells = <1>;
#size-cells = <1>;
device_type = "share_space0";
/* dsp write addr and len */
/* arm write addr and len */
/* dsp log addr and len */
/* reserve */
reg = < 0x42100000 0x00001000
0x42101000 0x00002000
0x42102000 0x0000E000
0x00000000 0x00000000>;
dsp_id = <0>;
status = "disabled";
};
share_space1: share_space@0x42110000 {
compatible = "allwinner,sun50iw11p1-dsp-share-space";
#address-cells = <1>;
#size-cells = <1>;
device_type = "share_space1";
/* dsp write addr and len */
/* arm write addr and len */
/* dsp log addr and len */
/* reserve */
reg = < 0x42110000 0x00001000
0x42111000 0x00002000
0x42112000 0x0000E000
0x00000000 0x00000000>;
dsp_id = <1>;
status = "disabled";
};
dma0:dma-controller@03002000 {
compatible = "allwinner,sun50i-dma";
reg = <0x0 0x03002000 0x0 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, /* non secure */
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* secure */
clocks = <&clk_dma>;
#dma-cells = <1>;
};
mbus0:mbus-controller@047fa000 {
compatible = "allwinner,sun50i-mbus";
reg = <0x0 0x03102000 0x0 0x1000>;
#mbus-cells = <1>;
};
hwspinlock: hwspinlock@3004000 {
compatible = "allwinner,sunxi-hwspinlock";
/*
clocks = <&clk_hwspinlock_rst>, <&clk_hwspinlock_bus>;
clock-names = "clk_hwspinlock_rst", "clk_hwspinlock_bus";
*/
reg = <0x0 0x03004000 0x0 0x1000>;
num-locks = <8>; /* the number hwspinlock we needed, max 32 */
status = "okay";
};
box_start_os: box_start_os0 {
compatible = "allwinner,box_start_os";
start_type = <0x0>;
irkey_used = <0x0>;
pmukey_used = <0x0>;
pmukey_num = <0x0>;
led_power = <0x0>;
led_state = <0x0>;
status = "disable";
};
soc_timer0: timer@02000000 {
compatible = "allwinner,sun4i-a10-timer";
device_type = "soc_timer";
reg = <0x0 0x02000000 0x0 0x400>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
/* On FPGA, timer can only use the losc.
* On IC, timer should use the hosc.
*/
clocks = <&clk_hosc>;
/*clocks = <&clk_losc>; */
};
rtc: rtc@07090000 {
compatible = "allwinner,sunxi-rtc";
device_type = "rtc";
reg = <0x0 0x07090000 0x0 0x400>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
gpr_offset = <0x100>;
gpr_len = <8>;
gpr_cur_pos = <6>;
gpr_bootcount_pos = <7>;
clocks = <&clk_rtc>;
auto_switch;
wakeup-source;
};
wdt: watchdog@020000a0 {
compatible = "allwinner,sun50i-wdt";
reg = <0x0 0x020000a0 0x0 0x20>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
};
uart0: uart@02500000 {
compatible = "allwinner,sun50i-uart";
device_type = "uart0";
reg = <0x0 0x02500000 0x0 0x400>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
sunxi,uart-fifosize = <64>;
clocks = <&clk_uart0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-1 = <&uart0_pins_b>;
uart0_port = <0>;
uart0_type = <2>;
status = "okay";
};
uart1: uart@02500400 {
compatible = "allwinner,sun50i-uart";
device_type = "uart1";
reg = <0x0 0x02500400 0x0 0x400>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
sunxi,uart-fifosize = <256>;
clocks = <&clk_uart1>;
use_rxdma = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart1_pins_a>;
pinctrl-1 = <&uart1_pins_b>;
uart1_port = <1>;
uart1_type = <4>;
status = "okay";
};
uart2: uart@02500800 {
compatible = "allwinner,sun50i-uart";
device_type = "uart2";
reg = <0x0 0x02500800 0x0 0x400>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
sunxi,uart-fifosize = <256>;
clocks = <&clk_uart2>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart2_pins_a>;
pinctrl-1 = <&uart2_pins_b>;
uart2_port = <2>;
uart2_type = <4>;
status = "disabled";
};
uart3: uart@02500c00 {
compatible = "allwinner,sun50i-uart";
device_type = "uart3";
reg = <0x0 0x02500c00 0x0 0x400>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
sunxi,uart-fifosize = <256>;
clocks = <&clk_uart3>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart3_pins_a>;
pinctrl-1 = <&uart3_pins_b>;
uart3_port = <3>;
uart3_type = <4>;
status = "disabled";
};
uart4: uart@07080000 {
compatible = "allwinner,sun50i-uart";
device_type = "uart4";
reg = <0x0 0x07080000 0x0 0x400>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
sunxi,uart-fifosize = <64>;
clocks = <&clk_r_uart>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&s_uart0_pins_a>;
pinctrl-1 = <&s_uart0_pins_b>;
uart3_port = <4>;
uart3_type = <2>;
status = "disabled";
};
s_cir0: s_cir@07040000 {
compatible = "allwinner,s_cir";
reg = <0x0 0x07040000 0x0 0x400>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&s_cir0_pins_a>;
pinctrl-1 = <&s_cir0_pins_b>;
clocks = <&clk_hosc>,<&clk_cpurcir>;
supply = "";
supply_vol = "";
status = "disabled";
};
ir1: ir@0x02003000 {
compatible = "allwinner,ir_tx";
reg = <0x0 0x02003000 0x0 0x400>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_hosc>, <&clk_irtx>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&ir0_pins_a>;
pinctrl-1 = <&ir0_pins_b>;
status = "disabled";
};
twi2: twi@0x07081400{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun50i-twi";
device_type = "s_twi0";
reg = <0x0 0x07081400 0x0 0x400>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_r_twi0>;
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&s_twi0_pins_a>;
pinctrl-1 = <&s_twi0_pins_b>;
twi_drv_used = <1>;
status = "okay";
};
twi0: twi@0x02502000{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun50i-twi";
device_type = "twi0";
reg = <0x0 0x02502000 0x0 0x400>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi0>;
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&twi0_pins_a>;
pinctrl-1 = <&twi0_pins_b>;
status = "disabled";
};
twi1: twi@0x02502400{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun50i-twi";
device_type = "twi1";
reg = <0x0 0x02502400 0x0 0x400>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi1>;
clock-frequency = <200000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&twi1_pins_a>;
pinctrl-1 = <&twi1_pins_b>;
status = "okay";
};
usbc0:usbc0@0 {
device_type = "usbc0";
compatible = "allwinner,sunxi-otg-manager";
usb_port_type = <2>;
usb_detect_type = <1>;
usb_id_gpio;
usb_det_vbus_gpio;
usb_drv_vbus_gpio;
usb_regulator_io = "nocare";
usb_wakeup_suspend = <0>;
usb_serial_unique = <0>;
usb_serial_number = "20080411";
rndis_wceis = <1>;
status = "okay";
};
udc:udc-controller@0x04100000 {
compatible = "allwinner,sunxi-udc";
reg = <0x0 0x04100000 0x0 0x1000>, /*udc base*/
<0x0 0x00000000 0x0 0x100>; /*sram base*/
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy0>, <&clk_usbotg0>;
status = "okay";
};
ehci0:ehci0-controller@0x04101000 {
compatible = "allwinner,sunxi-ehci0";
reg = <0x0 0x04101000 0x0 0xFFF>, /*hci0 base*/
<0x0 0x00000000 0x0 0x100>, /*sram base*/
<0x0 0x04100000 0x0 0x1000>; /*otg base*/
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy0>, <&clk_usbehci0>;
hci_ctrl_no = <0>;
status = "okay";
};
ohci0:ohci0-controller@0x04101400 {
compatible = "allwinner,sunxi-ohci0";
reg = <0x0 0x04101000 0x0 0xFFF>, /*hci0 base*/
<0x0 0x00000000 0x0 0x100>, /*sram base*/
<0x0 0x04100000 0x0 0x1000>; /*otg base*/
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy0>, <&clk_usbohci0>, <&clk_usbohci0_12m>, <&clk_osc48md4>, <&clk_hosc>, <&clk_losc>;
hci_ctrl_no = <0>;
status = "okay";
};
usbc1:usbc1@0 {
device_type = "usbc1";
usb_drv_vbus_gpio;
usb_regulator_io = "nocare";
usb_wakeup_suspend = <0>;
status = "okay";
};
ehci1:ehci1-controller@0x04201000 {
compatible = "allwinner,sunxi-ehci1";
reg = <0x0 0x04201000 0x0 0xFFF>, /*hci1 base*/
<0x0 0x00000000 0x0 0x100>, /*sram base*/
<0x0 0x04200000 0x0 0x1000>; /*otg base*/
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy1>, <&clk_usbehci1>;
hci_ctrl_no = <1>;
status = "okay";
};
ohci1:ohci1-controller@0x04201400 {
compatible = "allwinner,sunxi-ohci1";
reg = <0x0 0x04201000 0x0 0xFFF>, /*hci1 base*/
<0x0 0x00000000 0x0 0x100>, /*sram base*/
<0x0 0x04200000 0x0 0x1000>; /*otg base*/
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy1>, <&clk_usbohci1>, <&clk_usbohci1_12m>, <&clk_osc48md4>, <&clk_hosc>, <&clk_losc>;
hci_ctrl_no = <1>;
status = "okay";
};
daudio0:daudio@0x02004000 {
compatible = "allwinner,sunxi-daudio";
reg = <0x0 0x02004000 0x0 0x74>;
clocks = <&clk_pll_audio1>,<&clk_pll_audio1x4>,<&clk_i2s0>,
<&clk_pll_audio0>,<&clk_pll_audio0_div2>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "i2s0-irq";
pinctrl-names = "default","default","sleep";
pinctrl-0 = <&daudio0_pins_a>;
pinctrl-1 = <&daudio0_pins_b>;
pinctrl-2 = <&daudio0_pins_c>;
clk_num = <0x5>;
pll_num = <0x2>;
pinctrl_used = <0x1>;
pcm_lrck_period = <0x80>;
slot_width_select = <0x20>;
frametype = <0x00>;
tdm_config = <0x01>;
tdm_num = <0x0>;
mclk_div = <0x0>;
clk_parent = <0x3>;
capture_cma = <128>;
playback_cma = <128>;
tx_num = <1>;/* 1:tx0 2:tx0+tx1 3:tx0+tx1+tx2 4:tx0+tx1+tx2+tx3 */
tx_chmap1 = <0x76543210>;
tx_chmap0 = <0xFEDCBA98>;
rx_num = <4>;
rx_chmap3 = <0x03020100>;
rx_chmap2 = <0x07060504>;
rx_chmap1 = <0x0B0A0908>;
rx_chmap0 = <0x0F0E0D0C>;
device_type = "daudio0";
status = "disabled";
};
daudio1:daudio@0x02005000 {
compatible = "allwinner,sunxi-daudio";
reg = <0x0 0x02005000 0x0 0x74>;
clocks = <&clk_pll_audio1>,<&clk_pll_audio1x4>,<&clk_i2s1>,
<&clk_pll_audio0>,<&clk_pll_audio0_div2>;
pinctrl-names = "default","default","sleep";
pinctrl-0 = <&daudio1_pins_a>;
pinctrl-1 = <&daudio1_pins_b>;
pinctrl-2 = <&daudio1_pins_c>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "i2s1-irq";
clk_num = <0x5>;
pll_num = <0x2>;
pinctrl_used = <0x1>;
pcm_lrck_period = <0x20>;
slot_width_select = <0x20>;
frametype = <0x00>;
tdm_config = <0x01>;
tdm_num = <0x1>;
mclk_div = <0x0>;
clk_parent = <0x3>;
capture_cma = <128>;
playback_cma = <128>;
tx_num = <1>;/* 1:tx0 2:tx0+tx1 3:tx0+tx1+tx2 4:tx0+tx1+tx2+tx3 */
tx_chmap1 = <0x76543210>;
tx_chmap0 = <0xFEDCBA98>;
rx_num = <4>;
rx_chmap3 = <0x03020100>;
rx_chmap2 = <0x07060504>;
rx_chmap1 = <0x0B0A0908>;
rx_chmap0 = <0x0F0E0D0C>;
device_type = "daudio1";
status = "disabled";
};
daudio2:daudio@0x02006000 {
compatible = "allwinner,sunxi-daudio";
reg = <0x0 0x02006000 0x0 0x74>;
clocks = <&clk_pll_audio1>,<&clk_pll_audio1x4>,<&clk_i2s2>,
<&clk_pll_audio0>,<&clk_pll_audio0_div2>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "i2s2-irq";
clk_num = <0x5>;
pll_num = <0x2>;
pinctrl_used = <0x0>;
pcm_lrck_period = <0x80>;
slot_width_select = <0x20>;
frametype = <0x00>;
tdm_config = <0x01>;
tdm_num = <0x2>;
mclk_div = <0x0>;
clk_parent = <0x3>;
capture_cma = <256>;
playback_cma = <256>;
tx_num = <1>;/* 1:tx0 2:tx0+tx1 3:tx0+tx1+tx2 4:tx0+tx1+tx2+tx3 */
tx_chmap1 = <0x76543210>;
tx_chmap0 = <0xFEDCBA98>;
rx_num = <4>;
rx_chmap3 = <0x03020100>;
rx_chmap2 = <0x07060504>;
rx_chmap1 = <0x0B0A0908>;
rx_chmap0 = <0x0F0E0D0C>;
device_type = "daudio2";
status = "disabled";
};
sunxi_rpaf_dsp0:rpaf-dsp@0 {
compatible = "allwinner,rpaf-dsp0";
device_type = "sunxi_rpaf_dsp0";
dsp_id = <0x0>;
status = "okay";
};
sunxi_rpaf_dsp1:rpaf-dsp@1 {
compatible = "allwinner,rpaf-dsp1";
device_type = "sunxi_rpaf_dsp1";
dsp_id = <0x1>;
status = "okay";
};
r_daudio0:daudio@0x07033000 {
compatible = "allwinner,sunxi-daudio";
reg = <0x0 0x07033000 0x0 0xA0>;
clocks = <&clk_pll_audio1>,<&clk_pll_audio1x4>,<&clk_r_i2s0>,
<&clk_pll_audio0>,<&clk_pll_audio0_div2>,<&clk_r_i2s0_asrc>;
pinctrl-names = "default","default","sleep";
pinctrl-0 = <&s_daudio0_pins_a>;
pinctrl-1 = <&s_daudio0_pins_b>;
pinctrl-2 = <&s_daudio0_pins_c>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "r_i2s0-irq";
clk_num = <0x5>;
pll_num = <0x2>;
pinctrl_used = <0x1>;
tdm_num = <0x3>;
clk_parent = <0x3>;
/* eg:0 snddaudio0, 1 snddaudio1 */
dsp_daudio = <0x0>;
/* eg:0 sndcodec; 1 snddmic; 2 snddaudio0; */
dsp_card = <0x2>;
/* default is 0, for reserved */
dsp_device = <0x0>;
/* dsp config */
mclk_div = <0x01>;
frametype = <0x00>;
tdm_config = <0x01>;
sign_extend = <0x00>;
tx_data_mode = <0x00>;
rx_data_mode = <0x00>;
msb_lsb_first = <0x00>;
pcm_lrck_period = <0x80>;
slot_width_select = <0x20>;
capture_cma = <64>;
playback_cma = <32>;
tx_num = <1>;
tx_chmap1 = <0x76543210>;
tx_chmap0 = <0xFEDCBA98>;
rx_num = <4>;
rx_chmap3 = <0x03020100>;
rx_chmap2 = <0x07060504>;
rx_chmap1 = <0x0B0A0908>;
rx_chmap0 = <0x0F0E0D0C>;
rx_sync_en = <0x0>;
audio_format = <0x01>;
daudio_master = <0x04>;
signal_inversion = <0x01>;
daudio_used = <0x0>; /* be equal to status = "disabled" for dsp */
device_type = "r_daudio0";
status = "disabled";
};
r_daudio1:daudio@0x07034000 {
compatible = "allwinner,sunxi-daudio";
reg = <0x0 0x07033000 0x0 0x74>;
clocks = <&clk_pll_audio1>,<&clk_pll_audio1x4>,<&clk_r_i2s1>,
<&clk_pll_audio0>,<&clk_pll_audio0_div2>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "r_i2s1-irq";
clk_num = <0x5>;
pll_num = <0x2>;
pinctrl_used = <0x0>;
tdm_num = <0x4>;
clk_parent = <0x3>;
/* dsp config */
mclk_div = <0x01>;
frametype = <0x00>;
tdm_config = <0x01>;
sign_extend = <0x00>;
tx_data_mode = <0x00>;
rx_data_mode = <0x00>;
msb_lsb_first = <0x00>;
pcm_lrck_period = <0x100>;
slot_width_select = <0x20>;
capture_cma = <64>;
playback_cma = <64>;
tx_num = <1>;
tx_chmap1 = <0x76543210>;
tx_chmap0 = <0xFEDCBA98>;
rx_num = <4>;
rx_chmap3 = <0x03020100>;
rx_chmap2 = <0x07060504>;
rx_chmap1 = <0x0B0A0908>;
rx_chmap0 = <0x0F0E0D0C>;
rx_sync_en = <0x0>;
audio_format = <0x04>;
daudio_master = <0x04>;
signal_inversion = <0x03>;
daudio_used = <0x1>; /* be equal to status = "okay" for dsp */
device_type = "r_daudio1";
status = "disabled";
};
spdif:spdif-controller@0x02002c00{
compatible = "allwinner,sunxi-spdif";
reg = <0x0 0x02002c00 0x0 0x40>;
clocks = <&clk_pll_audio1>,<&clk_pll_audio1x4>,<&clk_spdif>,
<&clk_pll_audio0>,<&clk_pll_audio0_div2>,<&clk_pll_periph0>,<&clk_spdifrx>;
pinctrl-names = "default","default","sleep";
pinctrl-0 = <&spdif_pins_a>;
pinctrl-1 = <&spdif_pins_b>;
pinctrl-2 = <&spdif_pins_c>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "spdif-irq";
clk_parent = <0x3>;
clk_num = <0x7>;
pll_num = <0x3>;
capture_cma = <128>;
playback_cma = <128>;
device_type = "spdif";
status = "disabled";
};
r_dmic:dmic-controller@0x07031000{
compatible = "allwinner,sunxi-dmic";
reg = <0x0 0x07031000 0x0 0x50>;
clocks = <&clk_pll_audio1>,<&clk_pll_audio1x4>,<&clk_dmic>,
<&clk_pll_audio0>,<&clk_pll_audio0_div2>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&s_dmic_pins_a>;
pinctrl-1 = <&s_dmic_pins_b>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dmic-irq";
clk_parent = <0x3>;
clk_num = <0x5>;
pll_num = <0x2>;
/* dsp config */
capture_cma = <64>;
rx_chmap = <0x76543210>;
data_vol = <0xB0>;
rx_sync_en = <0x0>;
dsp_card = <0x1>;
device_type = "r_dmic";
status = "disabled";
};
codec:codec@0x07032000 {
compatible = "allwinner,sunxi-internal-codec";
reg = <0x0 0x07032000 0x0 0x334>;/*digital baseadress*/
clocks = <&clk_pll_audio0_div2>,<&clk_pll_audio1>,
<&clk_codec_adc>,<&clk_codec_dac>,
<&clk_pll_audio0_div5>;
pa_ctl_level = <0x1>;
digital_vol = <0x0>;
/* dsp config */
playback_cma = <32>;
capture_cma = <64>;
pa_msleep_time = <0x64>;
spk_vol = <0xA>;
mic1gain = <0x13>;
mic2gain = <0x13>;
mic3gain = <0x13>;
mic4gain = <0x13>;
mic5gain = <0x0>;
mic6gain = <0x0>;
mic_num = <0x6>;
adcdrc_cfg = <0x00>;
adchpf_cfg = <0x01>;
dacdrc_cfg = <0x00>;
dachpf_cfg = <0x00>;
rx_sync_en = <0x0>;
device_type = "codec";
status = "disabled";
};
cpudai:cpudai-controller@0x07032000 {
compatible = "allwinner,sunxi-internal-cpudai";
reg = <0x0 0x07032000 0x0 0x330>;/*digital baseadress*/
playback_cma = <128>;
capture_cma = <256>;
dsp_card = <0x0>;
device_type = "cpudai";
status = "disabled";
};
mad:mad@0x07097000{
compatible = "allwinner,sunxi-mad";
reg = <0x0 0x07097000 0x0 0x3ff>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "lpsd-irq", "mad-irq";
wakeup-source;
clocks = <&clk_pll_audio1>,<&clk_hosc>,<&clk_lpsd>,
<&clk_mad>,<&clk_mad_sram>,<&clk_mad_cfg>;
lpsd_clk_src_cfg = <0x0>;
/* IO:0x1, MEMORY:0x0 */
standby_sram_io_type = <0x1>;
lpsd_th = <0x4b0>;
lpsd_rrun = <0x4d>;
lpsd_rstop = <0x80>;
lpsd_ecnt = <2>;
device_type = "mad";
status = "disabled";
};
sndcodec:sound@0 {
compatible = "allwinner,sunxi-codec-machine";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "audiocodec-irq";
sunxi,cpudai-controller = <&cpudai>;
sunxi,audio-codec = <&codec>;
device_type = "sndcodec";
status = "disabled";
};
snddaudio0:sound@1{
compatible = "allwinner,sunxi-daudio0-machine";
sunxi,daudio-controller = <&daudio0>;
daudio_master = <0x04>;
audio_format = <0x01>;
signal_inversion = <0x01>;
device_type = "snddaudio0";
status = "disabled";
};
snddaudio1:sound@2{
compatible = "allwinner,sunxi-daudio1-machine";
sunxi,daudio-controller = <&daudio1>;
daudio_master = <0x04>;
audio_format = <0x01>;
signal_inversion = <0x01>;
device_type = "snddaudio1";
status = "disabled";
};
snddaudio2:sound@3{
compatible = "allwinner,sunxi-daudio2-machine";
sunxi,daudio-controller = <&daudio2>;
daudio_master = <0x04>;
audio_format = <0x01>;
signal_inversion = <0x01>;
device_type = "snddaudio2";
status = "disabled";
};
snddaudio3:sound@4{
compatible = "allwinner,sunxi-daudio3-machine";
sunxi,daudio-controller = <&r_daudio0>;
device_type = "snddaudio3";
status = "disabled";
};
snddaudio4:sound@5{
compatible = "allwinner,sunxi-daudio4-machine";
sunxi,daudio-controller = <&r_daudio1>;
device_type = "snddaudio4";
status = "disabled";
};
sndspdif:sound@6{
compatible = "allwinner,sunxi-spdif-machine";
sunxi,spdif-controller = <&spdif>;
device_type = "sndspdif";
status = "disabled";
};
snddmic:sound@7{
compatible = "allwinner,sunxi-dmic-machine";
sunxi,dmic-controller = <&r_dmic>;
device_type = "snddmic";
status = "disabled";
};
spi0: spi@04025000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun50i-spi";
device_type = "spi0";
reg = <0x0 0x04025000 0x0 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_periph0>, <&clk_spi0>;
clock-frequency = <100000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi0_pins_a &spi0_pins_b>;
pinctrl-1 = <&spi0_pins_c>;
spi0_cs_number = <1>;
spi0_cs_bitmap = <1>;
status = "disabled";
spi-nand {
compatible = "spi-nand";
spi-max-frequency=<0x5F5E100>;
reg = <0x0>;
spi-rx-bus-width=<0x04>;
spi-tx-bus-width=<0x04>;
status="disabled";
};
};
spi1: spi@04026000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun50i-spi";
device_type = "spi1";
reg = <0x0 0x04026000 0x0 0x1000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_periph0>, <&clk_spi1>;
clock-frequency = <100000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi1_pins_a &spi1_pins_b>;
pinctrl-1 = <&spi1_pins_c>;
spi1_cs_number = <1>;
spi1_cs_bitmap = <1>;
status = "disabled";
};
ledc: ledc@0x02002800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sunxi-leds";
reg = <0x0 0x02002800 0x0 0x100>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ledcirq";
clocks = <&clk_ledc>, <&clk_cpuapb>;
clock-names = "clk_ledc", "clk_cpuapb";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&ledc_pins_a>;
pinctrl-1 = <&ledc_pins_b>;
led_count = <34>;
output_mode = "GRB";
reset_ns = <84>;
t1h_ns = <800>;
t1l_ns = <450>;
t0h_ns = <400>;
t0l_ns = <850>;
wait_time0_ns = <84>;
wait_time1_ns = <84>;
wait_data_time_ns = <600000>;
};
scr0:smartcard@0x02505000{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sunxi-scr";
device_type = "scr0";
reg = <0x0 0x02505000 0x0 0x100>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_scr0>, <&clk_apb2>;
clock-frequency = <24000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&scr0_pins_a &scr0_pins_b>;
pinctrl-1 = <&scr0_pins_c>;
status = "disabled";
};
sdc0: sdmmc@04020000 {
compatible = "allwinner,sunxi-mmc-v5p3x";
device_type = "sdc0";
reg = <0x0 0x04020000 0x0 0x1000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_hosc>,
<&clk_pll_periph0x2>,
<&clk_sdmmc0_mod>,
<&clk_sdmmc0_bus>,
<&clk_sdmmc0_rst>;
clock-names = "osc24m","pll_periph","mmc","ahb","rst";
pinctrl-names = "default","sleep";
pinctrl-0 = <&sdc0_pins_a>;
pinctrl-1 = <&sdc0_pins_b>;
bus-width = <4>;
cap-wait-while-busy;
sunxi-power-save-mode;
ctl-spec-caps = <0x8>;
no-sdio;
status = "okay";
};
sdc1: sdmmc@04021000 {
compatible = "allwinner,sunxi-mmc-v5p3x";
device_type = "sdc1";
reg = <0x0 0x04021000 0x0 0x1000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_hosc>,
<&clk_pll_periph0x2>,
<&clk_sdmmc1_mod>,
<&clk_sdmmc1_bus>,
<&clk_sdmmc1_rst>;
clock-names = "osc24m","pll_periph","mmc","ahb","rst";
pinctrl-names = "default","sleep";
pinctrl-0 = <&sdc1_pins_a>;
pinctrl-1 = <&sdc1_pins_b>;
max-frequency = <50000000>;
bus-width = <4>;
/*broken-cd;*/
/*cd-inverted*/
/*cd-gpios = <&pio PG 6 6 1 2 0>;*/
/* vmmc-supply = <&reg_3p3v>;*/
/* vqmc-supply = <&reg_3p3v>;*/
/* vdmc-supply = <&reg_3p3v>;*/
/*vmmc = "vcc-card";*/
/*vqmc = "";*/
/*vdmc = "";*/
cap-sd-highspeed;
no-mmc;
/*sd-uhs-sdr50;*/
/*sd-uhs-ddr50;*/
/*sd-uhs-sdr104;*/
/*cap-sdio-irq;*/
keep-power-in-suspend;
/*ignore-pm-notify;*/
/*sunxi-power-save-mode;*/
/*sunxi-dly-400k = <1 0 0 0 0>; */
/*sunxi-dly-26M = <1 0 0 0 0>;*/
/*sunxi-dly-52M = <1 0 0 0 0>;*/
sunxi-dly-52M-ddr4 = <1 0 0 0 2>;
/*sunxi-dly-52M-ddr8 = <1 0 0 0 0>;*/
sunxi-dly-104M = <1 0 0 0 1>;
/*sunxi-dly-208M = <1 1 0 0 0>;*/
sunxi-dly-208M = <1 0 0 0 1>;
/*sunxi-dly-104M-ddr = <1 0 0 0 0>;*/
/*sunxi-dly-208M-ddr = <1 0 0 0 0>;*/
ctl-spec-caps = <0x8>;
/*status = "okay";*/
status = "disabled";
};
pwm: pwm@02000c00 {
compatible = "allwinner,sunxi-pwm";
reg = <0x0 0x02000c00 0x0 0x3ff>;
clocks = <&clk_pwm>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
pwm-number = <10>;
pwm-base = <0x0>;
pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>,
<&pwm5>, <&pwm6>, <&pwm7>, <&pwm8>, <&pwm9>;
#pwm-cells = <3>;
};
s_pwm: s_pwm@07020c00 {
compatible = "allwinner,sunxi-pwm";
reg = <0x0 0x07020c00 0x0 0x3ff>;
clocks = <&clk_r_pwm>;
pwm-number = <6>;
pwm-base = <10>;
pwms = <&s_pwm0>, <&s_pwm1>, <&s_pwm2>, <&s_pwm3>,
<&s_pwm4>, <&s_pwm5>;
#pwm-cells = <3>;
};
pwm0: pwm0@02000c00 {
compatible = "allwinner,sunxi-pwm0";
pinctrl-names = "active", "sleep";
reg_base = <0x02000c00>;
};
pwm1: pwm1@02000c00 {
compatible = "allwinner,sunxi-pwm1";
pinctrl-names = "active", "sleep";
reg_base = <0x02000c00>;
};
pwm2: pwm2@02000c00 {
compatible = "allwinner,sunxi-pwm2";
pinctrl-names = "active", "sleep";
reg_base = <0x02000c00>;
};
pwm3: pwm3@02000c00 {
compatible = "allwinner,sunxi-pwm3";
pinctrl-names = "active", "sleep";
reg_base = <0x02000c00>;
};
pwm4: pwm4@02000c00 {
compatible = "allwinner,sunxi-pwm4";
pinctrl-names = "active", "sleep";
reg_base = <0x02000c00>;
};
pwm5: pwm5@02000c00 {
compatible = "allwinner,sunxi-pwm5";
pinctrl-names = "active", "sleep";
reg_base = <0x02000c00>;
};
pwm6: pwm6@02000c00 {
compatible = "allwinner,sunxi-pwm6";
pinctrl-names = "active", "sleep";
reg_base = <0x02000c00>;
};
pwm7: pwm7@02000c00 {
compatible = "allwinner,sunxi-pwm7";
pinctrl-names = "active", "sleep";
reg_base = <0x02000c00>;
};
pwm8: pwm8@02000c00 {
compatible = "allwinner,sunxi-pwm8";
pinctrl-names = "active", "sleep";
reg_base = <0x02000c00>;
};
pwm9: pwm9@02000c00 {
compatible = "allwinner,sunxi-pwm9";
pinctrl-names = "active", "sleep";
reg_base = <0x02000c00>;
};
s_pwm0: s_pwm0@07020c00 {
compatible = "allwinner,sunxi-pwm10";
pinctrl-names = "active", "sleep";
reg_base = <0x07020c00>;
};
s_pwm1: s_pwm1@07020c00 {
compatible = "allwinner,sunxi-pwm11";
pinctrl-names = "active", "sleep";
reg_base = <0x07020c00>;
};
s_pwm2: s_pwm2@07020c00 {
compatible = "allwinner,sunxi-pwm12";
pinctrl-names = "active", "sleep";
reg_base = <0x07020c00>;
};
s_pwm3: s_pwm3@07020c00 {
compatible = "allwinner,sunxi-pwm13";
pinctrl-names = "active", "sleep";
reg_base = <0x07020c00>;
};
s_pwm4: s_pwm4@07020c00 {
compatible = "allwinner,sunxi-pwm14";
pinctrl-names = "active", "sleep";
reg_base = <0x07020c00>;
};
s_pwm5: s_pwm5@07020c00 {
compatible = "allwinner,sunxi-pwm15";
pinctrl-names = "active", "sleep";
reg_base = <0x07020c00>;
};
lcdfb: lcdfb@0 {
compatible = "allwinner,sunxi-lcdfb";
pinctrl-names = "active","sleep";
status = "okay";
};
lcd_fb0: lcd_fb0@0 {
compatible = "allwinner,sunxi-lcd_fb0";
pinctrl-names = "active","sleep";
status = "okay";
};
Vdevice: vdevice@0 {
compatible = "allwinner,sun50i-vdevice";
device_type = "Vdevice";
pinctrl-names = "default";
interrupt-parent = <&pio>;
interrupts = < PG 5 IRQ_TYPE_LEVEL_HIGH>; /* bank offset type */
pinctrl-0 = <&vdevice_pins_a>;
test-gpios = <&pio PG 8 1 2 2 1>; /* PG 8 0=in/1=out drive pull level */
status = "okay";
};
emce: emce@01905000 {
compatible = "allwinner,sunxi-emce";
device_name = "emce";
reg = <0x0 0x01905000 0 0x100>;
clock-frequency = <300000000>; /*300MHZ*/
/*clocks = <&clk_emce>, <&clk_pll_periph0x2>;*/
};
cryptoengine: ce@03040000 {
compatible = "allwinner,sunxi-ce";
device_name = "ce";
reg = <0x0 0x03040000 0x0 0xa0>, /* non-secure space */
<0x0 0x03048000 0x0 0xa0>; /* secure space */
interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, /* non-secure space */
<GIC_SPI 53 IRQ_TYPE_EDGE_RISING>; /* secure space */
clock-frequency = <300000000>; /* 300MHz */
clocks = <&clk_ce>, <&clk_pll_periph0x2>;
};
nand0:nand0@04011000 {
compatible = "allwinner,sun50iw11-nand";
device_type = "nand0";
reg = <0x0 0x04011000 0x0 0x1000>;/* nand0 */
interrupts = <GIC_SPI 38 0x04>;
clocks = <&clk_pll_periph0x2>,<&clk_nand0>,<&clk_nand1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&nand0_pins_a &nand0_pins_b>;
pinctrl-1 = <&nand0_pins_c>;
nand0_regulator1 = "vcc-nand";
nand0_regulator2 = "none";
nand0_cache_level = <0x55aaaa55>;
nand0_flush_cache_num = <0x55aaaa55>;
nand0_capacity_level = <0x55aaaa55>;
nand0_id_number_ctl = <0x55aaaa55>;
nand0_print_level = <0x55aaaa55>;
nand0_p0 = <0x55aaaa55>;
nand0_p1 = <0x55aaaa55>;
nand0_p2 = <0x55aaaa55>;
nand0_p3 = <0x55aaaa55>;
chip_code = "sun50iw11";
status = "disabled";
};
ths: thermal_sensor {
compatible = "allwinner,sun50iw11p1-ths";
reg = <0x0 0x07030400 0x0 0x400>;
clocks = <&clk_ths>;
clock-names = "bus";
nvmem-cells = <&ths_calib>;
nvmem-cell-names = "calibration";
#thermal-sensor-cells = <1>;
};
thermal-zones {
cpu_thermal_zone {
polling-delay-passive = <500>;
polling-delay = <1000>;
thermal-sensors = <&ths 0>;
sustainable-power = <463>;
cpu_trips: trips {
cpu_threshold: trip-point@0 {
temperature = <70000>;
type = "passive";
hysteresis = <0>;
};
cpu_target: trip-point@1 {
temperature = <80000>;
type = "passive";
hysteresis = <0>;
};
cpu_crit: cpu_crit@0 {
temperature = <110000>;
type = "critical";
hysteresis = <0>;
};
};
cooling-maps {
map0 {
trip = <&cpu_target>;
cooling-device = <&cpu0
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
};
};
gpadc:gpadc{
compatible = "allwinner,sunxi-gpadc";
reg = <0x0 0x07030000 0x0 0x400>;
interrupts = <GIC_SPI 116 IRQ_TYPE_NONE>;
clocks = <&clk_gpadc>;
status = "disable";
};
gpadc1:gpadc1{
compatible = "allwinner,sunxi-gpadc";
reg = <0x0 0x07042000 0x0 0x400>;
interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>;
clocks = <&clk_gpadc1>;
status = "disable";
};
keyboard0:keyboard{
compatible = "allwinner,keyboard_1200mv";
reg = <0x0 0x07030800 0x0 0x400>;
clocks = <&clk_lradc>;
interrupts = <GIC_SPI 115 IRQ_TYPE_NONE>;
status = "disabled";
key_cnt = <5>;
key0 = <210 115>;
key1 = <410 114>;
key2 = <590 139>;
key3 = <750 28>;
key4 = <880 102>;
};
gmac0: eth@0x04500000 {
compatible = "allwinner,sunxi-gmac";
reg = <0x0 0x04500000 0x0 0x10000>,
<0x0 0x03000030 0x0 0x4>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gmacirq";
clocks = <&clk_gmac0>, <&clk_gmac0_25m>;
clock-names = "gmac", "ephy";
pinctrl-0 = <&gmac_pins_a>;
pinctrl-1 = <&gmac_pins_b>;
pinctrl-names = "default", "sleep";
phy-rst;
phy-mode;
tx-delay;
rx-delay;
gmac-power0;
gmac-power1;
gmac-power2;
status = "disabled";
};
msgbox0: msgbox0@0x03003000 {
compatible = "sunxi,msgbox";
reg = <0x0 0x03003000 0x0 0x1000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
rpmsg_id = "sunxi,dsp0","sunxi,dsp0-reserved","sunxi,dsp0-info","rpmsg_chrdev";
};
msgbox1: msgbox1@0x03008000 {
compatible = "sunxi,msgbox";
reg = <0x0 0x03008000 0x0 0x1000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
rpmsg_id = "sunxi,dsp1","sunxi,dsp1-reserved","sunxi,dsp1-info","rpmsg_chrdev";
};
dsp0_rproc: dsp0@0 {
compatible = "sunxi,r329-remote-proc";
interrupts = <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>;
clocks = <&clk_dsp0>;
};
dsp1_rproc: dsp1@0 {
compatible = "sunxi,r329-remote-proc";
interrupts = <GIC_SPI 105 IRQ_TYPE_EDGE_RISING>;
clocks = <&clk_dsp1>;
};
};
cpu_opp_table: cpu-opp-table {
compatible = "allwinner,sun50i-operating-points";
nvmem-cells = <&vf_table>;
nvmem-cell-names = "speed";
opp-shared;
opp@480000000 {
opp-hz = /bits/ 64 <480000000>;
opp-microvolt-a0 = <900000>;
opp-microvolt-a1 = <900000>;
opp-microvolt-a2 = <900000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
opp@600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt-a0 = <900000>;
opp-microvolt-a1 = <900000>;
opp-microvolt-a2 = <900000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
opp@720000000 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt-a0 = <900000>;
opp-microvolt-a1 = <900000>;
opp-microvolt-a2 = <900000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
opp@936000000 {
opp-hz = /bits/ 64 <936000000>;
opp-microvolt-a0 = <900000>;
opp-microvolt-a1 = <900000>;
opp-microvolt-a2 = <900000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
opp@1104000000 {
opp-hz = /bits/ 64 <1104000000>;
opp-microvolt-a0 = <900000>;
opp-microvolt-a1 = <900000>;
opp-microvolt-a2 = <900000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
opp@1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt-a0 = <950000>;
opp-microvolt-a1 = <900000>;
opp-microvolt-a2 = <900000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
opp@1320000000 {
opp-hz = /bits/ 64 <1320000000>;
opp-microvolt-a0 = <1000000>;
opp-microvolt-a1 = <900000>;
opp-microvolt-a2 = <900000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
opp@1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt-a0 = <1050000>;
opp-microvolt-a1 = <950000>;
opp-microvolt-a2 = <900000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
opp@1512000000 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt-a0 = <1100000>;
opp-microvolt-a1 = <1000000>;
opp-microvolt-a2 = <950000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
};
};
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