274 lines
9.4 KiB
C
274 lines
9.4 KiB
C
/*
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* (C) Copyright 2007-2011
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* Allwinnertech Technology Co., Ltd. <www.allwinnertech.com>
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*
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* some simple description for this code
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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*/
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#include "nand_scan.h"
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#include "nand_physic_fun.h"
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#include "nand_type_spinand.h"
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struct spi_nand_function spi_nand_function0 = {
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m0_spi_nand_reset, m0_spi_nand_read_status,
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m0_spi_nand_setstatus, m0_spi_nand_getblocklock,
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m0_spi_nand_setblocklock, m0_spi_nand_getotp,
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m0_spi_nand_setotp, m0_spi_nand_getoutdriver,
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m0_spi_nand_setoutdriver, m0_erase_single_block,
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m0_write_single_page, m0_read_single_page,
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};
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struct spi_nand_function spi_nand_function1 = {
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m1_spi_nand_reset, m1_spi_nand_read_status,
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m1_spi_nand_setstatus, m1_spi_nand_getblocklock,
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m1_spi_nand_setblocklock, m1_spi_nand_getotp,
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m1_spi_nand_setotp, m1_spi_nand_getoutdriver,
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m1_spi_nand_setoutdriver, m1_erase_single_block,
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m1_write_single_page, m1_read_single_page,
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};
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struct spi_nand_function spi_nand_function2 = {
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m2_spi_nand_reset, m2_spi_nand_read_status,
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m2_spi_nand_setstatus, m2_spi_nand_getblocklock,
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m2_spi_nand_setblocklock, m2_spi_nand_getotp,
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m2_spi_nand_setotp, m2_spi_nand_getoutdriver,
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m2_spi_nand_setoutdriver, m2_erase_single_block,
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m2_write_single_page, m2_read_single_page,
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};
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struct spi_nand_function spi_nand_function3 = {
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m3_spi_nand_reset, m3_spi_nand_read_status,
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m3_spi_nand_setstatus, m3_spi_nand_getblocklock,
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m3_spi_nand_setblocklock, m3_spi_nand_getotp,
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m3_spi_nand_setotp, m3_spi_nand_getoutdriver,
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m3_spi_nand_setoutdriver, m3_erase_single_block,
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m3_write_single_page, m3_read_single_page,
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};
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//==============================================================================
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// define the physical architecture parameter for all kinds of nand flash
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//==============================================================================
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//==============================================================================
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//============================ GIGADEVICE & MIRA NAND FLASH
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//==============================
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//==============================================================================
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struct __NandPhyInfoPar_t GigaDeviceNandTbl[] = {
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// NAND_CHIP_ID DieCnt SecCnt PagCnt
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// BlkCnt OpOpt Freq mode pagewithbadflag
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// function offset maxerasetime
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// maxecc ecclimit idnumber
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//-------------------------------------------------------------------------
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// no support because of no testing
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//{ {0xc8, 0xf1, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64,
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//1024, 0x007d, 100, 0, 0, &spi_nand_function0 ,
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//1, 50000, 8, 8,
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//0x000000},//GD5F1GQ4UAYIG
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//{ {0xc8, 0xf2, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64,
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//2048, 0x047d, 12, 0, 0, &spi_nand_function0 , 1,
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//50000, 8, 8,
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//0x000001},//GD5F2GQ4UAYIG
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//{ {0xc8, 0xf4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64,
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//4096, 0x007d, 100, 0, 0, &spi_nand_function0 ,
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//1, 50000, 8, 8,
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//0x000002},//GD5F4GQ4UAYIG
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//{ {0xc8, 0xb4, 0x68, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 8, 64,
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//2048, 0x017d, 100, 0, 0, &spi_nand_function2 ,
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//1, 50000, 8, 5,
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//0x000003},//GD5F4GQ4UCYIXX
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//{ {0xc8, 0x20, 0x7f, 0x7f, 0x7f, 0xff, 0xff, 0xff }, 1, 4, 64,
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//512, 0x007d, 100, 0, 1, &spi_nand_function3 , 1,
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//50000, 1, 1,
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//0x000004},//PSU12S20BN
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//------------------------------------------------------------------------------------------------------------------------
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{{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
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0,
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0,
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0,
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0,
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0x0000,
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0,
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0,
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0,
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0,
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0}, // NULL
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};
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//==============================================================================
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//============================ ATO NAND FLASH ==============================
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//==============================================================================
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struct __NandPhyInfoPar_t AtoNandTbl[] = {
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// NAND_CHIP_ID DieCnt SecCnt PagCnt
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// BlkCnt OpOpt Freq mode pagewithbadflag
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// function offset
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// maxerasetime maxecc ecclimit idnumber
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//-------------------------------------------------------------------------
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// no support because of no testing
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//{ {0x9b, 0x12, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64,
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//1024, 0x007c, 100, 0, 0, &spi_nand_function0, 1,
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//100000, 0x010000 },//ATO25D1GA
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//-------------------------------------------------------------------------
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{{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
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0,
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0,
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0,
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0,
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0x0000,
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0,
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0,
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0,
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0,
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0}, // NULL
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};
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//==============================================================================
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//============================ Micron NAND FLASH ==============================
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//==============================================================================
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struct __NandPhyInfoPar_t MicronNandTbl[] = {
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// NAND_CHIP_ID DieCnt SecCnt PagCnt
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// BlkCnt OpOpt Freq mode pagewithbadflag
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// function offset
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// maxerasetime maxecc ecclimit idnumber
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//-------------------------------------------------------------------------
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// no support because of no testing
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//{ {0x2c, 0x12, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64,
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//1024, 0x00fd, 40, 0, 0, &spi_nand_function1, 1,
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//50000, 4, 1, 0x020000
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//},//MT29F1G01AAADD
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// { {0x2c, 0x22, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64,
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// 2048, 0x00fd, 40, 0, 0, &spi_nand_function1, 1,
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// 50000, 4, 1, 0x020001
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// },//MT29F2G01AAAED
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//{ {0x2c, 0x32, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64,
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//4096, 0x00fd, 40, 0, 0, &spi_nand_function1, 1,
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//50000, 4, 1, 0x020002
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//},//MT29F4G01AAADD
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//-------------------------------------------------------------------------
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{{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
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0,
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0,
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0,
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0,
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0x0000,
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0,
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0,
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0,
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0,
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0}, // NULL
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};
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//=============================================================================
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//============================ Mxic NAND FLASH ==============================
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//=============================================================================
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struct __NandPhyInfoPar_t MxicNandTbl[] = {
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// NAND_CHIP_ID DieCnt SecCnt PagCnt
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// BlkCnt OpOpt Freq mode pagewithbadflag
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// function offset
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// maxerasetime maxecc ecclimit idnumber
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//-------------------------------------------------------------------------
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{{0xc2, 0x12, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
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1,
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4,
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64,
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1024,
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0x067c,
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75,
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0,
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1,
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&spi_nand_function0,
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1,
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65000,
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4,
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1,
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0x030000}, // MX35LF1GE4AB
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// no support because of no testing
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{{0xc2, 0x22, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
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1,
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4,
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64,
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2048,
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0x06fc,
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75,
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0,
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1,
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&spi_nand_function1,
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1,
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65000,
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4,
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1,
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0x030001}, // MX35LF2GE4AB
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//---------------------------------------------------------------------
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{{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
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0,
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0,
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0,
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0,
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0x0000,
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0,
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0,
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0,
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0,
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0}, // NULL
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};
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//=============================================================================
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//=========================== Winbond NAND FLASH ==============================
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//=============================================================================
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struct __NandPhyInfoPar_t WinbondNandTbl[] = {
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// NAND_CHIP_ID DieCnt SecCnt PagCnt
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// BlkCnt OpOpt Freq mode pagewithbadflag
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// function offset
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// maxerasetime maxecc ecclimit idnumber
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//-------------------------------------------------------------------------
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//{ {0xef, 0xaa, 0x21, 0xff, 0xff, 0xff, 0xff, 0xff }, 1, 4, 64,
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//1024, 0x007d, 75, 0, 0, &spi_nand_function0, 1,
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//65000, 4, 1, 0x040000
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//},//W25N01GVSF1G
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//-------------------------------------------------------------------------
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{{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
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0,
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0,
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0,
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0,
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0x0000,
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0,
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0,
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0,
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0,
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0}, // NULL
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};
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//=============================================================================
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//============================ DEFAULT NAND FLASH =============================
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//=============================================================================
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struct __NandPhyInfoPar_t DefaultNandTbl[] = {
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// NAND_CHIP_ID DieCnt SecCnt PagCnt
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// BlkCnt OpOpt Freq mode pagewithbadflag
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// function offset
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// maxerasetime maxecc ecclimit idnumber
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//-------------------------------------------------------------------------
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{{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
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0,
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0,
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0,
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0,
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0x0000,
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0,
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0,
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0,
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NULL,
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0,
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0,
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0x000000}, // default
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};
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